SMM.LST 7.8 KB

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  1. SYSTEM-MANAGEMENT MODE Release 60 Last change 03jan99
  2. Copyright (c) 1997,1998,1999 Ralf Brown
  3. ---------------------------------------------
  4. SMM Am486
  5. Format of Am486 SMM State-Save Map:
  6. Offset Size Description (Table S0001)
  7. FE00h reserved
  8. FEE4h DWORD DR3
  9. FEE8h DWORD DR2
  10. FEECh DWORD DR1
  11. FEF0h DWORD DR0
  12. FEF4h DWORD CR2
  13. FEF8h DWORD SMM state dump base address
  14. fEFCh DWORD SMM revision ID (see #S0004)
  15. FF00h WORD I/O restart
  16. (set to 00FFh to re-execute trapped I/O)
  17. FF02h WORD halt auto restart
  18. (bit 0 set on entry if SMI during HLT)
  19. (set to 00FFh to restart from HLT)
  20. FF04h DWORD I/O trap word (see #S0002)
  21. FF08h DWORD reserved
  22. FF0Ch DWORD reserved
  23. FF10h DWORD previous EIP
  24. FF14h 5 DWORDs ???
  25. FF28h DWORD reserved
  26. FF2Ch DWORD reserved
  27. FF30h DWORD ES limit
  28. FF34h DWORD ES base
  29. FF38h DWORD ES attributes
  30. FF3Ch DWORD CS limit
  31. FF40h DWORD CS base
  32. FF44h DWORD CS attributes
  33. FF48h DWORD SS limit
  34. FF4Ch DWORD SS base
  35. FF50h DWORD SS attributes
  36. FF54h DWORD DS limit
  37. FF58h DWORD DS base
  38. FF5Ch DWORD DS attributes
  39. FF60h DWORD FS limit
  40. FF64h DWORD FS base
  41. FF68h DWORD FS attributes
  42. FF6Ch DWORD GS limit
  43. FF70h DWORD GS base
  44. FF74h DWORD GS attributes
  45. FF78h DWORD LDT limit
  46. FF7Ch DWORD LDT base
  47. FF80h DWORD LDT attribute
  48. FF84h DWORD GDT limit
  49. FF88h DWORD GDT base
  50. FF8Ch DWORD GDT attribute
  51. FF90h DWORD IDT limit
  52. FF94h DWORD IDT base
  53. FF98h DWORD IDT attribute
  54. FF9Ch DWORD TSS limit
  55. FFA0h DWORD TSS base
  56. FFA4h DWORD TSS attribute
  57. FFA8h WORD ES
  58. FFAAh WORD unused???
  59. FFACh WORD CS
  60. FFAEh WORD unused???
  61. FFB0h WORD SS
  62. FFB2h WORD unused???
  63. FFB4h WORD DS
  64. FFB6h WORD unused???
  65. FFB8h WORD FS
  66. FFBAh WORD unused???
  67. FFBCh WORD GS
  68. FFBEh WORD unused???
  69. FFC0h DWORD LDTR
  70. FFC4h DWORD TR
  71. FFC8h DWORD DR7
  72. FFCCh DWORD DR6
  73. FFD0h DWORD EAX
  74. FFD4h DWORD ECX
  75. FFD8h DWORD EDX
  76. FFDCh DWORD EBX
  77. FFE0h DWORD ESP
  78. FFE4h DWORD EBP
  79. FFE8h DWORD ESI
  80. FFECh DWORD EDI
  81. FFF0h DWORD EIP
  82. FFF4h DWORD EFLAGS
  83. FFF8h DWORD CR3
  84. FFFCh DWORD CR0
  85. SeeAlso: #S0003
  86. Bitfields for AMD Am486 I/O trap word:
  87. Bit(s) Description (Table S0002)
  88. 31-16 I/O address
  89. 15-2 reserved
  90. 1 valid I/O instruction
  91. 0 direction
  92. SeeAlso: #S0001
  93. ---------------------------------------------
  94. SMM AMD-K5
  95. Format of AMD K5 SMM State-Save Area:
  96. Offset Size Description (Table S0003)
  97. FE00h reserved
  98. FEF8h DWORD SMM base address
  99. (may be set to any multiple of 32K; initially 00030000h)
  100. FEFCh DWORD SMM revision identifier (see #S0004)
  101. FF00h WORD I/O trap restart slot (see #S0007)
  102. FF02h WORD HLT restart slot (see #S0005)
  103. FF04h DWORD I/O restart EDI
  104. FF08h DWORD I/O restart ECX
  105. FF0Ch DWORD I/O restart ESI
  106. FF10h DWORD CR4
  107. FF14h DWORD CR2
  108. FF18h 3 DWORDs reserved
  109. FF24h DWORD ES limit
  110. FF28h DWORD ES base
  111. FF2Ch DWORD ES attributes
  112. FF30h DWORD CS limit
  113. FF34h DWORD CS base
  114. FF38h DWORD CS attributes
  115. FF3Ch DWORD SS limit
  116. FF40h DWORD SS base
  117. FF44h DWORD SS attributes
  118. FF48h DWORD DS limit
  119. FF4Ch DWORD DS base
  120. FF50h DWORD DS attributes
  121. FF54h DWORD FS limit
  122. FF58h DWORD FS base
  123. FF5Ch DWORD FS attributes
  124. FF60h DWORD GS limit
  125. FF64h DWORD GS base
  126. FF68h DWORD GS attributes
  127. FF6Ch DWORD LDT limit
  128. FF70h DWORD LDT base
  129. FF74h DWORD LDT attributes
  130. FF78h DWORD TSS limit
  131. FF7Ch DWORD TSS base
  132. FF80h DWORD TSS attributes
  133. FF84h DWORD GDT limit
  134. FF88h DWORD GDT base
  135. FF8Ch DWORD IDT limit
  136. FF90h DWORD IDT base
  137. FF94h 2 DWORDs reserved
  138. FF9Ch DWORD I/O trap EIP
  139. FFA0h DWORD reserved
  140. FFA4h DWORD I/O trap DWORD (see #S0006)
  141. FFA8h WORD ES
  142. FFAAh WORD unused???
  143. FFACh WORD CS
  144. FFAEh WORD unused???
  145. FFB0h WORD SS
  146. FFB2h WORD unused???
  147. FFB4h WORD DS
  148. FFB6h WORD unused???
  149. FFB8h WORD FS
  150. FFBAh WORD unused???
  151. FFBCh WORD GS
  152. FFBEh WORD unused???
  153. FFC0h DWORD LDTR
  154. FFC4h DWORD TR
  155. FFC8h DWORD DR7
  156. FFCCh DWORD DR6
  157. FFD0h DWORD EAX
  158. FFD4h DWORD ECX
  159. FFD8h DWORD EDX
  160. FFDCh DWORD EBX
  161. FFE0h DWORD ESP
  162. FFE4h DWORD EBP
  163. FFE8h DWORD ESI
  164. FFECh DWORD EDI
  165. FFF0h DWORD EIP
  166. FFF4h DWORD EFLAGS
  167. FFF8h DWORD CR3
  168. FFFCh DWORD CR0
  169. SeeAlso: #S0001
  170. Bitfields for AMD K5 SMM Revision Identifier:
  171. Bit(s) Description (Table S0004)
  172. 31-18 reserved (0)
  173. 17 SMM base address relocation available (always 1 [enabled] on K5)
  174. 16 I/O trap restart supported (always 1 on K5)
  175. 15-0 SMM revision level (currently 0000h)
  176. SeeAlso: #S0003
  177. Bitfields for AMD K5 Halt Restart Slot:
  178. Bit(s) Description (Table S0005)
  179. 15-1 undefined
  180. 0 (on SMM entry) entered SMM from Halt state
  181. (at RSM) return to Halt state instead of state in SMM state-save area
  182. SeeAlso: #S0003
  183. Bitfields for AMD K5 I/O Trap DWORD:
  184. Bit(s) Description (Table S0006)
  185. 31-16 I/O port address
  186. 15 I/O was string operation (INS,OUTS,etc.)
  187. 14-2 reserved
  188. 1 valid I/O instruction
  189. 0 direction (0 = output, 1 = input)
  190. SeeAlso: #S0003,#S0007
  191. Bitfields for AMD K5 I/O Trap Restart Slot:
  192. Bit(s) Description (Table S0007)
  193. 31-16 reserved
  194. 15-0 I/O instruction restart on RSM
  195. 0000h resume at next instruction following trapped I/O instruction
  196. (default on SMM entry)
  197. 00FFh re-execute the trapped I/O instruction
  198. Note: before changing the restart value, check that the I/O instruction is
  199. actually valid (see #S0006)
  200. SeeAlso: #S0003,#S0006
  201. ---------------------------------------------
  202. SMM Pentium
  203. Format of Pentium State Dump record:
  204. Offset Size Description (Table S0008)
  205. FE00h 248 BYTEs officially reserved, actually unused
  206. FEF8h DWORD state dump base address (must be multiple of 32K)
  207. FEFCh DWORD SMM revision identifier
  208. bits 15-0: SMM revision level
  209. bit 16: I/O trap extension is present (offset FF00h)
  210. bit 17: SMM base relocation supported (offset FEF8h)
  211. bits 31-18: reserved
  212. FF00h WORD I/O Trap restart
  213. (set to 00FFh to re-execute trapped I/O)
  214. FF02h WORD Halt auto-restart
  215. (bit 0 set on entry if SMI during HLT; if handler clears it,
  216. the CPU returns to the instruction after the interrupted HLT
  217. rather than to the HLT instruction)
  218. FF04h DWORD (undoc) I/O restart EDI / CR0
  219. FF08h DWORD (undoc) I/O restart ECX
  220. FF0Ch DWORD (undoc) I/O restart ESI
  221. FF10h DWORD (undoc) I/O restart EIP
  222. FF14h 16 BYTEs unused
  223. FF24h WORD (undoc) alternate DR6
  224. FF26h WORD (undoc) RSM control
  225. if bit 0 set on return, the low word of DR6 is loaded from FF26h
  226. instead of FFCCh
  227. FF28h DWORD (undoc) CR4
  228. FF2Ch DWORD unused
  229. FF30h 12 BYTEs (undoc) ES descriptor cache
  230. DWORD limit
  231. DWORD base address
  232. DWORD type
  233. FF3Ch 12 BYTEs (undoc) CS descriptor cache
  234. FF48h 12 BYTEs (undoc) SS descriptor cache
  235. FF54h 12 BYTEs (undoc) DS descriptor cache
  236. FF60h 12 BYTEs (undoc) FS descriptor cache
  237. FF6Ch 12 BYTEs (undoc) GS descriptor cache
  238. FF78h 12 BYTEs (undoc) LDT descriptor cache
  239. FF84h 12 BYTEs (undoc) GDT descriptor cache
  240. FF90h 12 BYTEs (undoc) IDT descriptor cache
  241. FF9Ch 12 BYTEs (undoc) TSS descriptor cache
  242. FFA8h WORD ES
  243. FFAAh WORD reserved
  244. FFACh WORD CS
  245. FFAEh WORD reserved
  246. FFB0h WORD SS
  247. FFB2h WORD reserved
  248. FFB4h WORD DS
  249. FFB6h WORD reserved
  250. FFB8h WORD FS
  251. FFBAh WORD reserved
  252. FFBCh WORD GS
  253. FFBEh WORD reserved
  254. FFC0h DWORD LDTR
  255. FFC4h DWORD TR
  256. FFC8h DWORD DR7
  257. FFCCh DWORD DR6
  258. FFD0h DWORD EAX
  259. FFD4h DWORD ECX
  260. FFD8h DWORD EDX
  261. FFDCh DWORD EBX
  262. FFE0h DWORD ESP
  263. FFE4h DWORD EBP
  264. FFE8h DWORD ESI
  265. FFECh DWORD EDI
  266. FFF0h DWORD EIP
  267. FFF4h DWORD EFLAGS
  268. FFF8h DWORD CR3
  269. FFFCh DWORD CR0
  270. SeeAlso: #S0003
  271. --------!---Admin----------------------------
  272. Highest Table Number = S0008
  273. --------!---FILELIST-------------------------
  274. Please redistribute all of the files comprising the interrupt list (listed at
  275. the beginning of the list and in INTERRUP.1ST) unmodified as a group, in a
  276. quartet of archives named INTER60A through INTER60D (preferably the original
  277. authenticated PKZIP archives), and the utility and hypertext conversion
  278. programs in three additional archives called INTER60E.ZIP to INTER60G.ZIP.
  279. Copyright (c) 1989,1990,1991,1992,1993,1994,1995,1996,1997,1998,1999 Ralf Brown
  280. --------!---CONTACT_INFO---------------------
  281. Internet: ralf@pobox.com (currently forwards to ralf@telerama.lm.com)
  282. FIDO: Ralf Brown 1:129/26.1