old/ASM/intlist/PORTS.LST

PORTS LIST			Release 60		Last change 03jan99
Copyright (c) 1989,1990,1991,1992,1993,1994,1995,1996,1997,1998,1999 Ralf Brown
[This file originally by Wim Osterholt <wim@djo.wtm.tudelft.nl>,
 though it has grown considerably since.]

		XT, AT and PS/2	 I/O port addresses

Do NOT consider this information to be complete and accurate.  If you want
to do hardware programming ALWAYS check the appropriate data sheets (but
even they are sometimes in error!).  Be aware that erroneous port programming
can put your data or even your hardware at risk.

There are a number of memory-mapped addresses in use for I/O; see MEMORY.LST
for details on memory-mapped I/O.

--------!---Note-----------------------------
Note: the port description format is:

PPPPw RW  description

where:	PPPP	is the four-digit hex port number or a plus sign and three hex
		digits to indicate an offset from a base port address
	w	is blank for byte-size port, 'w' for word, and 'd' for dword
	R	is dash (or blank) if not readable, 'r' if sometimes readable,
		'R' if "always" readable, '?' if readability unknown
	W	is dash (or blank) if not writable, 'w' if sometimes writable,
		'W' if "always" writable, 'C' if write-clear, and
		'?' if writability unknown
----------P0000001F--------------------------
PORT 0000-001F - DMA 1 - FIRST DIRECT MEMORY ACCESS CONTROLLER (8237)
SeeAlso: PORT 0080h-008Fh"DMA",PORT 00C0h-00DFh

0000  R-  DMA channel 0	current address		byte  0, then byte 1
0000  -W  DMA channel 0	base address		byte  0, then byte 1
0001  RW  DMA channel 0 word count		byte 0, then byte 1
0002  R-  DMA channel 1	current address		byte  0, then byte 1
0002  -W  DMA channel 1	base address		byte  0, then byte 1
0003  RW  DMA channel 1 word count		byte 0, then byte 1
0004  R-  DMA channel 2	current address		byte  0, then byte 1
0004  -W  DMA channel 2	base address		byte  0, then byte 1
0005  RW  DMA channel 2 word count		byte 0, then byte 1
0006  R-  DMA channel 3	current address		byte  0, then byte 1
0006  -W  DMA channel 3	base address		byte  0, then byte 1
0007  RW  DMA channel 3 word count		byte 0, then byte 1

0008  R-  DMA channel 0-3 status register (see #P0001)
0008  -W  DMA channel 0-3 command register (see #P0002)
0009  -W  DMA channel 0-3 write request register (see #P0003)
000A  RW  DMA channel 0-3 mask register (see #P0004)
000B  -W  DMA channel 0-3 mode register (see #P0005)

000C  -W  DMA channel 0-3 clear byte pointer flip-flop register
	  any write clears LSB/MSB flip-flop of address and counter registers
000D  R-  DMA channel 0-3 temporary register
000D  -W  DMA channel 0-3 master clear register
	  any write causes reset of 8237
000E  -W  DMA channel 0-3 clear mask register
	  any write clears masks for all channels
000F  rW  DMA channel 0-3 write mask register (see #P0006)
Notes:	the temporary register is used as holding register in memory-to-memory
	  DMA transfers; it holds the last transferred byte
	channel 2 is used by the floppy disk controller
	on the IBM PC/XT channel 0 was used for the memory refresh and
	  channel 3 was used by the hard disk controller
	on AT and later machines with two DMA controllers, channel 4 is used
	  as a cascade for channels 0-3
	command and request registers do not exist on a PS/2 DMA controller

Bitfields for DMA channel 0-3 status register:
Bit(s)	Description	(Table P0001)
 7	channel 3 request active
 6	channel 2 request active
 5	channel 1 request active
 4	channel 0 request active
 3	channel terminal count on channel 3
 2	channel terminal count on channel 2
 1	channel terminal count on channel 1
 0	channel terminal count on channel 0
SeeAlso: #P0002,#P0481

Bitfields for DMA channel 0-3 command register:
Bit(s)	Description	(Table P0002)
 7	DACK sense active high
 6	DREQ sense active high
 5	=1 extended write selection
	=0 late write selection
 4	rotating priority instead of fixed priority
 3	compressed timing (two clocks instead of four per transfer)
	=1 normal timing (default)
	=0 compressed timing
 2	=1 enable controller
	=0 enable memory-to-memory
 1-0	channel number
SeeAlso: #P0001,#P0004,#P0005,#P0482

Bitfields for DMA channel 0-3 request register:
Bit(s)	Description	(Table P0003)
 7-3	reserved (0)
 2	=0 clear request bit
	=1 set request bit
 1-0	channel number
	00 channel 0 select
	01 channel 1 select
	10 channel 2 select
	11 channel 3 select
SeeAlso: #P0004

Bitfields for DMA channel 0-3 mask register:
Bit(s)	Description	(Table P0004)
 7-3	reserved (0)
 2	=0 clear mask bit
	=1 set mask bit
 1-0	channel number
	00 channel 0 select
	01 channel 1 select
	10 channel 2 select
	11 channel 3 select
SeeAlso: #P0001,#P0002,#P0003,#P0484

Bitfields for DMA channel 0-3 mode register:
Bit(s)	Description	(Table P0005)
 7-6	transfer mode
	00 demand mode
	01 single mode
	10 block mode
	11 cascade mode
 5	direction
	=0 increment address after each transfer
	=1 decrement address
 3-2	operation
	00 verify operation
	01 write to memory
	10 read from memory
	11 reserved
 1-0	channel number
	00 channel 0 select
	01 channel 1 select
	10 channel 2 select
	11 channel 3 select
SeeAlso: #P0002,#P0485

Bitfields for DMA channel 0-3 write mask register:
Bit(s)	Description	(Table P0006)
 7-4	reserved
 3	channel 3 mask bit
 2	channel 2 mask bit
 1	channel 1 mask bit
 0	channel 0 mask bit
Note:	each mask bit is automatically set when the corresponding channel
	  reaches terminal count or an extenal EOP sigmal is received
SeeAlso: #P0004,#P0486
----------P0010001F--------------------------
PORT 0010-001F - DMA CONTROLLER (8237) ON PS/2 MODEL 60 & 80
SeeAlso: PORT 0000h-001Fh,PORT 0080h-008Fh"DMA",PORT 00C0h-00DFh

0018  -W  extended function register (see #P0007)
001A  -W  extended function execute register

Bitfields for DMA extended function register:
Bit(s)	Description	(Table P0007)
 7-4	function code (see #P0008)
 3	reserved (0)
 2-0	channel number
	000 channel 0 select
	001 channel 1 select
	010 channel 2 select
	011 channel 3 select
	100 channel 4 select
	101 channel 5 select
	110 channel 6 select
	111 channel 7 select

(Table P0008)
Values for DMA extended function codes (data go to/from PORT 001Ah):
Value	Description		  Parameters  Results
 00h	current address register      -	      CA0,CA1
 02h	write address		      -	      A0,A1,P
 03h	read  address		   A0,A1,P	 -
 04h	write word count register   C0,C1	 -
 05h	read  word count register     -	       C0,C1
 06h	read status register	      -		 S
 07h	mode register		      -		 M
 09h	mask channel		      -		 -
 0Ah	unmask channel		      -		 -
 0Dh	master clear		      -		 -
Note:	CA0/CA1	  LSB/MSB of the current address register
	A0/A1	  LSB/MSB of the base address register
	P	  DMA page address
	C0/C1	  LSB/MSB of the word count register
	S	  status register value (see #P0001, #P0481)
	M	  mode register value (see #P0005, #P0485)
	first, the extended function register is written, then the extended
	  function register execute register is read/written if the function
	  being executing requires

Bitfields for DMA extended mode register:
Bit(s)	Description	(Table P0009)
 7	reserved (0)
 6	=0 8-bit transfer
	=1 16-bit transfer
 5-4	reserved (0)
 3	transfer type
	=0 read from memory
	=1 write to memory
 2	=0 disable memory write
	=1 enable  memory write
 1	reserved (0)
 0	address select
	=0 use 0 as base address
	=1 use a value from base address register
Note:	the IBM PS/2 model 80 technical reference doesn't seem to mention this
	  register's address
----------P0020003F--------------------------
PORT 0020-003F - PIC 1 - PROGRAMMABLE INTERRUPT CONTROLLER (8259A)
SeeAlso: PORT 00A0h-00AFh"PIC 2",INT 08"IRQ0",INT 0F"IRQ7"

0020  -W  PIC initialization command word ICW1 (see #P0010)
0020  -W  PIC output control word OCW2 (see #P0015)
0020  -W  PIC output control word OCW3 (see #P0016)
0020  R-  PIC  interrupt request/in-service registers after OCW3
		request register:
		 bit 7-0 = 0  no active request for the corresponding int. line
			 = 1  active request for corresponding interrupt line
		in-service register:
		 bit 7-0 = 0  corresponding line not currently being serviced
			 = 1  corresponding int. line currently being serviced

0021  -W  PIC ICW2,ICW3,ICW4 immed after ICW1 to 0020 (see #P0011,#P0012,#P0013)
0021  RW  PIC master interrupt mask register OCW1 (see #P0014)

Bitfields for PIC initialization command word ICW1:
Bit(s)	Description	(Table P0010)
 7-5	0 (only used in 8080/8085 mode)
 4	ICW1 is being issued
 3	(LTIM)
	=0  edge triggered mode
	=1  level triggered mode
 2	interrupt vector size
	=0 successive interrupt vectors use 8 bytes (8080/8085)
	=1 successive interrupt vectors use 4 bytes (80x86)
 1	(SNGL)
	=0  cascade mode
	=1  single mode, no ICW3 needed
 0	ICW4 needed
SeeAlso: #P0011,#P0012,#P0013

Bitfields for PIC initialization command word ICW2:
Bit(s)	Description	(Table P0011)
 7-3	address lines A0-A3 of base vector address for PIC
 2-0	reserved
SeeAlso: #P0010,#P0012,#P0013

Bitfields for PIC initialization command word ICW3:
Bit(s)	Description	(Table P0012)
 7-0	=0 slave controller not attached to corresponding interrupt pin
	=1 slave controller attached to corresponding interrupt pin
SeeAlso: #P0010,#P0011,#P0013

Bitfields for PIC initialization command word ICW4:
Bit(s)	Description	(Table P0013)
 7-5	reserved (0)
 4	running in special fully-nested mode
 3-2	mode
	0x nonbuffered mode
	10 buffered mode/slave
	11 buffered mode/master
 1	Auto EOI
 0	=0  8085 mode
	=1  8086/8088 mode
SeeAlso: #P0010,#P0011,#P0012

Bitfields for PIC output control word OCW1:
Bit(s)	Description	(Table P0014)
 7	disable IRQ7 (parallel printer interrupt)
 6	disable IRQ6 (diskette interrupt)
 5	disable IRQ5 (fixed disk interrupt)
 4	disable IRQ4 (serial port 1 interrupt)
 3	disable IRQ3 (serial port 2 interrupt)
 2	disable IRQ2 (video interrupt)
 1	disable IRQ1 (keyboard, mouse, RTC interrupt)
 0	disable IRQ0 (timer interrupt)
SeeAlso: #P0015,#P0016,#P0418

Bitfields for PIC output control word OCW2:
Bit(s)	Description	(Table P0015)
 7-5	operation
	000 rotate in auto EOI mode (clear)
	001 (WORD_A) nonspecific EOI
	010 (WORD_H) no operation
	011 (WORD_B) specific EOI
	100 (WORD_F) rotate in auto EOI mode (set)
	101 (WORD_C) rotate on nonspecific EOI command
	110 (WORD_E) set priority command
	111 (WORD_D) rotate on specific EOI command
 4-3	reserved (00 - signals OCW2)
 2-0	interrupt request to which the command applies
	(only used by WORD_B, WORD_D, and WORD_E)
SeeAlso: #P0014,#P0016

Bitfields for PIC output control word OCW3:
Bit(s)	Description	(Table P0016)
 7	reserved (0)
 6-5	special mask
	0x  no operation
	10  reset special mask
	11  set special mask mode
 4-3	reserved (01 - signals OCW3)
 2	poll command
 1-0	function
	0x  no operation
	10  read interrupt request register on next read from PORT 0020h
	11  read interrupt in-service register on next read from PORT 0020h
Note:	the special mask mode permits all other interrupts (even those with
	  lower priority) to be processed while an interrupt is already in
	  service, but will not re-issue an interrupt for a particular IRQ
	  while it remains in service
SeeAlso: #P0014,#P0015
----------P0022------------------------------
PORT 0022 - Intel 82439TX Chipset - Power Control register
SeeAlso: PORT 0022h"82443BX"

0022  RW  PM2 Register Block
	bits 7-1: reserved
	bit 0:	Arbiter Disable
--------p-P0022------------------------------
PORT 0022 - Intel 82443BX - "PM2_CTL" ACPI Power Control 2 Register
SeeAlso: PORT 0022h"82439TX",#01142 at INT 1A/AX=B10Ah/SF=8086h

0022  RW  ACPI Power Control Register 2
	bits 7-1: reserved
	bit 0:	disable primary PCI and AGP arbiter requests
----------P00220023--------------------------
PORT 0022-0023 - CHIP SET DATA
Note:	These two ports are used by numerous chipsets.	Various chipsets are
	  detailed below.

0022  -W  index for accesses to data port
0023  RW  chip set data
----------P00220023--------------------------
PORT 0022-0023 - Cyrix Cx486SLC/DLC PROCESSOR - CACHE CONFIGURATION REGISTERS
SeeAlso: PORT 0022h"5x86",PORT 0022h"6x86"

0022  -W  index for accesses to next port (see #P0017)
0023  RW  cache configuration register array (indexed by PORT 0022h)
	Note:	the index must be written to PORT 0022h before every access
		  to PORT 0023h; out-of-sequence accesses or index values
		  not supported by the processor generate external I/O cycles

(Table P0017)
Values for Cyrix Cx486SLC/DLC Cache Configuration register number:
 C0h	CR0 (see #P0019)
 C1h	CR1 (see #P0020)
 C4h	non-cacheable region 1, start address bits 31-24
 C5h	non-cacheable region 1, start address bits 23-16
 C6h	non-cacheable region 1, start addr 15-12, size (low nibble) (see #P0018)
 C7h	non-cacheable region 2, start address bits 31-24
 C8h	non-cacheable region 2, start address bits 23-16
 C9h	non-cacheable region 2, start addr 15-12, size (low nibble) (see #P0018)
 CAh	non-cacheable region 3, start address bits 31-24
 CBh	non-cacheable region 3, start address bits 23-16
 CCh	non-cacheable region 3, start addr 15-12, size (low nibble) (see #P0018)
 CDh	non-cacheable region 4, start address bits 31-24
 CEh	non-cacheable region 4, start address bits 23-16
 CFh	non-cacheable region 4, start addr 15-12, size (low nibble) (see #P0018)
SeeAlso: #P0023,#P0021

(Table P0018)
Values for Cyrix Cx486SLC/DLC non-cacheable region sizes:
 00h	disabled
 01h	4K
 02h	8K
 03h	16K
 04h	32K
 05h	64K
 06h	128K
 07h	256K
 08h	512K
 09h	1M
 0Ah	2M
 0Bh	4M
 0Ch	8M
 0Dh	16M
 0Eh	32M
 0Fh	4G
SeeAlso: #P0017

Bitfields for Cyrix Cx486SLC/DLC Configuration Register 0:
Bit(s)	Description	(Table P0019)
 0	"NC0" first 64K of each 1M noncacheable in real/V86
 1	"NC1" 640K-1M noncacheable
 2	"A20M" enables A20M# input pin
 3	"KEN"  enables KEN# input pin
 4	"FLUSH" enables FLUSH input pin
 5	"BARB" enables internal cache flushing on bus holds
 6	"C0" cache direct-mapped instead of 2-way associative
 7	"SUSPEND" enables SUSP# input and SUSPA# output pins
SeeAlso: #P0017,#P0020,#P0032

Bitfields for Cyrix Cx486SLC/DLC Configuration Register 1:
Bit(s)	Description	(Table P0020)
 0	"RPL" enables output pins RPLSET and RPLVAL#
SeeAlso: #P0017,#P0019,#P0024
----------P00220023--------------------------
PORT 0022-0023 - Cyrix 486S2/D2/DX/DX2/DX4 PROCESSOR - CONFIGURATION REGISTERS
SeeAlso: PORT 0022h"Cx486SLC",PORT 0022h"5x86",PORT 0022h"6x86"

0022  -W  index for accesses to next port (see #P0021)
0023  RW  cache configuration register array (indexed by PORT 0022h)
	Note:	the index must be written to PORT 0022h before every access
		  to PORT 0023h; out-of-sequence accesses or index values
		  not supported by the processor generate external I/O cycles

(Table P0021)
Values for Cyrix 486S2/D2/DX/DX2/DX4 configuration register number:
 C2h	CR2 (see #P0025)
 C3h	CR3 (see #P0026)
 CDh	SMM region, start address bits 31-24
 CEh	SMM region, start address bits 23-16
 CFh	SMM region, start addr 15-12, size (low nibble) (see #P0018)
 FEh R	Device Identification #0 (see #P0022)
	CPU device ID
 FFh R	Device Identification #1
	bits 3-0: revision
	bits 7-4: stepping
SeeAlso: #P0017,#P0023,#P0031

(Table P0022)
Values for Cyrix device identification:
(#0 /#1)
 00h	Cx486SLC
 01h	Cx486DlC
 02h	Cx486SLC2
 03h	Cx486DLC2
 04h	Cx486SRx
 05h	Cx486DRx
 06h	Cx486SRx2
 07h	Cx486DRx2
 10h	Cx486S (B-step)
 11h	Cx486S2 (B-step)
 12h	Cx486Se (B-step)
 13h	Cx486S2e (B-step)
1Ah/05h	Cx486DX-40
1Bh/08h	Cx486DX2-50
1Bh/0Bh	Cx486DX2-66
1Bh/31h	Cx486DX2-v80
1Fh/36h	Cx486DX4-v100
 28h	5x86 1xs
 29h	5x86 2xs
 2Ah	5x86 1xp
 2Bh	5x86 2xp
 2Ch	5x86 4xs
 2Dh	5x86 3xs
 2Eh	5x86 4xp
 2Fh	5x86 3xp
 30h	6x86 1xs
 31h	6x86 2xs
 32h	6x86 1xp
 33h	6x86 2xp
 34h	6x86 4xs
 35h	6x86 3xs
 36h	6x86 4xp
 37h	6x86 3xp
Note:	#0 is the value in configuration register FEh, while #1 is the value
	  in configuration register FFh
SeeAlso: #P0021
----------P00220023--------------------------
PORT 0022-0023 - Cyrix 5x86 PROCESSOR - CONFIGURATION CONTROL REGISTERS
SeeAlso: PORT 0022h"Cx486SLC",PORT 0022h"486S2",PORT 0022h"6x86"

0022  -W  index for accesses to next port (see #P0023)
0023  RW  configuration control register array (indexed by PORT 0022h)
	Note:	the index must be written to PORT 0022h before every access
		  to PORT 0023h; out-of-sequence accesses or index values
		  not supported by the processor generate external I/O cycles

(Table P0023)
Values for Cyrix 5x86 configuration registers:
 20h	Performance Control (see #P0028)
 C1h	Configuration Control #1 (CCR1) (see #P0024)
 C2h	Configuration Control #2 (CCR2) (see #P0025)
 C3h	Configuration Control #3 (CCR3) (see #P0026)
 CDh	System Memory Management address region #0 (smar0) (see #P0029)
 CEh	System Memory Management address region #1 (smar1)
 CFh	System Memory Management address region #2 (smar2)
 E8h	Configuration Control Register 4
 F0h	Power Management (see #P0030)
 FEh R	Device Identification #0 (see #P0022)
	CPU device ID
 FFh R	Device Identification #1
	bits 3-0: revision
	bits 7-4: stepping
SeeAlso: #P0017,#P0021,#P0031

Bitfields for Cyrix 5x86,6x86 Configuration Control Register 1 (CCR1):
Bit(s)	Description	(Table P0024)
 0	reserved
 1	enable SMM pins
 2	system management memory access
 3	main memory access
 4	(6x86) no LOCK during bus cycles
 6-5	reserved
 7	(6x86) use address region 3 as SMM space
Note:	bits 1,2,7 may only be written when CCR3 bit 0 is enabled
SeeAlso: #P0020,#P0025,#P0026,#P0027

Bitfields for Cyrix 5x86,6x86 Configuration Control Register 2 (CCR2):
Bit(s)	Description	(Table P0025)
 0	reserved
 1	enable write-back cache interface pins
 2	lock NW bit
 3	suspend on HLT instruction
 4	write-through region 1
 5	reserved
 6	enable burst write cycles
 7	enable suspend pins
SeeAlso: #P0024,#P0026,#P0027

Bitfields for Cyrix 5x86,6x86 Configuration Control Register 3 (CCR3):
Bit(s)	Description	(Table P0026)
 0	SMM register lock (can only be cleared in SMM mode or by CPU reset)
 1	NMI enable
 2	linear address burst cycles (5x86,6x86 only)
	=0 Pentium-compatible
	=1 linear sequencing
 3	SMM mode (5x86 only)
	=0 486SL
	=1 Cyrix
 7-4	map enable (5x86,6x86 only)
	0000 only allow access to configuration registers C0h-CFh,FEh,FFh
	0001 enable access to all configuration registers
SeeAlso: #P0024,#P0025,#P0027,#P0028,#P0030

Bitfields for Cyrix 5x86,6x86 Configuration Control Register 4 (CCR4):
Bit(s)	Description	(Table P0027)
 2-0	I/O recovery time (000 = none, else 2^N clocks)
 3	enable memory-read bypassing (5x86 only)
 4	enable directory table entry cache
 6-5	reserved
 7	enable CPUID instruction (stepping 1+ and Cx6x86)
Note:	this register is only accessible when bits 7-4 of CCR3 are 0001
SeeAlso: #P0024,#P0025,#P0026

Bitfields for Cyrix 5x86 Performance Control register:
Bit(s)	Description	(Table P0028)
 0	return stack enabled (speculatively execute code after current CALL)
 1	branch-target buffer enabled
 2	loop enable
 6-3	reserved (0)
 7	load-store serialization enabled
	(memory reads and writes may be reorganized into optimum order)
Note:	this register is only accessible when bits 7-4 of CCR3 are 0001
SeeAlso: #P0030,#P0024

Bitfields for Cyrix 5x86 SMM Address Region register:
Bit(s)	Description	(Table P0029)
 3-0	block size
 23-4	starting address

Bitfields for Cyrix 5x86 Power Management register:
Bit(s)	Description	(Table P0030)
 1-0	core clock to bus clock ratio
	00 1:1
	01 2:1
	10 reserved
	11 3:1
 2	CPU running at half bus speed, ignore bits 1-0
Note:	this register is only accessible when bits 7-4 of CCR3 are 0001
----------P00220023--------------------------
PORT 0022-0023 - Cyrix 6x86 PROCESSOR - CONFIGURATION CONTROL REGISTERS
SeeAlso: PORT 0022h"Cx486",PORT 0022h"5x86"

0022  -W  index for accesses to next port (see #P0023)
0023  RW  configuration control register array (indexed by PORT 0022h)
	Note:	the index must be written to PORT 0022h before every access
		  to PORT 0023h; out-of-sequence accesses or index values
		  not supported by the processor generate external I/O cycles

(Table P0031)
Values for Cyrix 6x86 configuration registers:
 C0h	Configuration Control Register 0 (CCR0) (see #P0032)
 C1h	Configuration Control #1 (CCR1) (see #P0024)
 C2h	Configuration Control #2 (CCR2) (see #P0025)
 C3h	Configuration Control #3 (CCR3) (see #P0026)
 C4h	Address region 0 (bits 31-24)
 C5h	Address region 0 (bits 23-16)
 C6h	Address region 0 (bits 15-12 and size)
 C7h	Address region 1 (bits 31-24)
 C8h	Address region 1 (bits 23-16)
 C9h	Address region 1 (bits 15-12 and size)
 CAh	Address region 2 (bits 31-24)
 CBh	Address region 2 (bits 23-16)
 CCh	Address region 2 (bits 15-12 and size)
 CDh	Address region 3 (bits 31-24)
 CEh	Address region 3 (bits 23-16)
 CFh	Address region 3 (bits 15-12 and size)
 D0h	Address region 4 (bits 31-24)
 D1h	Address region 4 (bits 23-16)
 D2h	Address region 4 (bits 15-12 and size)
 D3h	Address region 5 (bits 31-24)
 D4h	Address region 5 (bits 23-16)
 D5h	Address region 5 (bits 15-12 and size)
 D6h	Address region 6 (bits 31-24)
 D7h	Address region 6 (bits 23-16)
 D8h	Address region 6 (bits 15-12 and size)
 D9h	Address region 7 (bits 31-24)
 DAh	Address region 7 (bits 23-16)
 DBh	Address region 7 (bits 15-12 and size)
 DCh	Region Control 0
 DDh	Region Control 1
 DEh	Region Control 2
 DFh	Region Control 3
 E0h	Region Control 4
 E1h	Region Control 5
 E2h	Region Control 6
 E3h	Region Control 7
 E8h	Configuration Control Register 4 (see #P0027)
 E9h	Configuration Control Register 5 (see #P0033)
 FEh R	Device Identification #0 (see #P0022)
	CPU device ID
 FFh R	Device Identification #1
	bits 3-0: revision
	bits 7-4: stepping
SeeAlso: #P0017,#P0023

Bitfields for Cyrix 6x86 Configuration Control Register 0:
Bit(s)	Description	(Table P0032)
 7-2	???
 1	address region 640K-1M is noncacheable
 0	???
SeeAlso: #P0019

Bitfields for Cyrix 6x86 Configuration Control Register 5:
Bit(s)	Description	(Table P0033)
 7-6	reserved
 5	enable all address-region registers (control registers C4h-DBh)
 4	assert LBA# pin on all accesses to 640K-1M
 3-1	reserved
 0	allocate new cache lines only on read misses
SeeAlso: #P0032,#P0027,#P0031
----------P00220023--------------------------
PORT 0022-0023 - GoldStar 286 - CHIP SET CONFIGURATION REGISTERS
SeeAlso: PORT 0022h"Cx486SLC",PORT 0022h"486S2",PORT 0022h"6x86"

0022  -W  index for accesses to next port (see #P0034)
0023  RW  configuration control register array (indexed by PORT 0022h)

(Table P0034)
Values for GoldStar 286 chipset configuration register index:
 60h	turbo control
	write 00h to PORT 0023h to turn on turbo, 10h to turn it off
--------X-P00220023--------------------------
PORT 0022-0023 - Intel 82358DT 'Mongoose' EISA CHIPSET - 82359 DRAM CONTROLLER
Notes:	this chip uses a chip ID of 01
	the LIM register herein use a chip ID of 1A
Index: Intel 82351

0022  -W  index for accesses to data port (see #P0036,#P0037,#P0038)
0023  RW  chip set data

(Table P0035)
Values for Intel 82351/82359 chip ID:
 01h	82359 DRAM controller, general registers
 02h	82351 EISA local I/O support
 A1h	82359 DRAM controller, EMS registers
 FFh	no chip accessible (default)
SeeAlso: #P0036,#P0037,#P0038

(Table P0036)
Values for 82359 DRAM controller general register index:
 00h	DRAM bank 0 type
	bit 7	unknown
	bit 6-4	000 DRAM in bank 0 (standard)
		001 bank 1
		010 bank 2
		011 bank 3
		100 banks 0,1
		101 banks 2,3
		110 banks 0,1,2,3
		111 empty (standard for 1,2,3)
	bit 3-2	unknown
	bit 1-0	00 64K chips used
		01 256K
		10 1M
		11 4M
 01h	DRAM bank 1 type
 02h	DRAM bank 2 type
 03h	DRAM bank 3 type
 04h	DRAM speed detection/selection
 05h	DRAM interleave control
 06h	RAS line mode
 07h	cache-enable selection
 08h	mode register A (DRAM, cache)
 09h	mode register B (cache, burst modes, BIOS size)
 0Ah	mode register C (concurrency control, burst/cycle speed)
 10h	host timing
 11h	host-system delay timing
 12h	system timing
 13h	DRAM row precharge time
 14h	DRAM row timing
 15h	DRAM column timing
 16h	CAS pulse width
 17h	CAS-to-MDS delay
 21h	chip ID register -- selects which chip responds on these ports
	(see #P0035)
 28h-2Ch	parity-error trap address
 30h	page hit cycle length (read)
 31h	page miss cycle length (read)
 32h	row miss cycle length (read)
 33h	page hit cycle length (write)
 34h	page miss cycle length (write)
 35h	row miss cycle length (write)
 40h	memory enable 00000h-7FFFFh
 41h	memory enable 80000h-9FFFFh
 42h	memory enable A0000h-AFFFFh
 43h	memory enable B0000h-BFFFFh
 44h	memory enable C0000h-CFFFFh
 45h	memory enable D0000h-DFFFFh
 46h	memory enable E0000h-EFFFFh
 47h	memory enable F0000h-FFFFFh
 4Eh	remap 80000h-FFFFFh to extended memory
 50h-53h	programmable attribute map 1
 54h-57h	programmable attribute map 2
 58h-5Bh	programmable attribute map 3
 5Ch-5Fh	programmable attribute map 4
 83h-84h	split address register (address bits A31-A20)
 85h	cache control
 8Bh	system throttle
 8Ch	host throttle
 8Dh	host memory throttle watchdog
 8Eh	host system throttle
 8Fh	host system throttle watchdog
 90h	RAM enable
 91h	RAM disable
 92h-93h	elapsed-time registers
 94h-95h	host memory ownership request
 96h-97h	system memory ownership request
 98h-99h	host memory ownership
 9Ah-9Bh	system bus ownership
 9Ch-9Dh	host system bus request
 9Eh-9Fh	memory ownership transfer
SeeAlso: #P0037,#P0038

(Table P0037)
Values for Intel 82359 DRAM controller EMS register index:
 00h	EMS cotnrol
 21h	chip ID register -- selects which chip responds on these ports
	(see #P0035)
 80h-8Fh	EMS page registers, pages 0-7
SeeAlso: #P0036,#P0038

(Table P0038)
Values for Intel 82351 EISA Local I/O register index:
 21h	chip ID register -- selects which chip responds on these ports
	(see #P0035)
 C0h	peripheral enable register A
 C1h	peripheral enable register B
 C2h	parallel configuration register
 C3h	serial configuration register A
 C4h	floppy disk controller configuration register
 C5h	serial configuration register B
 C6h	COM3 port address (low)
 C7h	COM3 port address (high)
 C8h	COM4 port address (low)
 C9h	COM4 port address (high)
 D0h-D3h	general chip select lines 0-3 (mask registers)
 D4h-D7h	general chip select line addresses 0-3 (low bytes)
 D8h-DBh	general chip select line addresses 0-3 (high bytes)
 DCh	extended CMOS RAM page port address (low)
 DDh	extended CMOS RAM page port address (high)
 DFh	extended CMOS RAM access select address (high byte)
 E8h-EBh	EISA ID configuration registers (reflect at PORT 0C80h)
SeeAlso: #P0036,#P0037
--------X-P00220023--------------------------
PORT 0022-0023 - Intel 82374EB/SB EISA CHIPSET
Index: Intel 82374EB;Intel 82374SB

0022  -W  index for accesses to data port (see #P0039)
0023  RW  chip set data

!!!29047604.pdf pg. 36
(Table P0039)
Values for Intel 82374 register index:
 02h	ESC identification register
	(82374 will only respond to ports 0022h and 0023h after an 0Fh
	 is written to this register)
 08h	revision ID register
 40h	mode select (see #P0040)
 42h	BIOS Chip Select A (see #P0041)
 43h	BIOS Chip Select B (see #P0042)
 4Dh	EISA clock divisor (see #P0043)
 4Eh	peripheral Chip Select A (see #P0044)
 4Fh	peripheral Chip Select B (see #P0045)
 50h-53h EISA ID registers
 57h	scatter/gather relocate base address (see also #01075)
	(specifies bits 15-0 if S/G port addresses [low byte always 10h-3Fh])
 59h	APIC base address relocation
 60h-63h PCI IRQn# route control (see also #01076)
 64h	general-purpose chip select low address 0
 65h	general-purpose chip select high address 0
 66h	general-purpose chip select mask register 0
 68h	general-purpose chip select low address 1
 69h	general-purpose chip select high address 1
 6Ah	general-purpose chip select mask register 1
 6Ch	general-purpose chip select low address 2
 6Dh	general-purpose chip select high address 2
 6Eh	general-purpose chip select mask register 2
 6Fh	general-purpose peripheral X-Bus control
---SB only---
 70h	PCI/APIC control (see #P0046)
 88h	test control
 A0h	SMI control (see #P0047)
 A2h-A3h  SMI enable (see #P0048)
 A4h-A7h  System Event Enable (see #P0049)
 A8h	Fast-Off timer
 AAh-ABh SMI Request (see #P0050)
 ACh	Clock Scale STPCLK# low timer
 AEh	Clock Scale STPCLK# high timer

Bitfields for 82374EB mode select (register 40h):
Bit(s)	Description	(Table P0040)
  7	reserved
  6	enable the selected (MREQ[7:4]#/PIRQ[3:0]# functionality
  5	enable/disable configuration RAM Page Address (CPG[4:0]) generation
	=1 accesses to the configuration RAM space will generate the RAM page
	  address on the LA[31:27]# pins (default)
	=0 the CPG[4:0] signals will not be activated
  4	General Purpose Chip Selects: select GPCS[2:0]#/ECS[2:0] pins' function
	=0 GPCS[2:0]# functionality is selected
	=1 ESC[2:0] functionality is selected
  3	System Error: enable generation of NMI based on SERR# signal pulsing
	=0 NMI is negated and SERR# is disabled from generating an NMI
	=1 NMI signal is asserted when NMIs are enabled via the NMIERTC
	  Register and SERR# is asserted
	Note: other NMI sources are enabled/disabled via the NMISC register
  2-0	PIRQx Mux/Mapping Control: select muxing/mapping of PIRQ[3:0]# with
	  MREQ[7:4] and group of X-Bus signals (DLIGHT#, RTCWR#, RTCRD#).
	Different bit combinations select the number of EISA slots or group of
	  X-Bus signals which can be supported with the certain number of
	  PIRQx# signals by determining the functionality of pins
	  AEN[4:1]/EAEN[4:1], MACK[3:0]#/EMACK[3:0]#, MREQ[7:4]/PIRQ[3:0]#,
	  DLIGHT#/PIRQ0#, FDCCS#/PIRQ1#, RTCWR#/PIRQ2#, and RTCRD#/PIRQ3#.
SeeAlso: #P0039

Bitfields for 82374EB BIOS Chip Select A "BIOSCSA" (register 42h):
Bit(s)	Description	(Table P0041)
  7-6	reserved
  5	Enlarged BIOS: assert LBIOSCS# for memory read cycles to locations
	  FFF80000h-FFFDFFFFh
  4	High BIOS: assert LBIOSCS# for memory read cycles to locations
	  0F0000h-0FFFFFh, FF0000h-FFFFFFh, and FFFF0000h-FFFFFFFFh
  3	Low BIOS 4: assert LBIOSCS# for memory read cycles to locations
	  0EC000h-0EFFFFh, FFEEC000h-FFEEFFFFh, and FFFEC000h-FFFEFFFFh
  2	Low BIOS 3: assert LBIOSCS# for memory read cycles to locations
	  0E8000h-0EBFFFh, FFEE8000h-FFEEBFFFh, and FFFE8000h-FFFEBFFFh
  1	Low BIOS 2: assert LBIOSCS# for memory read cycles to locations
	  0E4000h-0E7FFFh, FFEE4000h-FFEE7FFFh, and FFFE4000h-FFFE7FFFh
  0	Low BIOS 1: assert LBIOSCS# for memory read cycles to locations
	  0E0000h-0E3FFFh, FFEE0000h-FFEE3FFFh, and FFFE0000h-FFFE3FFFh
Note:	if bit 3 of register 43h (BIOSCSB) is set, then LBIOSCS# will be
	  asserted for write cycles as well as read cycles on any enabled range
SeeAlso: #P0039,#P0042

Bitfields for 82374EB BIOS Chip Select B (register 43h):
Bit(s)	Description	(Table P0042)
  7-4	Reserved
  3	BIOS Write Enable: assert LBIOSCS# for both memory read AND write
	  cycles for addresses in the decoded and enabled BIOS range
	  (see #P0041)
  2	16 Meg BIOS: assert LBIOSCS# for memory read cycles to locations
	  FF0000h-FFFFFFh
  1	High VGA BIOS: assert LBIOSCS# for memory read cycles to locations
	  0C4000h-0C7FFFh
  0	Low VGA BIOS: assert LBIOSCS# for memory read cycles to locations
	  0C0000h-0C3FFFh
Note:	if bit 3 of register 43h (BIOSCSB) is set, then LBIOSCS# will be
	  asserted for write cycles as well as read cycles on any enabled range
	  above
SeeAlso: #P0039,#P0041

Bitfields for 82374EB EISA clock divisor (register 4Dh):
Bit(s)	Description	(Table P0043)
  7-6	Reserved
  5	Co-processor Error: specify if the FERR# signal is connected to the
	  ESC internal IRQ13 interrupt signal.
	=0 FERR# signal is ignored by the ESC (i.e. this signal is not
	  connected to any logic in the ESC).
	=1 assert IRQ13 to the interrupt controller if FERR# signal is asserted
  4	82374EB: Reserved
	82374SB: ABFULL (with IRQ12):
	=0 internal IRQ12 is directed to the interrupt controller and 
	  transitions on ABFULL have no effect on this interrupt signal
	=1 the assertion of ABFULL is latched and directed to the internal
	  IRQ12 signal in the following manner:
	    If the interrupt controller is programmed for edge detect mode on
	      IRQ12, a low-to-high transition is generated on the internal
	      IRQ12 signal. Transitions on the IRQ12 input pin are not
	      reflected on the internal IRQ12 signal.
	    If the interrupt controller is programmed for level-sensitive mode,
	      a high-to-low transition is generated on the internal IRQ12
	      signal.  Transitions on the IRQ12 input pin are also reflected
	      on the internal IRQ12 signal.
	The latching of the ABFULL signal is cleared by an I/O read of
	  address 60h (no aliasing) or by a hard reset.
  3	82374EB: Reserved
	82374SB: Keyboard Full (KBFULL): select edge-detect KBFULL function on
	  the IRQ1 input signal
	=0 IRQ1 is directed to the interrupt controller
	=1 (default) IRQ1 is latched and directed to the interrupt controller.
	  The latched IRQ1 is cleared by an I/O read of address 60h (no
	  aliasing) or by a hard reset.
  2-0	Clock Divisor: select the integer used to divide the PCICLK down to
	  generate the BCLK.
	000 4 (33.33 MHz) 8.33 MHz (default after reset)
	001 3 (25 MHz) 8.33 MHz
	01x reserved
	1xx reserved
SeeAlso: #P0039

Bitfields for 82374EB peripheral Chip Select A (register 4Eh):
Bit(s)	Description	(Table P0044)
  7	Reserved
  6	Keyboard Controller Mapping
	=0 the keyboard controller encoded chip select signal and the X-Bus
	  transceiver enable (XBUSOE#) are generated for accesses to address
	  locations 60h (82374EB/SB), 62h (82374EB only), 64h (82374EB/SB) and
	  66h (82374EB only).
	=1 the keyboard controller chip select signals are generated for
	  accesses to the above address locations. However XBUSOE# is disabled.
	Note:	bit 1 must be 1 for either value of this configuration bit to
		  decode an access to locations 60h, 62h, 64h, or 66h.
  5	Floppy Disk/IDE Controller Address range
	=0 primary (1Fxh and 3Fxh)
	=1 secondary (17xh and 37xh)
  4	IDE DECODE: enable or disable IDE locations 1F0h-1F7h (primary) or
	  170h-177h (secondary) and 3F6h,3F7h (primary) or 376h,377h (sec).
	82374EB: When this bit is set to 0, the IDE encoded chip select signals
	  and the X-Bus transceiver signal (XBUSOE#) are not generated for
	  these addresses.
	82374SB: When this bit is set to 0, the IDE encoded chip select signals
	  and the X-Bus transceiver signal (XBUSOE#) are not generated for
	  addresses 1F0h-1F7h (primary) or 170h-177h (secondary) and 3F6h or
	  376h.	 Read/write accesses to addresses 377h and 3F7h are not
	  disabled and still generate XBUSOE#.
  3-2	Floppy Disk and IDE/Floppy Disk Decodes: Bits 2 and 3 are used to
	  enable or disable the floppy locations as indicated. Bit 2 defaults
	  to enabled (1) and bit 3 defaults to disabled (0) when a reset occurs
  1	Keyboard Controller Decode: enable the keyboard controller address
	  locations 60h (82374EB/SB), 62h (82374EB only), 64h (82374EB/SB), and
	  66h (82374EB only).
	=0 the keyboard controller encoded chip select signals and the X-Bus
	  transceiver signal (XBUSOE#) are not generated for these locations
	Note:	the value of this bit affects control function (keyboard
		  controlling mapping) provided by bit 6 of this register.
  0	Real Time Clock Decode: enable the RTC address locations 70h-77h.
	=0 the RTC encoded chip	select signals RTCALE, RTCRD, RTCWR#, and
	  XBUSOE# signals are not generated for these addresses.
SeeAlso: #P0039,#P0045

Bitfields for 82374EB peripheral Chip Select B (register 4Fh):
Bit(s)	Description	(Table P0045)
  7	CRAM Decode: enable I/O write accesses to location 0C00h and I/O
	  read/write accesses to locations 0800h-08FFh. The configuration RAM
	  read and write (CRAMRD#, CRAMWR#) strobes are valid for accesses to
	  0800h-08FFh.
  6	Port 92 Decode: enable access to Port 92 (default at PCIRST is enabled)
  5-4	select which Parallel Port address range (LPT1, 2, or 3) is decoded.
	00 LPT1 (3BCh-3BFh)
	01 LPT2 (378h-37Fh)
	10 LPT3 (278h-27Fh)
	11 disabled
  3-2	Serial Port B Address Decode: If either COM1 or COM2 address ranges
	  are selected, these bits default to disabled upon PCIRST.
	00 3F8h-3FFh (COM1)
	01 2F8h-2FFh (COM2)
	10 Reserved
	11 Port B disabled
  1-0	Serial Port A Address Decode: If either COM1 or COM2 address ranges are
	  selected, these bits default to disabled upon PCIRST.
	00 3F8h-3FFh (COM1)
	01 2F8h-2FFh (COM2)
	10 Reserved
	11 Port A disabled
SeeAlso: #P0039,#P0044

Bitfields for 82374SB PCI/APIC control (register 70h):
Bit(s)	Description	(Table P0046)
  7-2	Reserved
  1	SMI Routing Control (SMIRC)
	=1 SMI is routed via the APIC
	=0 SMI is routed via the SMI# signal
	Note:	when SMRCe1, INTR can not be routed through the APIC, since it
		  is sharing the APIC interrupt input with SMI#.
  0	INTR Routing Control (INTRC): When APIC is enabled (in mixed or pure
	  APIC mode), this bit allows the ESC's external INTR signal to be
	  masked (forces INTR to the inactive state but does not tri-states
	  the signal). Thus, the CPU's INTR pin can be used (by providing a
	  simple -gate) for the APIC Local Interrupt (LINTRx). However, INTR
	  must not be masked via this bit when APIC is disabled and INTR is
	  the only mechanism to signal the 8259 recognized interrupts to the
	  CPU.
	=1 INTR is disabled (APIC must be enabled)
	=0 INTR is enabled
SeeAlso: #P0039

Bitfields for 82374SB SMI control (register A0h):
Bit(s)	Description	(Table P0047)
  7	reserved (0)
  6-4	reserved
  3	Fast Off Timer Freeze (CTMRFRZ): disable the Fast Off Timer
	Disabling the timer prevents time-outs from occurring while executing
	  SMM code.
  2	STPCLK# Scaling Enable (CSTPCLKSC)
	=0 (default) scaling control of the STPCLK# signal is disabled.
	=1, the STPCLK# signal scaling control is enabled. When enabled (and
	  bit 1=1, enabling the STPCLK# signal), the high and low times for the
	  STPCLK# signal are controlled by the Clock Scaling STPCLK# High Timer
	  and Clock Scaling STPCLK# Low Timer Registers, respectively.
  1	STPCLK# Signal Enable (CSTPCLKE): permits software to place the CPU
	  into a low power state.
	=0 (default) STPCLK# signal is disabled and is negated (high)
	=1 the STPCLK# signal is enabled and a read from the APMC Register
	  causes STPCLK# to be asserted
	Software can set this bit to 0 by writing a 0 to it or by any write to
	  the APMC Register.
  0	SMI# Gate (CSMIGATE)
	=0 (default) the SMI# signal is masked and negated
	=1 SMI# signal is enabled and a system management interrupt condition
	  causes the SMI# signal to be asserted
Note:	bit 0 only affects the SMI# signal and does not affect the
	  detection/recording of SMI events (i.e., it does not affect the SMI
	  status bits in the SMIREQ Register). Thus, SMI conditions can be
	  pending when bit 0 is set to 1; if an SMI is already pending, the
	  SMI# signal is asserted.
SeeAlso: #P0039

Bitfields for 82374SB SMI enable (register A2h-A3h):
Bit(s)	Description	(Table P0048)
  15-8	Reserved
  7	APMC Write SMI Enable
	=0 writes to the APMC Register do not generate an SMI
	=1 writes to the APMC Register generate an SMI
  6	EXTSMI# SMI Enable
	=1 asserting the EXTSMI# input signal generates an SMI
  5	Fast Off Timer SMI Enable
	=1 Fast-Off timer generates an SMI when it decrements to zero
  4	IRQ12 SMI Enable (PS/2 Mouse Interrupt)
	=1 asserting the IRQ12 input signal generates an SMI
  3	IRQ8 SMI Enable (RTC Alarm Interrupt)
	=1 asserting the IRQ8 input signal generates an SMI
  2	IRQ4 SMI Enable (COM2/COM4 Interrupt or Mouse)
	=1 asserting the IRQ3 input signal generates an SMI
  1	IRQ3 SMI Enable (COM1/COM3 Interrupt or Mouse)
	=1 asserting the IRQ3 input signal generates an SMI
  0	IRQ1 SMI Enable (Keyboard Interrupt)
	=1 asserting the IRQ1 input signal generates an SMI
SeeAlso: #P0039

Bitfields for 82374SB System Event Enable (register A4h-A7h):
Bit(s)	Description	(Table P0049)
  31	Fast Off SMI Enable (FSMIEN)
	=1 an SMI causes a system event that re-loads the Fast Off Timer and a
	  break event that negates the STPCLK# signal
	=0 an SMI does not re-load the Fast Off Timer or negate the STPCLK#
	  signal
  30	reserved
  29	Fast Off NMI Enable (FNMIEN)
	=1 an NMI (e.g., parity error) causes a system event that re-loads the
	  Fast Off Timer and a break event that negates the STPCLK# signal
	=0 an SMI does not re-load the Fast Off Timer or negate	the STPCLK#
	  signal.
  28-16 reserved
  15-3	These bits are used to prevent the system from entering Fast Off and
	  break any current powerdown state when the selected hardware
	  interrupt (IRQ15-IRQ3) occurs
	=1 the corresponding interrupt causes a	system event that re-loads the
	  Fast Off Timer and a break event that	negates the STPCLK# signal
	=0 the corresponding interrupt does not re-load the Fast Off Timer or
	  negate the STPCLK# signal
  2	reserved
  1-0	These bits are used to prevent the system from entering Fast Off and
	  break any current powerdown state when the selected hardware
	  interrupt (IRQ1-IRQ0) occurs
	=1 the corresponding interrupt causes a	system event that re-loads the
	  Fast Off Timer and a break event that	negates the STPCLK# signal
	=0 the corresponding interrupt does not re-load the Fast Off Timer or
	  negate the STPCLK# signal
SeeAlso: #P0039

Bitfields for 82374SB SMI Request (register AAh-ABh):
Bit(s)	Description	(Table P0050)
  15-8	Reserved
  7	APM SMI Status (RAPMC): set to 1 to indicate that a write to the APM
	  Control Register caused an SMI
  6	EXTSMI# SMI Status (REXT): set to 1 when EXTSMI# caused an SMI
  5	Fast Off Timer Expired Status (RFOT): set to 1 to indicate that the
	  Fast Off Timer expired and caused an SMI.  The Fast Off  timer
	  re-starts counting on the next clock after it expires.
  4	SMI caused by IRQ12
  3	SMI caused by IRQ8
  2	SMI caused by IRQ4
  1	SMI caused by IRQ3
  0	SMI caused by IRQ1
SeeAlso: #P0039
----------P00220023--------------------------
PORT 0022-0023 - CHIPSET FROM ETEC CHEETAH ET6000 (SINGLE CHIP)

0022  RW  chip set data
0023  ?W  index for accesses to data port (see #P0051)

(Table P0051)
Values for Etec Cheetah ET6000 chip set register index:
 10h	system configuration register (see #P0052)
 11h	cache configuration & non-cacheable block size register (see #P0053)
 12h	non-cacheable block address register
	bit 7-1	non-cacheable address, A25-A19
	bit 0	reserved
 13h	DRAM bank & type configuration register (see #P0054)
 14h	DRAM configuration register (see #P0055)
 15h	shadow RAM configuration register (see #P0056)

Bitfields for Etec Cheetah ET6000 system configuration register:
Bit(s)	Description	(Table P0052)
 7-6	00 turbo/non-turbo
	01 local device supported
	10 suspend mode
	11 illegal
 5	reserved
 4	refresh selection
	0 = AT type refresh
	1 = concurrent refresh
 3	slow refresh  95mSec enabled
 2	fast reset delay
	0 = do not use delay
	1 = wait for 2mSec delay
 1	wait for HALT after KBDRST
 0	RAM at A0000-BFFFF
	0 = AT bus cycle
	1 = local bus cycle
SeeAlso: #P0051

Bitfields for Etec Cheetah ET6000 cache configuration register:
Bit(s)	Description	(Table P0053)
 7-5	000 disabled
	001 512K
	010 1M
	011 2M
	100 4M
	101 8M
	110 16M
	111 32M
 4	DRAM banks
	0 = 2-bank DRAM
	1 = 4-bank DRAM
 3-0	reserved
SeeAlso: #P0051

Bitfields for Etec Cheetah ET6000 DRAM bank & type configuration register:
Bit(s)	Description	(Table P0054)
 7-6	bank 3 DRAM type
	00 none
	01 256K
	10 1M
	11 4M
 5-4	bank 2 DRAM type
 3-2	bank 1 DRAM type
 1-0	bank 0 DRAM type
SeeAlso: #P0051

Bitfields for Etec Cheetah ET6000 DRAM configuration register:
Bit(s)	Description	(Table P0055)
 7	on-board memory range 15M to 16M disabled
 6	on-board memory range 512K-640K disabled
 5	ROM chip select at C0000-DFFFF enabled
 4	RAS to CAS time
	0 = 1 SYSCLCK,	not for R0WS
	1 = 2 SYSCLCK
 3	RAS precharge time
	0 = 1.5 SYSCLCK
	1 = 2.5 SYSCLCK
 2-1	read cycle wait state
	00 = 0 wait state
	01 = 1 ws
	10 = 2 ws
	11 = 3 ws
 0	write cycle wait state
	0 = 0 ws
	1 = 1 ws
SeeAlso: #P0051

Bitfields for Etec Cheetah ET6000 shadow RAM configuration register:
Bit(s)	Description	(Table P0056)
 7	shadow at C0000-FFFFF
	0 = non-cacheable
	1 = cacheable and cache-write-proteced
 6	access ROM/RAM at F0000-FFFFF
	0 = read from ROM, write to RAM
	1 = read from shadow, write is protected
 5	access ROM/RAM at E0000-EFFFF
	0 = access on-board ROM, AT bus cycle
	1 = access shadow E0000-EFFFF enabled
 4	RAM at E0000-EFFFF is read-only
 3	access ROM/RAM at D0000-DFFFF
	0 = access on-board ROM, AT bus cycle
	1 = access shadow D0000-DFFFF enabled
 2	RAM at D0000-DFFFF is read-only
 1	access ROM/RAM at C0000-CFFFF
	0 = access on-board ROM, AT bus cycle
	1 = access shadow C0000-CFFFF enabled
 0	RAM at C0000-CFFFF is read-only
SeeAlso: #P0051
----------P00220023--------------------------
PORT 0022-0023 - Hewlett-Packard Hornet chipset (HP 100LX/200LX)

0022  RW  index for accesses to data port (see Table P189)
0023  RW  chip set data

(Table P0057)
Values for HP Hornet chipset register index:
 1Eh	buzzer volume/clock oscillator speed
	bit 7-6: buzzer volume
	bit 5-4: system oscillator speed
		00: 10.738636MHz
		01: 15.836773MHz(HP 100/200LX has oscillator with this speed)
		10: 21.477272MHz
		11: 31.673550MHz
 21h	display timing???
 23h	LCD contrast (see INT15h AH=62h)
	valid values: 00h-1fh (1fh is the darkest)
 51h	power adapter status
	bit 7-1: ???
	bit 0: power adapter status(0=inactive/1=active)
 52h	nicad charge status
	bit 7-3: ???
	bit 2: battery charging status(0=???/1=slow charge)
	bit 1-0: ???
 53h	nicad charge status
	bit 7-1: ???
	bit 0: battery charging status(0=???/1=fast charge)
 80h	memory wait for internal ROM
	valid values: 00h-07h
 81h	memory wait for internal RAM
	valid values: 00h-03h
 82h	memory wait for external RAM
	valid values: 00h-0fh
 87h	battery status???
----------P00220023--------------------------
PORT 0022-0023 - Chips&Technologies 82C100/110 - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)

0022  -W  configuration register index (see #P0058)
0023  RW  configuration register data

(Table P0058)
Values for Chips&Technologies 82C100/110 configuration register index:
 40h	clock mode/size (see #P0059)
 41h	system configuration (see #P0060)
 42h	configuration valid (see #P0061)
 43h	DIP switch emulation (see #P0062)
 44h-47h substitute NMI vector, bytes 0-3
	(these specify the vector to be substituted at the INT 02 vector's
	  memory address whenever an NMI occurs, preventing application
	  software from modifying the NMI handler)
 48h	refresh timer counter (see #P0063)
 49h	wait state select, refresh enable, keyboard type (see #P0064)
 4Ah	reserved
 4Bh	sleep/memory configuration (see #P0065)
 4Ch	EMS configuration (see #P0066)
 4Dh-4Fh reserved

Bitfields for Chips&Technologies 82C100 clock mode/size register:
Bit(s)	Description	(Table P0059)
 !!!
!!!chips\82c110.pdf p.35
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C100 system configuration register:
Bit(s)	Description	(Table P0060)
 !!!
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C100 configuration valid register:
Bit(s)	Description	(Table P0061)
 !!!
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C110 DIP Switch Emulation register:
Bit(s)	Description	(Table P0062)
 !!!chips\82c110.pdf p.36
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C100 refresh timer count register:
Bit(s)	Description	(Table P0063)
 !!!
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C100 wait state select register:
Bit(s)	Description	(Table P0064)
 !!!
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C100 sleep/memory configuration:
Bit(s)	Description	(Table P0065)
 !!!
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C100 EMS configuration register:
Bit(s)	Description	(Table P0066)
 !!!
SeeAlso: #P0058
----------P00220023--------------------------
PORT 0022-0023 - Chips&Technologies 82C235 "SCAT" - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)

0022  -W  configuration register index (see #P0067)
0023  RW  configuration register data

(Table P0067)
Values for Chips&Technologies 82C235 configuration register index:
 01h	DMA wait-state control
 40h	version (read-only)
 41h	clock control
 42h-43h reserved (but listed as read-write in docs)
 44h	peripheral control
 45h	miscellaneous status
 46h	power management
 47h	reserved
 48h	ROM enable
 49h	RAM write-protect control
 4Ah	shadow RAM enable 1
 4Bh	shadow RAM enable 2
 4Ch	shadow RAM enable 3
 4Dh	DRAM configuration
 4Eh	extended boundary
 4Fh	EMS control
 !!!chips\82c235.pdf p.87, p.140
----------P00220023--------------------------
PORT 0022-0023 - Chips&Technologies 82C311 - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)

0022  -W  configuration register index (see #P0068)
0023  RW  configuration register data

(Table P0068)
Values for Chips&Technologies 82C311 configuration register index:
 04h	version (read-only)   !!!chips\82c311.pdf p.65
 05h	AT-bus command delay
 06h	AT-bus wait-state control
 08h	identification
 09h	low RAM/ROM configuration
 0Ch	memory enable map (80000h-9FFFFh)
 0Dh	memory enable map (A0000h-BFFFFh)
 0Eh	memory enable map (C0000h-DFFFFh)
 0Fh	memory enable map (E0000h-FFFFFh)
 10h	block 0 type and start address
 11h	block 0 DRAM timing
 12h	block 1 type and start address
 13h	block 1 DRAM timing
 14h	block 2 type and start address
 15h	block 2 DRAM timing
 16h	block 3 type and start address
 17h	block 3 DRAM timing
 18h	memory block types
 20h	cache control
 21h	directory RAM control 1
 22h	tag RAM directory address (low)
 23h	reference location
 24h	SRAM configuration/direct access address
 25h	directory RAM control 2
 26h	READY timeout
 28h	error source/address
 29h	error address (bits 23-16)
 2Ah	memory enable map (00000h-7FFFFh)
 2Bh	miscellaneous control
 2Ch	middle RAM/ROM configuration
 2Fh	page mode posted-write control (82C311 rev. C only)
 30h	block 0 non-cacheable address (bits 23-16)
 31h	block 0 non-cacheable address (bits 15-12) and size
 32h	block 1 non-cacheable address (bits 23-16)
 33h	block 1 non-cacheable address (bits 15-12) and size
 34h	block 2 non-cacheable address (bits 23-16)
 35h	block 2 non-cacheable address (bits 15-12) and size
 36h	block 3 non-cacheable address (bits 23-16)
 37h	block 3 non-cacheable address (bits 15-12) and size
 38h	block 0/1 non-cacheable addresses (bits 26-24)
 39h	block 2/3 non-cacheable addresses (bits 26-24)
 60h	fast reset control
!!!chips\82c311.pdf p.76, p.115
----------P00220023--------------------------
PORT 0022-0023 - Chips&Technologies 82C315 - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)
SeeAlso: PORT 0022h"82C311",PORT 0022h"82C316"

0022  -W  configuration register index (see #P0069)
0023  RW  configuration register data

(Table P0069)
Values for Chips&Technologies 82C315 configuration register index:
 07h	processor and bus clock source selection (see #P0070)

Bitfields for C&T 82C315 clock source selection register:
Bit(s)	Description	(Table P0070)
 7-5	reserved (0)
 4	80387 is present
 3	processor clock select
	=0 CLK2IN
	=1 AT bus state machine clock
 2-0	bus clock source select
	000 CLK2IN/5
	001 CLK2IN/4
	010 CLK2IN/3
	011 CLK2IN/2
	100 ATCLK
SeeAlso: #P0069
----------P00220023--------------------------
PORT 0022-0023 - Chips&Technologies 82C316 - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)
SeeAlso: PORT 0022h"82C311",PORT 0022h"82C315",PORT 0022h"82C811"

0022  -W  configuration register index (see #P0071)
0023  RW  configuration register data

(Table P0071)
Values for Chips&Technologies 82C316 configuration register index:
 01h	clock/wait-state control	!!!chips\cs8233.pdf p.178
 26h	RTC/NMI/Coprocessor reset	!!!chips\cs8233.pdf p.231
 71h	programmable I/O port 1 address, bits 15-8
 72h	programmable I/O port 1 address, bits 7-0
 73h	programmable I/O port 1 enable
 74h	programmable I/O port 2 address, bits 15-8
 75h	programmable I/O port 2 address, bits 7-0
 76h	programmable I/O port 2 enable
 77h	programmable I/O port 3 address, bits 15-8
 78h	programmable I/O port 3 address, bits 7-0
 79h	programmable I/O port 3 enable
SeeAlso: #P0069
--------h-P00220023--------------------------
PORT 0022-0023 - Chips&Technologies 82C811/82C812 - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)
SeeAlso: PORT 0022h"82C311",PORT 0022h"82C315"

0022  -W  configuration register index (see #P0072)
0023  RW  configuration register data

(Table P0072)
Values for Chips&Technologies 82C811/812 configuration register index:
 60h	(82C811) processor clock select (see #P0073)
 61h	(82C811) command delay (see #P0074)
 62h	(82C811) wait states (see #P0075)
---82C812---
 64h	version (see #P0076)
 65h	ROM configuration
 66h	memory enable 1
 67h	memory enable 2
 68h	memory enable 3
 69h	memory enable 4
 6Ah	bank 0/1 enable
 6Bh	memory configuration
 6Ch	bank 2/3 enable
 6Dh	EMS base address
 6Eh	EMS address extension
 6Fh	miscellaneous
!!!chips\cs8281.pdf p.48

Bitfields for C&T 82C811 processor clock select:
Bit(s)	Description	(Table P0073)
 7-6	82C811 release number (00 = initial release)
 5	fast CPU reset initiated by changing this bit from 0 to 1
 4	processor clock
	0 CLK2IN (default)
	1 BCLK
 3	reserved
 2	enable NMI generate on timeout of local-bus READY# signal
 1	reserved
 0	local-bus READY# signal timed out (128 clock cycles0
SeeAlso: #P0072,#P0074,#P0075

Bitfields for C&T 82C811 command delay register:
Bit(s)	Description	(Table P0074)
 7	enable additional address bus hold time
 6	reserved (1)
 5-4	AT-bus 16-bit memory access delay, in BCLK cycles (default = 0)
 3-2	AT-bus 8-bit memory access delay, in BCLK cycles (default = 1)
 1-0	I/O command delay, in BCLK cycles (default = 1)
SeeAlso: #P0072,#P0073,#P0075

Bitfields for C&T 82C811 wait states register:
Bit(s)	Description	(Table P0075)
 7	80387sx is present
 6	coprocessor is ready
 5-4	AT-bus 16-bit cycle wait states (default = 3)
 3-2	AT-bus 8-bit cycle wait states (00=two ... 11=five [default])
 1-0	bus clock (BCLK)
	00 CLK2IN/2 (default)
	01 CLK2IN/3
	10 ATCLK
	11 reserved
SeeAlso: #P0072,#P0073,#P0074

Bitfields for C&T 82C812 version register:
Bit(s)	Description	(Table P0076)
 7	NEATsx memory controller (0 = 82C812)
 6-5	82C812 revision (00 = initial release)
 4-0	reserved
SeeAlso: #P0072
--------h-P00220023--------------------------
PORT 0022-0023 - Chips&Technologies 84031/84035 - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)
SeeAlso: PORT 0022h"82C311",PORT 0022h"82C315"

0022  -W  configuration register index (see #P0077)
0023  RW  configuration register data

(Table P0077)
Values for Chips&Technologies 84031/84035 configuration register index:
 01h	(84035) IPC DMA controller wait states and clock (see #P0078)
!!!chips\82310.pdf p.71
!!!chips\api22.pdf p.33
 05h	(84031) ISA-bus command delays (see #P0079)
 06h	(84031) ISA-bus wait states (see #P0080)
 07h	(84031) ISA-bus clock select (see #P0081)
 08h	(84035) performance control (see #P0082)
 09h	(84035) miscellaneous control (see #P0083)
 0Ah	(84035) DMA clock select (see #P0084)
 10h	(84031) DRAM timing (see #P0085)
!!!chips\api22.pdf p.49
 11h	(84031) DRAM setup
 12h	(84031) block 0/1 DRAM configuration
 13h	(84031) block 2/3 DRAM configuration
 14h	(84031) DRAM block 0 start address
 15h	(84031) DRAM block 1 start address
 16h	(84031) DRAM block 2 start address
 17h	(84031) DRAM block 3 start address
 18h	(84031) video shadow / local bus control
 19h	(84031) shadow RAM read enable
 1Ah	(84031) shadow RAM write enable
 1Bh	(84031) ROMCS enable
 1Ch	(84031) soft reset / GATEA20

Bitfields for C&T 84035 IPC DMA controller configuration:
Bit(s)	Description	(Table P0078)
 7-6	reserved
 5-4	wait states for 16-bit DMA
	00 one (default)
	01 two
	10 three
	11 four
 3-2	wait states for 8-bit DMA (settings same as bits 5-4)
 1	disable one-cycle delay of MEMR# signal	after IOR#
 0	DMA clock (0 = BUSCLK/2 [default], 1 = BUSCLK)
SeeAlso: #P0077,#P0082

Bitfields for C&T 84031 ISA-bus command delays:
Bit(s)	Description	(Table P0079)
 !!!
SeeAlso: #P0077,#P0080,#P0081

Bitfields for C&T 84031 ISA-bus wait states:
Bit(s)	Description	(Table P0080)
 !!!
SeeAlso: #P0077,#P0079,#P0081

Bitfields for C&T 84031 ISA-bus clock select:
Bit(s)	Description	(Table P0081)
 !!!
SeeAlso: #P0077,#P0079,#P0080

Bitfields for C&T 84035 performance control:
Bit(s)	Description	(Table P0082)
 7	flush 486 cache during every slow-mode hold (keeps CPU from running out
	  of L1 cache during holds)
 6-0	width of CPU hold pulse in BUSCLKs (0-127)
SeeAlso: #P0077,#P0078,#P0083

Bitfields for C&T 84035 miscellaneous control:
Bit(s)	Description	(Table P0083)
 7	floating-point error mode
	=0 generate IRQ13 internally on FERR#
	=1 use external logic to generate IRQ13
 6	keyboard interrupt mode
	=0 receive IRQ1 directly on IRQ1 pin
	=1 receive IRQ1 over control link
 5	disable GATEA20 emulation
	=0 A20 controlled solely by PORT 0092h
	=1 A20 is OR of PORT 0092h and emulated 8042 A20 control
 4	A20M#/TEST# function
	=0 pin is TEST# input
	=1 pin is A29M# output
 3	reserved
 2	enable 8254 Timer 1 refresh requests
	clearing this bit prevents problems that may be caused by a refresh
	  request which occurs during a reset sequence
 1	use VL-bus-compatible preemptive arbitration for LGNT#
 0	deturbo mode (enable CPU holds as specified by performance-control
	  register) (see #P0082)
Note:	the documentation says that bit 6 should remain clear
SeeAlso: #P0077,#P0082

Bitfields for C&T 84035 DMA clock select:
Bit(s)	Description	(Table P0084)
 7	disable internal real-time clock
 6-4	reserved (0)
 3-0	DMA clock
	0000 SCLK/10
	0001 SCLK/8
	0010 SCLK/6
	1000 SCLK/5 (use with 40 MHz SCLK)
	1001 SCLK/4 (use with 33 MHz SCLK)
	1010 SCLK/3 (use with 25 MHz SCLK)
	1011 SCLK/2.5 (for 20 MHz SCLK)
	1100 SCLK/2 (for 16 MHz SCLK)
	1101 SCLK/1.5
	else reserved
Note:	bits 3-0 should normally be set the same as register 07h bits 3-0
SeeAlso: #P0077

Bitfields for C&T 84031 DRAM timing:
Bit(s)	Description	(Table P0085)
 7-6	reserved (0)
 5
 4
 3
 2	!!!
 1	reserved (0)
 0	read timing
	0 = 3-2-2-2
	1 = 4-3-3-3
SeeAlso: #P0077,#P0086

Bitfields for C&T 84031 DRAM setup:
Bit(s)	Description	(Table P0086)
 7	enable DRAM parity
	(PORT 0061h bits 7 and 2 must also both be clear to enable parity)
 6-4	reserved (0)
 3-0	enable interleave for banks 3-0
	(enabling interleave doubles address range for bank; banks 0/2 and 1/3
	  may be interleaved with each other)
SeeAlso: #P0077,#P0085
----------P00220023--------------------------
PORT 0022-0023 - OPTi 82C206 chipset - CONFIGURATION REGISTERS
Note:	many other OPTi chipsets integrate the functionality of the 82C206, and
	  thus support the 82C206's configuration register (e.g. the
	  82C558 from the Viper chipset)

0022  ?W  index for accesses to data port (set to 01h)
0023  RW  chip set data

Bitfields for OPTi 82C206 configuration register 01h:
Bit(s)	Description	(Table P0087)
 7-6	82C206 wait states
	00 1 SYSCLK
	01 2 SYSCLKs
	10 3 SYSCLKs
	11 4 SYSCLKs (default)
 5-4	number of wait states for 16-bit DMA cycles
	00 1 wait state (default)
	01 2 wait states
	10 3 wait states
	11 4 wait states
 3-2	number of wait states for 8-bit DMA cycles
	00 1 wait state (default)
	01 2 wait states
	10 3 wait states
	11 4 wait states
 1	enable early DMAMEMR#
 0	DMA speed
	0 SYSCLK/2
	1 SYSCLK
----------P00220023--------------------------
PORT 0022-0023 - Intel 82091AA Advanced Integrated Peripheral
Range:	PORT 0022h (X-Bus), PORT 0024h (X-Bus), PORT 026Eh (ISA), or
	  PORT 0398h (ISA)
SeeAlso: PORT 0024h"82091AA",PORT 026Eh"82091AA",PORT 0398h"82091AA"

0022  ?W  configuration register index (see #P0088)
0023  RW  configuration register data

(Table P0088)
Values for Intel 82091AA configuration register index:
 00h	product ID (read-only)
	A0h Intel 82091AA
 01h	product revision (read-only) (see #P0089)
 02h	configuration 1 (see #P0090)
 03h	configuration 2 (see #P0091)
 04h-0Fh reserved
 10h	floppy-disk controller configuration (see #P0092)
 11h	floppy-disk controller power management/status (see #P0093)
 12h-1Fh reserved
 20h	parallel port configuration (see #P0094)
 21h	parallel port power management/status (see #P0095)
 22h-2Fh reserved
 30h	serial port A configuration (see #P0096)
 31h	serial port A power management/status (see #P0097)
 32h-3Fh reserved
 40h	serial port B configuration (see #P0096)
 41h	serial port B power management/status (see #P0097)
 42h-4Fh reserved
 50h	IDE configuration (see #P0098)
 51h-FFh reserved

Bitfields for Intel 82091AA product revision register:
Bit(s)	Description	(Table P0089)
 7-4	stepping number 
 3-0	"dash"-number
SeeAlso: #P0088

Bitfields for Intel 82091AA configuration register 1:
Bit(s)	Description	(Table P0090)
 7	unused (0)
 6	supply voltage (read-only) (1 = 3.3V, 0 = 5.0V)
 5-4	configuration mode
	00 software motherboard
	01 software add-in
	10 extended hardware
	11 basic hardware
 3	configuration address (read-only)
	0 primary address (PORT 0022h for X-Bus, PORT 026Eh for ISA)
	1 secondary address (PORT 0024h for X-Bus, PORT 0398h for ISA)
 2-1	reserved
 0	power-down AIP's main clock circuitry
SeeAlso: #P0088,#P0091

Bitfields for Intel 82091AA configuration register 2:
Bit(s)	Description	(Table P0091)
 7-3	IRQ7-IRQ3 mode select
	0 = active high (ISA-compatible tri-state drive)
	1 = active low (EISA-compatible open-collector drive)
 2-0	reserved
SeeAlso: #P0088,#P0090

Bitfields for Intel 82091AA floppy-disk controller configuration register:
Bit(s)	Description	(Table P0092)
 7	four floppy drive support enabled (with external decoder)
 6-2	reserved
 1	FDC address
	0 = primary (03F0h)
	1 = secondary (0370h)
 0	enable FDC
SeeAlso: #P0088,#P0093

Bitfields for Intel 82091AA floppy-disk controller power management register:
Bit(s)	Description	(Table P0093)
 7-4	reserved
 3	enable FDC auto-powerdown on idle
 2	reset FDC
	(this bit must be pulsed, remaining high for at least 1.2 us)
 1	(read-only) FDC is idle
 0	power-down FDC
Note:	to restore FDC from explicit powerdown via bit 0, clear bit 0, then
	  reset the FDC using bit 2 (hardware reset) or using a software reset
	  (FDC's DOR bit 2 or DSR bit 7)
SeeAlso: #P0088,#P0092

Bitfields for Intel 82091AA parallel port configuration:
Bit(s)	Description	(Table P0094)
 7	FIFO threshold
	0 = 8 slots in each direction
	1 = one slot forward, 15 reverse
 6-5	parallel-port hardware mode
	00 ISA-compatible
	01 PS/2-compatible
	10 EPP
	11 ECP (read only -- ECP mode must be set via ECP Extended Control Reg)
 4	reserved
 3	IRQ select
	0 = IRQ5
	1 = IRQ7
 2-1	address select
	00 PORT 0378h-037Bh
	01 PORT 0278h-027Bh
	10 PORT 03BCh-03BEh (not for EPP mode)
	11 reserved
 0	enable parallel port
SeeAlso: #P0088,#P0095,#P0920,PORT 0678h"ECP"

Bitfields for Intel 82091AA parallel port power managment register:
Bit(s)	Description	(Table P0095)
 7-6	reserved
 5	FIFO overrun or underrun has occurred
	this bit is cleared by resetting the port via bit 2
 4	reserved
 3	enable auto-powerdown
 2	reset parallel port (pulse this bit; must remain high for 1.13 us)
 1	(read-only) parallel port is idle
 0	power-down parallel port
Note:	an explicit power-down may be canceled by either clearing bit 0 or
	  pulsing bit 2 to reset the port
SeeAlso: #P0088,#P0094

Bitfields for Intel 82091AA serial port configuration:
Bit(s)	Description	(Table P0096)
 7	enable 2MHz MIDI clock for MIDI baud rate
 6-5	reserved
 4	IRQ select
	0 = IRQ3
	1 = IRQ4
 3-1	address select
	000 PORT 03F8h-03FFh
	001 PORT 02F8h-02FFh
	010 PORT 0220h-0227h
	011 PORT 0228h-022Fh
	100 PORT 0238h-023Fh
	101 PORT 02E8h-02EFh
	110 PORT 0338h-033Fh
	111 PORT 03E8h-03EFh
 0	enable serial port
Note:	although it is possible to configure both serial ports at the same
	  address, this is not recommended because the 82091AA disables serial
	  port B without placing it into powerdown mode
SeeAlso: #P0088,#P0097

Bitfields for Intel 82091AA serial port power management register:
Bit(s)	Description	(Table P0097)
 7-5	reserved
 4	enable test mode
	when enabled, and DLAB bit in LCR is set, the baud rate clock is output
	  on the SOUTA pin
 3	enable auto-powerdown on idle
 2	reset serial port (should be pulsed, high for at least 1.13 us)
 1	(read-only) serial port is idle
 0	power-down serial port
Notes:	setting powerdown mode via bit 0 resets both receiver and transmitter,
	  including the FIFOs, so software should check that port is idle
	  before powering it down
	the serial port may be brought out of an explicit powerdown by either
	  clearing bit 0 or pulsing bit 2
SeeAlso: #P0088,#P0096

Bitfields for Intel 82091AA IDE configuration:
Bit(s)	Description	(Table P0098)
 7-3	reserved
 2	enable both primary and secondary addresses
 1	address select (when bit 2 is clear)
	0 PORT 01F0h-01F7h and 03F6h (primary)
	1 PORT 0170h-0177h and 0376h (secondary)
 0	enable IDE interface
 !!!intel\29048603.pdf p.45
SeeAlso: #P0088,#P0092
----------P00220024--------------------------
PORT 0022-0024 - CHIPSET FROM PICO POWER, UMC or PCChips

0022  ?W  index for accesses to data port
0024  RW  chip set data
----------P00220024--------------------------
PORT 0022-0024 - OPTi 82C281/282/283 CHIPSETS - CONFIGURATION REGISTERS
Note:	every access to PORT 0024h must be preceded by a write to PORT 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"

0022  ?W  index for accesses to data port (see #P0099)
0024  RW  chip set data

(Table P0099)
Values for OPTi 82C281/82C282/82C283 configuration register index:
 10h	DRAM configuration register (see #P0100)
 11h	Shadow RAM control register (see #P0101)
 12h	Shadow RAM control register 2 (see #P0102)
 13h	Shadow RAM control register 3 (see #P0103)
 14h	miscellaneous control register (see #P0104)
 15h	cache control register (see #P0105)
 16h	cache control register 2 (see #P0106)

Bitfields for OPTi 82C281/282/283 DRAM configuration register:
Bit(s)	Description	(Table P0100)
 7-6	82C281/2 revision number (read-only)
 7	82C283 revision (0 = A, 1 = B)
 6	82C283A: reserved
	82C283B: DRAM is pipelined
 5	local DRAM read wait states
	82C281/2: 0=one, 1=two	  82C283: 0=none, 1=one
 4	local DRAM write wait states
	82C281/2: 0=one, 1=two	  82C283: 0=none, 1=one
 3-0	local DRAM memory configuration
	(val)	Bank0	Bank1	Bank2	Bank3
	0001	256K	256K	256K	256K
	0010	256K	256K	1M	-
	0011	256K	256K	1M	1M
	0100	256K	256K	4M	-
	0101	1M	-	-	-
	0110	1M	1M	-	-
	0111	1M	1M	1M	-
	1000	1M	1M	1M	1M
	1001	1M	4M	-	-
	1010	1M	1M	4M	-
	1011	4M	4M	-	-
	1100	4M	-	-	-  (82C283B only)
	1111	256K	256K	-	-
SeeAlso: #P0099

Bitfields for OPTi 82C281 shadow RAM control register:
Bit(s)	Description	(Table P0101)
 7	BIOS ROM F000-FFFF shadowing
	0 read-only from shadow RAM
	1 read from ROM, write to shadow RAM
 6	adapter ROM at E000-EFFF
	0 disable shadow RAM
	1 shadow RAM selectively enabled by configuration register 12h
	  (see #P0102)
 5	adapter ROM at D000-DFFF
	0 disable shadow RAM
	1 shadow RAM selectively enabled by configuration register 12h
 4	adapter ROM at C000-CFFF
	0 disable shadow RAM
	1 shadow RAM selectively enabled by configuration register 13h
	  (see #P0103)
 3	shadow RAM Copy Enable control (C000-EFFF)
	0 write to expansion bus
	1 write to local DRAM
 2	shadow RAM E000-EFFF writeability
	0 read/write
	1 read-only
 1	shadow RAM D000-DFFF writeability
	0 read/write
	1 read-only
 0	shadow RAM C000-CFFF writeability
	0 read/write
	1 read-only
SeeAlso: #P0099,#P0102

Bitfields for OPTi 82C281 shadow RAM control register 2:
Bit(s)	Description	(Table P0102)
 7	enable EC00-EFFF
 6	enable E800-EBFF
 5	enable E400-E7FF
 4	enable E000-E3FF
 3	enable DC00-DFFF
 2	enable D800-DBFF
 1	enable D400-D7FF
 0	enable D000-D3FF
Note:	bits 7-4 are only in effect when register 11h bit 6 is set; bits 3-0
	  are only in effect when register 11h bit 5 is set
SeeAlso: #P0099,#P0101,#P0103

Bitfields for OPTi 82C281 shadow RAM control register 3:
Bit(s)	Description	(Table P0103)
 7	enable CC00-CFFF
 6	enable C800-CBFF
 5	enable C400-C7FF
 4	enable C000-C3FF
 3-0	unused shadow RAM remap address; supplies bits 23-20 of
	  address at which to map A000-BFFFF and D000-EFFF is not used
	  for shadowing (except if this field is set to 0, the remapping
	  is disabled)
SeeAlso: #P0099,#P0101,#P0102

Bitfields for OPTi 82C281 miscellaneous control register:
Bit(s)	Description	(Table P0104)
 7	allow F0000-F0FFF to be written even while F0000-FFFFF is
	  write-protected ("Zenith mode")
 6	keyboard reset control
	=1 HLT must be executed before 82C281 generates CPU reset from
	    keyboard controller Reset command
 5	master byte swap enable
 4	82C281/2: fast NMI request
	82C283A: reserved (0)
	82C283B: ATCLK setting (=0 from register 14h bit 0; =1 CLK/8)
 3	82C281/2/3A: reserved
	82C283B: on-board DRAM parity error enable
 2	enable slow refresh mode
	(every 95.5 us (281/282) or 63.6 us (283) instead of 15.9 us)
 1	enable turbo switch function
 0	clock select
	=0 ATCLK2 = CPUCLK2 / 6
	=1 ATCLK2 = CPUCLK2 / 4
SeeAlso: #P0099

Bitfields for OPTi 82C281/82C282 cache control register:
Bit(s)	Description	(Table P0105)
 7	enable cache
 6	reserved (0)
 5	enable posted write (82C281 only)
 4	ALL accesses are non-cacheable
 3	reserved (0)
 2-0	non-cacheable region size (see also #P0106)
	000  64K
	001 128K
	...
	101  4M
	110  8M
	111 disabled
SeeAlso: #P0099,#P0106

Bitfields for OPTi 82C281/82C282 cache control register 2:
Bit(s)	Description	(Table P0106)
 7-0	starting address bits 23-16 of non-cacheable region
Note:	the specified starting address must be a multiple of the region size
SeeAlso: #P0099,#P0105
----------P00220024--------------------------
PORT 0022-0024 - OPTi 82C291/82C295 CHIPSETS - CONFIGURATION REGISTERS
Note:	every access to PORT 0024h must be preceded by a write to PORT 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"

0022  ?W  index for accesses to data port (see #P0107)
0024  RW  chip set data

(Table P0107)
Values for OPTi 82C291/82C295 configuration register index:
 20h	Revision/AT Bus configuration register (see #P0108)
 21h	System Control register (see #P0109)
 22h	DRAM configuration register (see #P0110)
 23h	ROM Chip Select Control register (see #P0111)
 24h	Shadow RAM control register E (see #P0112)
 25h	Shadow RAM control register D (see #P0113)
 26h	Shadow RAM control register C (see #P0114)
 27h	Shadow RAM Write Protect/Remap Area (see #P0115)
 28h	Cache Control register (see #P0116)
 29h	Cacheable Upper Bound register (see #P0117)
 2Ah	Non-Cacheable Segments register 1 (see #P0118)
 2Bh	Non-Cacheable Segments register 2 (see #P0119)
 2Ch	Non-Cacheable Segments register 3 (see #P0120)

Bitfields for OPTi 82C291/82C295 AT Bus configuration register:
Bit(s)	Description	(Table P0108)
 7-6	82C291/295 revision (read-only)
 5-4	back-to-back I/O recovery time
	00-11 = 3-6 ATCLKs between I/O accesses
 3	enable slow refresh mode
 2	enable hidden refresh
 1-0	AT clock selection
	00 ATCLK = CLK2 / 10
	01 ATCLK = CLK2 / 8
	10 ATCLK = CLK2 / 6
	11 ATCLK = CLK2 / 4
SeeAlso: #P0107

Bitfields for OPTi 82C291/82C295 System Control register:
Bit(s)	Description	(Table P0109)
 7	AT bus master byte swap enabled
 6	ALE generation for each AT cycle
	0 a new ALE will be generated during bus conversion cycles
	1 multiple ALEs will be generated during bus conversion cycles
 5	keyboard fast reset emulation control
	0 enable, a "Halt" is required before a fast CPU reset is generated
	1 disable, fast CPU reset is generated directly after the "FE" I/O
	  command to port 64h is decoded
 4	AT cycle additional wait state
	0 disable, standard AT cycle
	1 enable, inserts one extra wait state in standard AT bus cycle
 3-2	reserved
 1	local device ready control
	0 RDYI# input to the 82C291 will be synchronized and set as RDY# to
	  the CPU one T-state delayed
	1 RDYI# input to the 82C291 will not be output to the CPU. RDY# from
	  the local device must be directed to the 82C291 and the CPU
 0	system memory parity checking
	0 disable, no parity checking	     
	1 enable, will check parity
SeeAlso: #P0107

Bitfields for OPTi 82C291/82C295 DRAM Configuration register:
Bit(s)	Description	(Table P0110)
 7-6	number of DRAM read cycle wait states
 5-4	number of DRAM write cycle wait states
 3-0	Banks 0 thru 3 DRAM configuration
	(val)	Bank0	Bank1	Bank2	Bank3
	0000	256K	256KB	-	-
	0001	256K	256K	256K	256K
	0010	256K	256K	1M	-
	0011	256K	256K	1M	1M
	0100	256K	256K	4M	-
	0101	1M	-	-	-
	0110	1M	1M	-	-
	0111	1M	1M	1M	-
	1000	1M	1M	1M	1M
	1001	1M	4M	-	-
	1010	1M	1M	4M	-
	1011	4M	-	-	-
	1100	4M	4M	-	-
	1101	reserved
	1110	reserved
	1111	reserved
SeeAlso: #P0107

Bitfields for OPTi 82C291/82C295 ROM Chip Select Control register:
Bit(s)	Description	(Table P0111)
 7	enable ROM Chip Select for write cycles (to support flash ROMs)
 6	enable ROMCS# for 0F0000-0FFFFF segments
 5	enable ROMCS# for 0E8000-0EFFFF segments
 4	enable ROMCS# for 0E0000-0E7FFF segments
 3	enable ROMCS# for 0D8000-0DFFFF segments
 2	enable ROMCS# for 0D0000-0D7FFF segments
 1	enable ROMCS# for 0C8000-0CFFFF segments
 0	enable ROMCS# for 0C0000-0C7FFF segments
SeeAlso: #P0107

Bitfields for OPTi 82C291/82C295 Shadow RAM control register E:
Bit(s)	Description	(Table P0112)
 7	enable shadow RAM reads for EC000-EFFFF segments
 6	enable shadow RAM reads for E8000-EBFFF segments
 5	enable shadow RAM reads for E4000-E7FFF segments
 4	enable shadow RAM reads for E0000-E3FFF segments
 3	enable shadow RAM writes for EC000-EFFFF segments
 2	enable shadow RAM writes for E8000-EBFFF segments
 1	enable shadow RAM writes for E4000-E7FFF segments
 0	enable shadow RAM writes for E0000-E3FFF segments
Note:	OPTi documentation incorrectly states the segment range for bits 5
	  and 1 as E4000-E7000.
SeeAlso: #P0107

Bitfields for OPTi 82C291/82C295 Shadow RAM control register D:
Bit(s)	Description	(Table P0113)
 7	enable shadow RAM reads for DC000-DFFFF segments
 6	enable shadow RAM reads for D8000-DBFFF segments
 5	enable shadow RAM reads for D4000-D7FFF segments
 4	enable shadow RAM reads for D0000-D3FFF segments
 3	enable shadow RAM writes for DC000-DFFFF segments
 2	enable shadow RAM writes for D8000-DBFFF segments
 1	enable shadow RAM writes for D4000-D7FFF segments
 0	enable shadow RAM writes for D0000-D3FFF segments
Note:	OPTi documentation incorrectly states the segment range for bits 5
	  and 1 as D4000-D7000.
SeeAlso: #P0107

Bitfields for OPTi 82C291/82C295 Shadow RAM control register C:
Bit(s)	Description	(Table P0114)
 7	enable shadow RAM reads for CC000-CFFFF segments
 6	enable shadow RAM reads for C8000-CBFFF segments
 5	enable shadow RAM reads for C4000-C7FFF segments
 4	enable shadow RAM reads for C0000-C3FFF segments
 3	enable shadow RAM writes for CC000-CFFFF segments
 2	enable shadow RAM writes for C8000-CBFFF segments
 1	enable shadow RAM writes for C4000-C7FFF segments
 0	enable shadow RAM writes for C0000-C3FFF segments
Note:	OPTi documentation incorrectly states the segment range for bits 5
	  and 1 as C4000-C7000.
SeeAlso: #P0107

Bitfields for OPTi 82C291/82C295 Shadow RAM Write Protect/Remap Area:
Bit(s)	Description	(Table P0115)
 7	enable Write Protect for F0000-FFFFF segments
 6	enable Write Protect for E0000-EFFFF segments
 5	enable Write Protect for D0000-DFFFF segments
 4	enable Write Protect for C0000-CFFFF segments
 3-0	DRAM remap starting address, bits 23-20
	0000  disabled, no mapping
	0001  1M
	0010  2M
	...
	1111 15M
SeeAlso: #P0107

Bitfields for OPTi 82C291/82C295 Cache Control register:
Bit(s)	Description	(Table P0116)
 7	enable write-back cache controller operation
 6	enable DRAM performance mode
	this bit should not be enabled unless external cache is disabled
	  (intended to optimize DRAM performance)
 5	enable all memory accesses no-cacheable mode
 4	enable 640K-1M area no-cacheable mode
 3-2	cache timing control bits
	00 invalid
	01 0 wait state cache write w/o CAWE# extended, use when 8K*8 SRAMs
	10 1 wait state cache write hit
	11 0 wait state cache write hit with CAWE# extended when 32K*8 SRAMs
 1-0	cache size/cacheable DRAM
	00  16K /  2M
	01  32K /  4M
	10  64K /  8M
	11 128K / 16M
SeeAlso: #P0107

Bitfields for OPTi 82C291/82C295 Cacheable Upper Bound register:
Bit(s)	Description	(Table P0117)
 7-4	reserved
 3-0	cacheable upper bound address, bits 23-20
	0000  feature disabled
	0001  1M
	0010  2M
	...
	1111 15M
SeeAlso: #P0107

Bitfields for OPTi 82C291/82C295 Non-Cacheable Segments register 1:
Bit(s)	Description	(Table P0118)
 7	enable non-cacheable segment A
 6-4	size of no-cacheable memory segment A
	000  64K
	001 128K
	010 256K
	011 512K
	100   1M
	101   2M
	110   4M
	111   8M
 3	enable non-cacheable segment B
 2-0	size of no-cacheable memory segment B (same values as bits 6-4)
SeeAlso: #P0107,#P0119
    
Bitfields for OPTi 82C291/82C295 Non-Cacheable Segments register 2:
Bit(s)	Description	(Table P0119)
 7-0	address bits 23-16 for starting address of non-cacheable memory
	  segment A
SeeAlso: #P0107,#P0118,#P0120

Bitfields for OPTi 82C291/82C295 Non-Cacheable Segments register 3:
Bit(s)	Description	(Table P0120)
 7-0	address bits 23-16 for starting address of non-cacheable memory
	  segment B
SeeAlso: #P0107,#P0118,#P0119
----------P00220024--------------------------
PORT 0022-0024 - OPTi 82C381/82C382 CHIPSETS - CONFIGURATION REGISTERS
Note:	every access to PORT 0024h must be preceded by a write to PORT 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"

0022  ?W  index for accesses to data port (see #P0121)
0024  RW  chip set data

(Table P0121)
Values for OPTi 82C381/82C382 configuration register index:
 00h	clock selects (see #P0122)
 01h	reset control (see #P0123)
 10h	remapping address (see #P0124)
 11h	shadow RAM (see #P0125)
 12h	memory enable (see #P0126)
 13h	bank configuration (see #P0127)
 14h	DRAM configuration (see #P0128)
 15h	video adapter shadow (see #P0129)
 16h	fast GateA20 (see #P0130)
 17h	cache configuration (see #P0131)
 18h	non-cacheable block 1 size (see #P0132)
 19h	non-cacheable block 1 address (see #P0133)
 1Ah	non-cacheable block 2 size (see #P0132)
 1Bh	non-cacheable block 2 address (see #P0133)
 1Ch	cacheable area (see #P0134)
Note:	registers 00h and 01h address the 82C381, the remaining registers
	  address the 82C382
SeeAlso: #P0189

Bitfields for OPTi 82C381/82C382 clock selects:
Bit(s)	Description	(Table P0122)
 7-6	cache controller enable
	00 cache controller disabled (default)
	01 cache controller disabled; PPCS#, SPCS#, NPCS# signals are
	      active if selected
	10 external cache controller installed
	11 on-chip cache controller installed
 5	hot CPU reset (low->high transition generates reset)
 4	enable ATCLK stretch
 3	turbo clock
	=0 CLKIN is CPU clock
	=1 HIGH pin selected clock (HIGH=0: CLKIN, HIGH=1: ICLK)
 2-1	ICLK clock select
	00 CLKIN/4 (default)
	01 CLKIN/3
	10 CLKIN/2
	11 reserved
 0	master byte swap enable (default = 0)
SeeAlso: #P0121,#P0123

Bitfields for OPTi 82C381/82C382 reset control:
Bit(s)	Description	(Table P0123)
 7-2	reserved
 1	RESET3 control
	=1 generate RESET3 on RESET2 only after a HLT instruction
	=0 generate RESET3 immediately on RESET2 (default)
 0	activate cache controller FLUSH# pin (default = 1)
SeeAlso: #P0121,#P0122,#P0124

Bitfields for OPTi 82C381/82C382 remapping address:
Bit(s)	Description	(Table P0124)
 7-5	reserved
 4	enable remapping
 3-0	remap address range, bits 23-20
	0000  no mapping
	0001  1M
	0010  2M
	...
	1111 15M
SeeAlso: #P0121

Bitfields for OPTi 82C381/82C382 shadow RAM control:
Bit(s)	Description	(Table P0125)
 7	BIOS ROM at F0000-FFFFF Shadowing
	0 read only from shadow RAM
	1 read from ROM, write to shadow RAM
 6	ROM at D0000-DFFFF
	0 disable shadow RAM
	1 shadow RAM selectively enabled by configuration register 12h
 5	Adaptor ROM at E0000-EFFFF
	0 disable shadow RAM
	1 shadow RAM selectively enabled by configuration register 12h
 4	write-protect shadow RAM at D0000h-DFFFFh (default = not protected)
 3	write-protect shadow RAM at E0000h-EFFFFh
 2	enable Timeout precharge counter 
 1-0	reserved
SeeAlso: #P0121

Bitfields for OPTi 82C381/82C382 memory enable:
Bit(s)	Description	(Table P0126)
 7	enable EC000-EFFFF
 6	enable E8000-EBFFF
 5	enable E4000-E7FFF
 4	enable E0000-E3FFF
 3	enable DC000-DFFFF
 2	enable D8000-DBFFF
 1	enable D4000-D7FFF
 0	enable D0000-D3FFF
Note:	0 = disable Shadow RAM (default), 1 = enable Shadow RAM
SeeAlso: #P0121

Bitfields for OPTi 82C381/82C382 memory bank configuration:
Bit(s)	Description	(Table P0127)
 7	Reserved
 6-4	Bank0 and Bank1 configuration
	(val)	Bank0	 Bank1 
	000	256K	 -  
	001	256K	 256K
	010	256K	 1M  
	011	1M	 256K
	100	1M	 -  
	101	1M	 1M 
	110	-	 -  
	111	256K	 - 
 3	reserved
 2-0	Bank2 and Bank3 configuration
	(val)	Bank2	 Bank3 
	000	256K	 -  
	001	256K	 256K
	010	-	 -  
	011	1M	 256K
	100	1M	 -  
	101	1M	 1M 
	11X	-	 -  
SeeAlso: #P0121,#P0128

Bitfields for OPTi 82C381/82C382 DRAM configuration:
Bit(s)	Description	(Table P0128)
 7,6	number of read cycle wait states (default = 01)
 5	write cycle wait state
	0 = 0 wait 
	1 = 1 wait (default)	  
 4-0	reserved	
SeeAlso: #P0121

Bitfields for OPTi 82C381/82C382 video adapter shadow:
Bit(s)	Description	(Table P0129)
 7	reserved
 6	copy enable for C0000-EFFFF
	0 write to AT Channel (default) 
	1 write to local DRAM
 5	Shadow RAM at C0000-CFFFF writability
	0 read/write (default)
	1 read only
 4	ROM at C0000-CFFFF
	0 disable shadow RAM
	1 shadow RAM selectively enabled by Bits<0:3> (default)
 3	enable Shadow RAM at CC000-CFFFF
 2	enable Shadow RAM at C8000-CbFFF
 1	enable Shadow RAM at C4000-C7FFF
 0	enable Shadow RAM at C0000-C3FFF
SeeAlso: #P0121

Bitfields for OPTi 82C381/82C382 fast GateA20 control:
Bit(s)	Description	(Table P0130)
 7-4	Reserved
 3	Fast GateA20 Control  
	0 Signal controled by GATEA20 signal from Keyboard Controler
	1 CPUA20 enabled onto GA20
 2-0	reserved	
SeeAlso: #P0121

Bitfields for OPTi 82C381/82C382 cache configuration:
Bit(s)	Description	(Table P0131)
 7	force NCA* Output Pin low
	if this bit is clear, it has no effect on NCA* Output Pin
 6	enable Cache
 5	write-through cache (Note: this bit must be set)
 4-3	line size
	00  4 bytes 
	01  8 bytes
	10  16 bytes
	11  reserved
 2-0	reserved	
SeeAlso: #P0121

Bitfields for OPTi 82C381/82C382 non-cacheable block size:
Bit(s)	Description	(Table P0132)
 7-5	block size
	000 64K
	001 128K
	010 256K
	011 512K
	100 1M
	101 4M (block 1 only)
	101 reserved (block 2 only)
	110 8M (block 1 only)
	110 reserved (block 2 only)
	111 disabled (default)
 4-0	reserved (0)
SeeAlso: #P0121,#P0131,#P0133

Bitfields for OPTi 82C381/82C382 non-cacheable block address:
Bit(s)	Description	(Table P0133)
 7-0	bits 23-16 of non-cacheable block's address
Note:	the selected address must be a multiple of the block size
	  selected by register 18h/1Ah
SeeAlso: #P0121,#P0132,#P0134

Bitfields for OPTi 82C381/82C382 cacheable area:
Bit(s)	Description	(Table P0134)
 7-4	cacheable address range
	0000 16M
	0001 1M
	0010 2M
	0011 3M
	...
	1111 15M
 3	256K remapped area is cacheable
 2-0	reserved
SeeAlso: #P0121
----------P00220024--------------------------
PORT 0022-0024 - OPTi 82C463MV CHIPSET - CONFIGURATION REGISTERS
Desc:	the 82C463MV contains a memory control unit (MCU), an AT Bus
	  Control Unit (BCU), a Power Management Unit (PMU), data
	  buffers and a 82C206 type IPC (without real time clock)
Note:	every access to PORT 0024h must be preceded by a write to PORT 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"

0022  ?W  index for accesses to data port (see #P0135)
0024  RW  chip set data

(Table P0135)
Values for OPTi 82C463MV configuration register index:
 30h	general control 1 (see #P0136)
 31h	general control 2 (see #P0137)
 32h	shadow RAM control 1 (see #P0138)
 33h	shadow RAM control 2 (see #P0139)
 34h	DRAM size (see #P0140)
 35h	DRAM timing and caching control (see #P0141)
 36h	shadow RAM control 3 (see #P0142)
 37h	D000h and E000h segment access control (see #P0143)
 38h	non-cacheable block 1 size, controls and address bit A24 (see #P0144)
 39h	non-cacheable block 1 address bits A23-A16
 3Ah	non-cacheable block 2 size and address bit A24 (see #P0145)
 3Bh	non-cacheable block 2 address bits A23-A16
 3Ch-3Fh	reserved
 40h	PMU control 1 (see #P0146)
 41h	PMU control 2: doze timer (see #P0147)
 42h	PMU control 3: other timers (see #P0148)
 43h	PMU control 4 (see #P0149)
 44h	LCD timer count (should not be loaded with a value <5)
 45h	disk timer count (should not be loaded with a value <5)
 46h	keyboard timer count (should not be loaded with a value <5)
 47h	GNR_ACCESS timer count (should not be loaded with a value <5)
 48h	GNR_ACCESS I/O base address (lines A8-A1, A0 is a "don't care")
 49h	GNR_ACCESS control and I/O base address line A9 (see #P0150)
 4Ah	CSG0# base address (lines A8-A1, A0 is a "don't care")
 4Bh	CSG0# control and base address line A9 (see #P0151)
 4Ch	CSG1# base address (lines A8-A1, A0 is a "don't care")
 4Dh	CSG1# control and base address line A9 (see #P0152)
 4Eh	idle timer control (see #P0153)
 4Fh	idle timer count (should not be loaded with a value <5)
 50h	suspend/resume control (see #P0154)
 51h	beeper/sequencer control (see #P0155)
 52h	PMU general-purpose storage 1
 53h	PMU general-purpose storage 2
 54h	PMU Periferal Power (PPWR) control 1 (see #P0156)
 55h	PMU Periferal Power (PPWR) control 2 (see #P0157)
 56h	PIO control 1 (see #P0158)
 57h	PIO control 2 (see #P0159)
 58h	PMU event control 1 (see #P0160)
 59h	PMU event control 2 (see #P0161)
 5Ah	PMU event control 3 (see #P0162)
 5Bh	PMU event control 4 (see #P0163)
 5Ch	SMI source (low) (see #P0164)
 5Dh	SMI source (high) (see #P0165)
 5Eh	clock stretching control (see #P0166)
 5Fh	resume interrupt control (see #P0167)
 60h	software sequencer address (write only)
 61h	debounce control (see #P0168)
 62h	doze-mode IRQ selects (see #P0169)
 63h	idle timer IRQ selects (see #P0170)
 64h	PMI#6 IRQ select (see #P0171)
 65h	doze-mode configuration (see #P0172)
 66h	suspend control (see #P0173)
 67h	CPU frequency (see #P0174)
 68h	timer clock source (see #P0175)
 69h	R_TIMER count (should not be loaded with a value <5)
 6Ah	resume IRQ selects (see #P0176)
 6Bh	resume sources (see #P0177)
 6Ch-6Fh	TMP0 - TMP3

Bitfields for 82C463MV general control 1 (register 30h):
Bit(s)	Description	(Table P0136)
 7-6	chipset revision number (read only)
 5	MASTER#/RI pin function (RI = modem Ring Indicator)
	=1 RI (default)
	=0 MASTER#
 4	enable turbo VGA
 3	enable global relocation/translation for SMI addresses (see also
	  register 31h bit 4 at #P0137)
 2	enable extra wait state in AT cycle
 1	fast reset control
	  =1 does not require Halt instruction
	  =0 requires Halt instruction before generation of CPURST (SRESET
	       if Intel SL Enhanced or Cyrix Cx486S/S2 CPUs
 0	reserved (0)
SeeAlso: #P0135

Bitfields for 82C463MV general control 2 (register 31h):
Bit(s)	Description	(Table P0137)
 7	enable master byte swap
 6	reserved, read-only (1)
 5	disable parity check
 4	Dynamic SMI relocation
	  if no SMI sequence is running
	    =1 allow relocation of addresses from the CPU in the 3000h/4000h
	       segment to the B000h/A000h SMI memory space
	    =0 disable relocation
	  if SMI sequence is running (qualified by SMIACT#)
	    =1 allow data accesses to the 3000h and 4000h segments
	    =0 relocate all accesses in the 3000h/4000h segment to the
	       B000h/A000h SMI segment (normal operation)
	  if SMI sequence is running (qualified by SMIADS#)
	    =1 not allowed
	    =0 for a SMIADS# cycle, relocate all accesses in the 6000h/7000h
	       segment to the A000h/B000h SMI segment
	       for a normal ADS# operation, there is no relocation
 3	EC000h-EFFFFh access control
	if register 36h bit 6=0
	  =1 R/W from ROMCS#
	  =0 R/W from AT-Bus
	if register 36h bit 6=1
	  =1 Read from ROMCS# if not shadowed (see register 33h bits 7-4),
		write to DRAM
	  =0 Read from AT-Bus if not shadowed (see register 33h bits 7-4),
		write to DRAM
 2	E8000h-EBFFFh access control (see bit 3)
 1	E4000h-E7FFFh access control (see bit 3)
 0	E0000h-E3FFFh access control (see bit 3)
SeeAlso: #P0135,#P0139,#P0142

Bitfields for 82C463MV shadow RAM control 1 (register 32h):
Bit(s)	Description	(Table P0138)
 7	segment F000h access control
	  =1 read from ROMCS#, write to ROMCS# (if register 36h bit 7=1)
	     or DRAM (if register 36h bit 7=0)
	  =0 read from DRAM and write protect (enable shadowing)
 6-5	reserved (1)
 4	write protect segment D000h
 3	write protect segment E000h
 2	reserved, read-only (1)
 1	reserved (0)
 0	ALE control
	  =1 single ALE during bus conversion
	  =0 multiple ALE
SeeAlso: #P0135,#P0142,#P0139

Bitfields for 82C463MV shadow RAM control 2 (register 33h):
Bit(s)	Description	(Table P0139)
 7	enable shadowing for EC000h-EFFFFh
 6	enable shadowing for E8000h-EBFFFh
 5	enable shadowing for E4000h-E7FFFh
 4	enable shadowing for E0000h-E3FFFh
 3	enable shadowing for DC000h-DFFFFh
 2	enable shadowing for D8000h-DBFFFh
 1	enable shadowing for D4000h-D7FFFh
 0	enable shadowing for D0000h-D3FFFh
SeeAlso: #P0135,#P0138

Bitfields for 82C463MV DRAM size (register 34h):
Bit(s)	Description	(Table P0140)
 7-4	DRAM Bank 0 and 1 Size
	0000 256K, unused
	0001 256K, 256K
	0010 256K, 1M
	0011 256K, 4M
	0100 512K, unused
	0101 512K, 512K
	0110 512K, 1M
	0111 512K, 4M
	1000 1M, unused
	1001 1M, 1M
	1010 1M, 4M
	1011 4M, 1M
	1100 4M, unused
	1101 4M, 4M
	1110 1M, 2M
	1111 both unused
 3-0	DRAM Bank 2 and 3 Size
	0000 1M, unused
	0001 1M, 1M
	0010 1M, 4M
	0011 4M, 4M
	0100 4M, unused
	0101 both unused
	0110 1M, 2M
	0111 512K, 512K
	10xx both unused
	110x both unused
	1110 2M, unused
	1111 2M, 2M (default)
SeeAlso: #P0135

Bitfields for 82C463MV DRAM timing and caching control (register 35h):
Bit(s)	Description	(Table P0141)
 7-6	DRAM read wait states
	00 = 0 wait states, burst mode 2-1-1-1
	01 = 1 wait state, burst mode 3-1-1-1
	10 = 1 wait state, burst mode 3-2-2-2
	11 = 2 wait states, burst mode 4-3-3-3 (default)
 5-4	DRAM write wait states
	00 = 0 wait states
	01 = 1 wait state
	10 = 2 wait states
	11 = reserved (default)
 3	MP2/STRAP2 status (read-only)
	=1 1X Clock
	=0 2X Clock
 2	disable caching of F000h segment (this bit is effective only when
	  register 32h bit 7 =0)
 1	global DRAM cache control (1=disable, default)
 0	disable caching of C0000h-C7FFFh (default)
SeeAlso: #P0135,#P0138

Bitfields for 82C463MV shadow RAM control 3 (register 36h):
Bit	Description	(Table P0142)
 7	segment F000h write control
	=1 write to ROMCS#
	=0 write to DRAM
	don't care if register 32h bit 7=0
 6	C0000h-EFFFFh control
	=1 read from AT-Bus or ROMCS# (if ROMCS# is enabled to that block),
	  write to DRAM
	=0 R/W from AT bus or ROMCS# (if ROMCS# is enabled to that block)
 5	write protect segment C000h
 4	reserved (1)
 3	enable shadowing for CC000h-CFFFFh
 2	enable shadowing for C8000h-CBFFFh
 1	enable shadowing for C4000h-C7FFFh
 0	enable shadowing for C0000h-C3FFFh
SeeAlso: #P0135,#P0138

Bitfields for 82C463MV D000h and E000h segments access control (register 37h):
Bit	Description	(Table P0143)
 7	DC000h-DFFFFh access control
	if register 36h bit 6=1
	    =1 read from ROMCS# if not shadowed, write to DRAM
	    =0 read from AT-Bus if not shadowed, write to DRAM
	if register 36h bit 6=0
	    =1 R/W from ROMCS#
	    =0 R/W from AT-Bus
 6	D8000h-DBFFFh access control (see bit 7)
 5	D4000h-D7FFFh access control (see bit 7)
 4	D0000h-D3FFFh access control (see bit 7)
 3	disable caching for EC000h-EFFFFh (default)
 2	disable caching for E8000h-EBFFFh (default)
 1	disable caching for E4000h-E7FFFh (default)
 0	disable caching for E0000h-E3FFFh (default)
SeeAlso: #P0135,#P0142

Bitfields for non-cacheable block 1 size, control and A24 (register 38h):
Bit(s)	Description	(Table P0144)
 7-5	size of non-cacheable memory block 1
	000 64K
	001 128K
	010 256K
	011 1M
	1xx disabled (default)
 4	CC000h-CFFFFh access control
	if register 36h bit 6=1
	    =1 read from ROMCS# if not shadowed, write to DRAM
	    =0 read from AT-Bus if not shadowed, write to DRAM
	if register 36h bit 6=0
	    =1 R/W from ROMCS#
	    =0 R/W from AT-Bus
 3	C8000h-CBFFFh access control (see bit 4)
 2	C4000h-C7FFFh access control (see bit 4)
 1	C0000h-C3FFFh access control (see bit 4)
 0	address bit A24 of non-cacheable memory block 1
SeeAlso: #P0135,#P0142

Bitfields for non-cacheable block 2 size and A24 (register 3Ah):
Bit(s)	Description	(Table P0145)
 7-5	size of non-cacheable memory block 2
	000 64K
	001 128K
	010 256K
	011 1M
	1xx disabled (default)
 4	unused
 3	enable internal HLDA latch during stop clock (must be disabled
	  before DMA transfers are performed)
 2	reserved (1)
 1	unused
 0	address bit A24 of non-cacheable memory block 2
SeeAlso: #P0135

Bitfields for 82C463MV PMU control 1 (register 40h):
Bit	Description	(Table P0146)
 7	Reset/SMI indication (read-only)
	=1 the last read or fetch from address XXXFFFF0h was a SMIADS#
	     cycle
	=0 the last read or fetch from address XXXFFFF0h was a regular
	     ADS# cycle
 6	divide global timer by 4
 5	LLOWBAT polarity selector
	=1 low active
	=0 high active
 4	LOWBAT polarity selector (see bit 5)
 3	SQWIN input clock frequency
	=1 128KHz
	=0 32KHz
 2	external EPMI2 pin polarity
	=1 active low
	=0 active high
 1	external EPMI1 pin polarity (see bit 2)
 0	send reset pulse during resume
Note:	for 1X clock with Intel SL Enhanced CPU, bit 6 must be =1
SeeAlso: #P0135,#P0147,#P0148

Bitfields for 82C463MV PMU control 2 (doze timer, register 41h):
Bit(s)	Description	(Table P0147)
 7-5	hardware doze time-out selector
	101 512 ms
	110 2 sec
	111 8 sec
 4-2	hardware doze-mode CPU clock selector
	000 CPUCLK/1
	001 CPUCLK/2
	010 CPUCLK/4
	011 CPUCLK/8 (should be used during CPU stop clock only)
	100 CPUCLK/16 (should be used during CPU stop clock only)
	101 CPUCLK/3
	110 reserved
	111 reserved
 1	enable LCD_ACCESS, KBD_ACCESS, DSK_ACCESS access to auto trigger
	  the hardware doze timer
 0	disable hardware doze-mode (enable APM doze-mode support)
SeeAlso: #P0135,#P0146,#P0148

Bitfields for 82C463MV PMU control 3 (timers other than doze, register 42h):
Bit(s)	Description	(Table P0148)
 7-6	clock source for general-purpose timer
	00 SQW0
	01 SQW1
	10 SQW2
	11 SQW3
 5-4	clock source for keyboard timer (see bits 7-6)
 3-2	clock source for disk timer (see bits 7-6)
 1-0	clock source for LCD timer (see bits 7-6)
SeeAlso: #P0135,#P0147,#P0149

Bitfields for 82C463MV PMU control 4 (register 43h):
Bit(s)	Description	(Table P0149)
 7	disable monitoring of PORT 3B0h-3DFh
 6	disable monitoring of memory range A0000h-BFFFFh
 5-4	LOWBAT pin sample rate
	if register 40h bit 6 =1
	    00 32 seconds
	    01 64 seconds
	    10 128 seconds
	    11 reserved
	if register 40h bit 6	 =0
	    00 8 seconds
	    01 16 seconds
	    10 32 seconds
	    11 reserved
 3	reserved (0)
 2-0	AT clock select
	000 OSCCLK2/8
	001 OSCCLK2/6
	010 OSCCLK2/4
	011 OSCCLK2/3
	100 OSC14/2 (7.2 MHz)
	111 stop
SeeAlso: #P0135,#P0146,#P0149,#P0150

Bitfields for 82C463MV GNR_ACCESS control, I/O base address line A9 (reg. 49h):
Bit(s)	Description	(Table P0150)
 7	GNR_ACCESS I/O base address bit A9
 6	enable compare in WRITE cycle
 5	enable compare in READ cycle
 4-0	I/O address A5-A1 mask bits. For each bit =1, the corresponding bit
	  in register 48h is not compared (this is used to determine I/O
	  address block size)
SeeAlso: #P0135,#P0149

Bitfields for 82C463MV CSG0# control and base address line A9 (register 4Bh):
Bit(s)	Description	(Table P0151)
 7	Programmable Chip Select 0 (CSG0#) - I/O base address line A9
 6	enable CSG0# for I/O write cycles
 5	enable CSG0# for I/O read cycles
 4	=1 CSG0# active before ALE
	=0 CSG0# active just like I/O command pulse
 3-0	I/O address A4-A1 mask bits. For each bit =1, the corresponding bit
	  in register 4Ah (bits 4-1) is not compared (this is used to
	  determine I/O address block size)
SeeAlso: #P0135,#P0152

Bitfields for 82C463MV CSG1# control and base address line A9 (register 4Dh):
Bit(s)	Description	(Table P0152)
 7	Programmable Chip Select 1 (CSG1#) - I/O base address line A9
 6	enable CSG1# for I/O write cycles
 5	enable CSG1# for I/O read cycles
 4	=1 CSG1# active before ALE
	=0 CSG1# active just like I/O command pulse
 3-0	I/O address A4-A1 mask bits. For each bit =1, the corresponding bit
	in register 4Ch (bits 4-1) is not compared (this is used to
	determine I/O address block size)
SeeAlso: #P0135,#P0151

Bitfields for OPTi 82C463MV idle timer control (register 4Eh):
Bit	Description	(Table P0153)
 7	CSG1 access
 6	CSG0 access
 5	LPT access (it refers to PORT 378h-37Fh, PORT 278h-27Fh and
	  PORT 3BCh-3BFh)
 4	COM access (it refers to PORT 3F8h-3FFh and PORT 2F8h-2FFh)
 3	GNR_ACCESS
 2	KBD_ACCESS
 1	DSK_ACCESS
 0	LCD_ACCESS
Note:	If a bit is =1, the corresponding access will reload IDLE_TIMER
	  otherwise not.
SeeAlso: #P0135

Bitfields for 82C463MV suspend/resume control (register 50h):
Bit	Description	(Table P0154)
 7	software generation of SMI (enabled by bit 7 of register 59h)
	  writing 1 asserts SMI to CPU to start SMM operation
	  writing 0 clears the SMI (the SMI routine must clear this bit)
 6	reserved (0)
 5	IRQ8 active level
	=1 high active
	=0 low active
 4	disable the internal 14.3MHz clock (to conserve power)
 3	start doze-mode / read DOZE_TIMER status
	write: start APM doze-mode
	    =1 start doze-mode (if register 40h bit 0 =1)
	    =0 no effect
	read: hardware DOZE_TIMER time-out status bit
	    =1 hardware DOZE_TIMER has timed out
	    =0 hardware DOZE_TIMER still counting
 2	Ready To Resume (RTR), read-only
 1	PMU mode (read-only)
	=1 suspend-mode still active
	=0 all other modes
 0	start suspend-mode (write only)
	=1 start suspend-mode
	=0 no effect
SeeAlso: #P0135,#P0146,#P0161

Bitfields for 82C463MV beeper/sequencer control (register 51h):
Bit(s)	Description	(Table P0155)
 7-2	sequencer base address translated-to A17-A12 (A19-A18 are always 1
	  during this operation)
 1-0	beeper control (independent from PORT 61h)
	if register 40h bit 6 =1
	    00 no action
	    01 1KHz
	    10 off
	    11 2KHz
	if register 40h bit 6 =0
	    00 no action
	    01 4KHz
	    10 off
	    11 8KHz
SeeAlso: #P0135,#P0146

Bitfields for 82C463MV PMU Periferal Power (PPWR) control 1 (register 54h):
Bit(s)	Description	(Table P0156)
 7-4	write mask of PPWR low nibble
	=1 enable write on corresponding bit
	=0 write disable
 3-0	read/write data bits for PPWR (low nibble)
SeeAlso: #P0135,#P0157

Bitfields for 82C463MV PMU Periferal Power (PPWR) control 2 (register 55h):
Bit(s)	Description	(Table P0157)
 7-4	write mask of PPWR high nibble
	=1 enable write on corresponding bit
	=0 write disable
 3-0	read/write data bits for PPWR (high nibble) (default =1)
SeeAlso: #P0135,#P0156

Bitfields for OPTi 82C463MV PIO control 1 (register 56h):
Bit(s)	Description	(Table P0158)
 7-4	write mask of PIO bits 3-0
	=1 enable write on corresponding bit
	=0 write disable
 3-0	read/write data bits for PIO
SeeAlso: #P0135,#P0159,#P0173

Bitfields for OPTi 82C463MV PIO control 2 (register 57h):
Bit	Description	(Table P0159)
 7	enable refresh (BIOS must set this bit to 1 after power up)
 6	enable interrupts to generate PMI #6 (see also #P0167,#P0171)
 5	disable monitoring floppy drive accesses
 4	disable monitoring hard drive accesses
 3	PIO3/STPGNT# pin direction
	=1 output
	=0 input
 2	PIO2/CPUSPD pin direction (see bit 3)
 1	PIO1/NOWS# pin direction (see bit 3)
 0	PIO0 pin direction (see bit 3)
SeeAlso: #P0135,#P0158

Bitfields for OPTi 82C463MV PMU event control 1 (register 58h):
Bit(s)	Description	(Table P0160)
 7-6	LOWBAT PMI #3 configuration
	00 disable
	01 sequencer
	10 reserved
	11 SMI
 5-4	EPMI2 PMI #2 configuration (see bits 7-6)
 3-2	EPMI1 PMI #1 configuration (see bits 7-6)
 1-0	LLOWBAT PMI #0 configuration (see bits 7-6)
SeeAlso: #P0135

Bitfields for OPTi 82C463MV PMU event control 2 (register 59h):
Bit(s)	Description	(Table P0161)
 7	global software SMI enable (see also bit 7 of register 50h at #P0154)
 6	reload timers during a resume sequence
 5-4	resume or INTR PMI #6 and Suspend PMI #7 configuration
	00 disable
	01 sequencer
	10 reserved
	11 SMI
 3-2	R_TIMER PMI #5 configuration (see bits 5-4)
 1-0	IDLE_TIMER PMI #4 configuration (see bits 5-4)
SeeAlso: #P0135

Bitfields for OPTi 82C463MV PMU event control 3 (register 5Ah):
Bit(s)	Description	(Table P0162)
 7-6	GNR_TIMER time out PMI #11 and access PMI #15 configuration
	00 disable
	01 sequencer
	10 reserved
	11 SMI
 5-4	KBD_TIMER time out PMI #10 and access PMI #14 cfg (see bits 7-6)
 3-2	DSK_TIMER time out PMI #9 and access PMI #13 cfg (see bits 7-6)
 1-0	LCD_TIMER time out PMI #8 and access PMI #12 cfg (see bits 7-6)
SeeAlso: #P0135,#P0163

Bitfields for OPTi 82C463MV PMU event control 4 (register 5Bh):
Bit	Description	(Table P0163)
 7	IRQ15 SMI select
	=1 enable SMI select (SMI internally connected to IRQ15) and
	  disable IRQ15 hardware pin function
	=0 disable SMI select (enable IRQ15 pin function as normal)
 6	disable all SMI
 5	enable sequencer
 4	SMI Type
	=0 Intel style SMI (SMM identified by SMIACT#)
	=1 AMD DXLV or Cyrix style SMI (SMM identified by SMIADS#)
	Note:	for Intel-style SMI, the 3000h/4000h segments will relocate to
		  B000h/A000h when in SMM; for AMD/Cyrix, the 7000h/6000h
		  segments will relocate to B000h/A000h when in SMM
 3	enable PMI source #15
 2	enable PMI source #14
 1	enable PMI source #13
 0	enable PMI source #12
SeeAlso: #P0135,#P0162,#P0164

Bitfields for OPTi 82C463MV SMI source (low) (register 5Ch):
Bit	Description	(Table P0164)
 7	PMI #7 - SUSPEND
 6	PMI #6 - RESUME or INTR
 5	PMI #5 - R_TIMER time out
 4	PMI #4 - IDLE_TIMER time out
 3	PMI #3 - LOWBAT pin
 2	PMI #2 - EPMI2 pin (external PMI source)
 1	PMI #1 - EPMI1 pin (external PMI source)
 0	PMI #0 - LLOWBAT pin
SeeAlso: #P0135,#P0165

Bitfields for OPTi 82C463MV SMI source (high) (register 5Dh):
Bit	Description	(Table P0165)
 7	PMI #15 - GNR_ACCESS
 6	PMI #14 - KBD_ACCESS
 5	PMI #13 - DSK_ACCESS
 4	PMI #12 - LCD_ACCESS
 3	PMI #11 - GNR_TIMER
 2	PMI #10 - KBD_TIMER
 1	PMI #9 - DSK_TIMER
 0	PMI #8 - LCD_TIMER
SeeAlso: #P0135,#P0164

Bitfields for OPTi 82C463MV clock stretching control (register 5Eh):
Bit	Description	(Table P0166)
 7	enable CPU clock stretch memory code cycle
 6	enable CPU clock stretch write cycle
 5	enable CPU clock stretch read cycle
 4	enable CPU clock stretch I/O cycle
 3	enable CPU clock stretch memory data cycle
 2	enable stop ATCLK when not in AT bus cycle
 1	ATCLK stretch
	=1 synchronous
	=0 asynchronous
 0	reserved (0)
SeeAlso: #P0135

Bitfields for OPTi 82C463MV resume interrupt control (register 5Fh):
Bit(s)	Description	(Table P0167)
 7	LCD_ACCESS includes AT bus video access
 6	LCD_ACCESS includes Local bus video access
 5	enable all resume sources of register 6Ah (see also #P0176,#P0159)
 4	RI counter count out will generate resume
 3-0	number of RI counts
SeeAlso: #P0135

Bitfields for OPTi 82C463MV debounce control (register 61h):
Bit(s)	Description	(Table P0168)
 7-6	LOWBAT and LLOWBAT pin debounce rate select
	if register 40h bit 6 =1
	    00 no debounce
	    01 250 microseconds
	    10 8ms
	    11 500ms
	if register 40h bit 6 =0
	    00 no debounce
	    01 62.5 microseconds
	    10 2 ms
	    11 125 ms
 5-4	SUSP/RSM pin debounce rate select
	if register 40h bit 6 =1
	    00 reserved
	    01 latch high to low edge
	    10 4 ms (low to high)
	    11 8 ms (low to high)
	if register 40h bit 6 =0
	    00 reserved
	    01 latch high to low edge
	    10 1 ms (low to high)
	    11 2 ms (low to high)
 3	reserved (0)
 2	enable STPCLK protocol for switching CPU clock frequencies
 1-0	STPCLK# delay (for use when STPCLK protocol is enabled)
	00 no delay
	01 120 microseconds
	10 240 microseconds
	11 1ms, if register 40h bit 6 set; 240 microseconds if clear
SeeAlso: #P0135,#P0146

Bitfields for OPTi 82C463MV doze-mode IRQ selects (register 62h):
Bit	Description	(Table P0169)
 7	enable IRQ13
 6	enable IRQ8
 5	enable IRQ7
 4	enable IRQ12
 3	enable IRQ5
 2	enable IRQ4
 1	enable IRQ3
 0	enable IRQ0
Notes:	in hardware doze-mode the selected interrupts will be used to re-load
	  the hardware DOZE_TIMER and/or trigger the system out of doze-mode
	in APM doze-mode the selected interrupts will be used to trigger the
	  system out of doze-mode only
SeeAlso: #P0135,#P0172,#P0170

Bitfields for OPTi 82C463MV idle timer IRQ selects (register 63h):
Bit	Description	(Table P0170)
 7	enable EPMI1 (level trigger)
 6	enable IRQ13
 5	enable IRQ8
 4	enable IRQ7
 3	enable IRQ5
 2	enable IRQ4
 1	enable IRQ3
 0	enable IRQ0
SeeAlso: #P0135,#P0169,#P0171

Bitfields for OPTi 82C463MV PMI#6 IRQ selects (register 64h):
Bit	Description	(Table P0171)
 7	enable IRQ14
 6	enable IRQ8
 5	enable IRQ7
 4	enable IRQ6
 3	enable IRQ5
 2	enable IRQ4
 1	enable IRQ3
 0	enable IRQ1
Note:	the value written into this register selects which IRQs generate
	  PMI#6 in normal mode, the value read from this register indicates
	  active IRQs at the time of the read
SeeAlso: #P0135,#P0159,#P0170

Bitfields for OPTi 82C463MV doze-mode configuration (register 65h):
Bit	Description	(Table P0172)
 7	enable monitoring all interrupt signals during hw or sw doze-mode
 6	doze-mode STPCLK protocol selector (see also #P0168)
	=1 STPCLK will latch for stopping the CPU clock (APM)
	     The delay is determined by register 61h bits 1-0
	=0 STPCLK will pulse for changing the frequency of the CPU clock
	  (hw doze-mode).
	     The pulse width is determined by register 61h bits 1-0
 5	enable EPMI1 to reload hardware DOZE_TIMER and exit from hardware or
	  software doze-mode
 4	enable recognition of SMI during APM stop clock
 3	allow IRQ1 to exit from hw or sw doze-mode (write-only)
	(see also #P0169)
 2-0	reserved (0)
SeeAlso: #P0135,#P0173

Bitfields for OPTi 82C463MV suspend control (register 66h):
Bit	Description	(Table P0173)
 7	refresh type during suspend
	=1 self refresh
	=0 normal refresh (refresh rate selected by register 67h bit 6)
 6	KBCLK during suspend
	=1 16 KHz
	=0 7.16 MHz (14.318 MHz /2)
 5	software (APM) CPU stop-clock control
	=1 the CPU clock can be stopped by entering APM doze-mode (that is
	  setting register 50h bit 3 to 1)
	=0 APM doze-mode will use the hw doze-mode clock selected by
	  bits 4-2 of register 41h
 4	avoid asserting HOLD before stopping the clock
 3	PIO3/STPGNT# pin selector
	=1 STPGNT# function (set register 57h bit 3 to input mode)
	    This is for use with CPUs that use the hw stop grant signal
	      to acknowledge stop request
	=0 PIO3 function (set register 57h bit 3 to determine input or
	  output mode)
 2	PIO2/CPUSPD pin selector
	=1 CPUSPD function, CPU speed indicator output (set register 57h
	  bit 2 to output mode)
	=0 PIO2 function (set register 57h bit 2 to determine input or
	  output mode)
 1	PIO1/NOWS# pin selector
	=1 NOWS# function (set register 57h bit 1 to input mode)
	=0 PIO1 function (set register 57h bit 1 to determine input or
	  output mode)
 0	enable CPU clock change request protocol
Note:	for hardware doze mode, bit 5 must be 0
SeeAlso: #P0135,#P0147,#P0154,#P0159,#P0174

Bitfields for OPTi 82C463MV CPU frequency (register 67h):
Bit(s)	Description	(Table P0174)
 7	CPU clock control during suspend
	=1 dynamic CPU (in suspend-mode, bits 2-0 select the CPU clock)
	=0 static CPU (in suspend-mode, 82C463MV stops the CPU clock)
 6	refresh control
	=1 slow refresh (128 ms)
	=0 normal refresh (15 ms for normal operation, 30 ms for suspend mode)
 5	PMU global enabler
 4	reserved (1)
 3	reserved (0)
 2-0	CPU clock frequency
	000 CPUCLK/1
	001 CPUCLK/2
	010 CPUCLK/4
	101 CPUCLK/3
	else reserved
SeeAlso: #P0135

Bitfields for OPTi 82C463MV timer clock source (register 68h):
Bit(s)	Description	(Table P0175)
 7-6	R_TIMER clock source selector
	00 SQW0
	01 SQW1
	10 SQW2
	11 SQW3
 5-4	IDLE_TIMER clock source selector (see bits 7-6)
 3-2	resume recovery time
	if register 40h bit 6 =1
	    00 8 ms
	    01 32 ms
	    10 128 ms
	    11 256 ms
	if register 40h bit 6 =0
	    00 2 ms
	    01 8 ms
	    10 32 ms
	    11 64 ms
 1	enable PPWR bit 1 suspend auto toggle (see also #P0156)
 0	enable PPWR bit 0 suspend auto toggle (see also #P0156)
Note:	bits 1 and 0 are not influenced by mask bits 5 and 4 of register 54h
SeeAlso: #P0135,#P0146

Bitfields for OPTi 82C463MV resume IRQ selects (register 6Ah):
Bit	Description	(Table P0176)
 7	enable EPMI2 (resume on a rising edge)
 6	enable EPMI1 (resume on a rising edge)
 5	enable IRQ8 (resume on a falling edge)
 4	enable IRQ7 (resume on a rising edge)
 3	enable IRQ5 (resume on a rising edge)
 2	enable IRQ4 (resume on a rising edge)
 1	enable IRQ3 (resume on a rising edge)
 0	enable IRQ1 (resume on a rising edge)
SeeAlso: #P0135

Bitfields for OPTi 82C463MV resume sources (register 6Bh):
Bit(s)	Description	(Table P0177)
 7	refresh pulse width during sequencer operation
	=1 6 AT clocks
	=0 4 AT clocks
 6-3	reserved (0)
 2-0	resume sources (read-only)
	001 RI
	010 INTR (as selected in register 6Ah)
	100 SUSP/RSM pin
	else reserved
SeeAlso: #P0135,#P0176
----------P00220024--------------------------
PORT 0022-0024 - OPTi 82C493 System Controller (SYSC) - CONFIGURATION REGISTERS
Desc:	The OPTi 486SXWB contains three chips and is designed for systems
	  running at 20, 25 and 33MHz.	The chipset includes an 82C493 System
	  Controller (SYSC), the 82C392 Data Buffer Controller, and the
	  82C206 Integrated peripheral Controller (IPC).
Note:	every access to PORT 0024h must be preceded by a write to PORT 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"

0022  ?W  configuration register index (see #P0178)
0024  RW  configuration register data

(Table P0178)
Values for OPTi 82C493 System Controller configuration register index:
 20h	Control Register 1 (see #P0179)
 21h	Control Register 2 (see #P0180)
 22h	Shadow RAM Control Register 1 (see #P0181)
 23h	Shadow RAM Control Register 2 (see #P0182)
 24h	DRAM Control Register 1 (see #P0183)
 25h	DRAM Control Register 2 (see #P0184)
 26h	Shadow RAM Control Register 3 (see #P0185)
 27h	Control Register 3 (see #P0186)
 28h	Non-cachable Block 1 Register 1 (see #P0187)
 29h	Non-cachable Block 1 Register 2 (see #P0188)
 2Ah	Non-cachable Block 2 Register 1 (see #P0187)
 2Bh	Non-cachable Block 2 Register 2 (see #P0188)

Bitfields for OPTi-82C493 Control Register 1:
Bit(s)	Description	(Table P0179)
 7-6	Revision of 82C493 (readonly) (default=01)
 5	Burst wait state control
	1 = Secondary cache read hit cycle is 3-2-2-2 or 2-2-2-2
	0 = Secondary cache read hit cycle is 3-1-1-1 or 2-1-1-1 (default)
	(if bit 5 is set to 1, bit 4 must be set to 0)
 4	Cache memory data buffer output enable control
	0 = disable (default)
	1 = enable
	(must be disabled for frequency <= 33Mhz)
 3	Single Address Latch Enable (ALE)
	0 = disable (default)
	1 = enable
	(if enabled, SYSC will activate single ALE rather than multiples
	  during bus conversion cycles)
 2	enable Extra AT Cycle Wait State (default is 0 = disabled)
 1	Emulation keyboard Reset Control
	0 = disable (default)
	1 = enable
	Note:	This bit must be enabled in BIOS default value; enabling this
		  bit requires HALT instruction to be executed before SYSC
		  generates processor reset (CPURST)
 0	enable Alternative Fast Reset (default is 0 = disabled)
SeeAlso: #P0180,#P0186

Bitfields for OPTi-82C493 Control Register 2:
Bit(s)	Description	(Table P0180)
 7	Master Mode Byte Swap Enable
	0 = disable (default)
	1 = enable
 6	Emulation Keyboard Reset Delay Control
	0 = Generate reset pulse 2us later (default)
	1 = Generate reset pulse immediately
 5	disable Parity Check (default is 0 = enabled)
 4	Cache Enable
	0 = Cache disabled and DRAM burst mode enabled (default)
	1 = Cache enabled and DRAM burst mode disabled
 3-2	Cache Size
	00  64KB (default)
	01  128KB
	10  256KB
	11  512KB
 1	Secondary Cache Read Burst Cycles Control
	0 = 3-1-1-1 cycle (default)
	1 = 2-1-1-1 cycle
 0	Cache Write Wait State Control
	0 = 1 wait state (default)
	1 = 0 wait state
SeeAlso: #P0179,#P0186

Bitfields for OPTi-82C493 Shadow RAM Control Register 1:
Bit(s)	Description	(Table P0181)
 7	ROM(F0000h - FFFFFh) Enable
	0 = read/write on write-protected DRAM
	1 = read from ROM, write to DRAM (default)
 6	Shadow RAM at D0000h - EFFFFh Area
	0 = disable (default)
	1 = enable
 5	Shadow RAM at E0000h - EFFFFh Area
	0 = disable shadow RAM (default)
	    E0000h - EFFFFh ROM is defaulted to reside on XD bus
	1 = enable shadow RAM
 4	enable write-protect for Shadow RAM at D0000h - DFFFFh Area
	0 = disable (default)
	1 = enable
 3	enable write-protect for Shadow RAM at E0000h - EFFFFh Area
	0 = disable (default)
	1 = enable
 2	Hidden refresh enable (with holding CPU)
	(Hidden refresh must be disabled if 4Mx1 or 1M x4 bit DRAM are used)
	1 = disable (default)
	0 = enable
 1	unused
 0	enable Slow Refresh (four times slower than normal refresh)
	(default is 0 = disable)
SeeAlso: #P0182

Bitfields for OPTi-82C493 Shadow RAM Control Register 2:
Bit(s)	Description	(Table P0182)
 7	enable Shadow RAM at EC000h - EFFFFh area
 6	enable Shadow RAM at E8000h - EBFFFh area
 5	enable Shadow RAM at E4000h - E7FFFh area
 4	enable Shadow RAM at E0000h - E3FFFh area
 3	enable Shadow RAM at DC000h - DFFFFh area
 2	enable Shadow RAM at D8000h - DBFFFh area
 1	enable Shadow RAM at D4000h - D7FFFh area
 0	enable Shadow RAM at D0000h - D3FFFh area
Note:	the default is disabled (0) for all areas

Bitfields for OPTi-82C493 DRAM Control Register 1:
Bit(s)	Description	(Table P0183)
 7	DRAM size
	0 = 256K DRAM mode
	1 = 1M and 4M DRAM mode
 6-4	DRAM types used for bank0 and bank1
	bits 7-4  Bank0	  Bank1
	0000	  256K	     x
	0001	  256K	  256K
	0010	  256K	    1M
	0011	     x	     x
	01xx	     x	     x
	1000	    1M	     x	(default)
	1001	    1M	    1M
	1010	    1M	    4M
	1011	    4M	    1M
	1100	    4M	     x
	1101	    4M	    4M
	111x	     x	     x
 3	unused
 2-0	DRAM types used for bank2 and bank3
	bits 7,2-0  Bank2  Bank3
	x000	   1M	    x
	x001	   1M	   1M
	x010	    x	    x
	x011	   4M	   1M
	x100	   4M	    x
	x101	   4M	   4M
	x11x	    x	    x  (default)
SeeAlso: #P0184

Bitfields for OPTi-82C493 DRAM Control Register 2:
Bit(s)	Description	(Table P0184)
 7-6	Read cycle additional wait states
	00 not used
	01 = 0
	10 = 1
	11 = 2 (default)
 5-4	Write cycle additional wait states
	00 = 0
	01 = 1
	10 = 2
	11 = 3 (default)
 3	Fast decode enable
	0 = disable fast decode. DRAM base wait states not changed (default)
	1 = enable fast decode. DRAM base wait state is decreased by 1
	Note:	This function may be enabled in 20/25Mhz operation to speed up
		  DRAM access.	If bit 4 of index register 21h (cache enable
		  bit) is enabled, this bit is automatically disabled--even if
		  set to 1
 2	unused
 1-0	ATCLK selection
	00  ATCLK = CLKI/6 (default)
	01  ATCLK = CLKI/4 (default)
	10  ATCLK = CLKI/3
	11  ATCLK = CLK2I/5  (CLKI * 2 /5)
	Note:	bit 0 will reflect the BCLKS (pin 142) status and bit 1 will be
		  set to 0 when 82C493 is reset.
SeeAlso: #P0183,#P0185

Bitfields for OPTi-82C493 Shadow RAM Control Register 3:
Bit(s)	Description	(Table P0185)
 7	unused
 6	Shadow RAM copy enable for address C0000h - CFFFFh
	0 = Read/write at AT bus (default)
	1 = Read from AT bus and write into shadow RAM
 5	Shadow write protect at address C0000h - CFFFFh
	0 = Write protect disable (default)
	1 = Write protect enable
 4	enable Shadow RAM at C0000h - CFFFFh
 3	enable Shadow RAM at CC000h - CFFFFh
 2	enable Shadow RAM at C8000h - CBFFFh
 1	enable Shadow RAM at C4000h - C7FFFh
 0	enable Shadow RAM at C0000h - C3FFFh
Note:	the default is disabled (0) for bits 4-0
SeeAlso: #P0183,#P0184

Bitfields for OPTi-82C493 Control Register 3:
Bit(s)	Description	(Table P0186)
 7	enable NCA# pin to low state (default is 1 = enabled)
 6-5	unused
 4	Video BIOS at C0000h - C8000h non-cacheable
	0 = cacheable
	1 = non-cacheable (default)
 3-0	Cacheable address range for local memory
	0000  0 - 64MB
	0001  0 - 4MB (default)
	0010  0 - 8MB
	0011  0 - 12MB
	0100  0 - 16MB
	0101  0 - 20MB
	0110  0 - 24MB
	0111  0 - 28MB
	1000  0 - 32MB
	1001  0 - 36MB
	1010  0 - 40MB
	1011  0 - 44MB
	1100  0 - 48MB
	1101  0 - 52MB
	1110  0 - 56MB
	1111  0 - 60MB
	Note:	If total memory is 1MB or 2MB the cacheable range is 0-1 MB or
		  0-2 MB and independent of the value of bits 3-0
SeeAlso: #P0179,#P0180

Bitfields for OPTi-82C493 Non-cacheable Block Register 1:
Bit(s)	Description	(Table P0187)
 7-5	Size of non-cachable memory block
	000  64K
	001  128K
	010  256K
	011  512K
	1xx  disabled (default)
 4-2	unused
 1-0	Address bits 25 and 24 of non-cachable memory block (default = 00)
Note:	this register is used together with configuration register 29h
	  (non-cacheable block 1) or register 2Bh (block 2) (see #P0188) to
	  define a non-cacheable block.	 The starting address must be a
	  multiple of the block size
SeeAlso: #P0178,#P0188

Bitfields for OPTi-82C493 Non-cacheable Block Register 2:
Bit(s)	Description	(Table P0188)
 7-0	Address bits 23-16 of non-cachable memory block (default = 0001xxxx)
Note:	the block address is forced to be a multiple of the block size by
	  ignoring the appropriate number of the least-significant bits
SeeAlso: #P0178,#P0187
----------P00220024--------------------------
PORT 0022-0024 - OPTi "Viper" (82C557) CHIPSET - SYSTEM CONTROL REGISTERS
Note:	every access to PORT 0024h must be preceded by a write to PORT 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"

0022  ?W  index for accesses to data port (see #P0189)
0023  RW  DMA clock select (see #P0087)
0024  RW  chip set data

(Table P0189)
Values for OPTi "Viper" (82C557) system control registers:
 00h	Byte Merge/Prefetch and Sony Cache Module Control register (see #P0190)
 00h	Compatible DRAM Configuration register 1 (see #P0191) (refer to note)
 01h	DRAM Control register 1 (see #P0192)
 02h	Cache Control register 1 (see #P0193)
 03h	Cache Control register 2 (see #P0194)
 04h	Shadow RAM Control register 1 (see #P0195)
 05h	Shadow RAM Control register 2 (see #P0197)
 06h	Shadow RAM Control register 3 (see #P0198)
 07h	Tag Test register (see #P0199)
 08h	CPU Cache Control register (see #P0200)
 09h	System Memory Function register (see #P0201)
 0Ah	DRAM Hole A Address Decode register 1 (see #P0202)
 0Bh	DRAM Hole B Address Decode register 2 (see #P0203)
 0Ch	Extended DMA register (see #P0204)
 0Dh	Clock Control register (see #P0205)
 0Eh	Cycle Control register 1 (see #P0206)
 0Fh	Cycle Control register 2 (see #P0207)
 10h	Miscellaneous Control register 1 (see #P0208)
 11h	Miscellaneous Control register 2 (see #P0209)
 12h	Refresh Control register (see #P0210)
 13h	Memory Decode Control register 1 (see #P0211)
 14h	Memory Decode Control register 2 (see #P0213)
 15h	PCI Cycle Control register 1 (see #P0214)
 16h	Dirty/Tag RAM Control register (see #P0215)
 17h	PCI Cycle Control register 2 (see #P0216)
 18h	Tristate Control register (see #P0217)
 19h	Memory Decode Control register 3 (see #P0218)
 1Ah-1Fh reserved
Note:	Byte Merge/Prefetch and Sony Cache Module Control register is accessed
	  through register 00h when bit 7 of register 13h is set, otherwise
	  Compatible DRAM Configuration register 1 is accessed as register 00h
	reserved registers 1Ah-1Fh must be written to 0
SeeAlso: #P0121,#P0211

Bitfields for OPTi "Viper" Byte Merge / Sony Cache Module Control register:
Bit(s)	Description	(Table P0190)
 7	enable pipelining of single CPU cycles to memory
 6	enable video memory byte/word read prefetch. Enables the prefetching
	  of bytes/words from PCI video memory to the CPU
 5	enable Sony SONIC-2WP support. If set, the ensure that the L2 cache
	  has been disabled (register 02h bits 3-2)
 4	enable byte/word merge support
 3	enable byte/word merging with CPU pipelining (NA# generation) support
 2-1	time-out counter for byte/word merge. Determines the maximum time
	  difference between two consecutive PCI bye/word writes to allow
	  merging
	00  4 CPU CLKs
	01  8 CPU CLKs
	10 12 CPU CLKs
	11 16 CPU CLKs
 0	enable internal hold requests to be blocked while performing byte merge
SeeAlso: #P0189

Bitfields for OPTi "Viper" Compatible DRAM Configuration register 1:
Bit(s)	Description	(Table P0191)
 7	enable pipelining of single CPU cycles to memory
 6	second bank SIMM selection. SIMMs need to be single sided
	0 single sided SIMM not installed in bank 0
	1 single sided SIMM installed in bank 0
 5	first bank SIMM selection. SIMMs need to be single sided
	0 single sided SIMM not installed in bank 0
	1 single sided SIMM installed in bank 0
 4-0	banks 0 thru 3 DRAM configuration
	(val)	Bank0	Bank1	Bank2	Bank3
	00000	256K	256KB	-	-
	00001	512K	512K	-	-
	00010	1M	1M	-	-
	00011	2M	2M	-	-
	00100	4M	4M	-	-
	00101	8M	8M	-	-
	00110	256K	256K	256K	256K
	00111	256K	256K	512K	512K
	01000	512K	512K	512K	512K
	01001	256K	256K	1M	1M
	01010	512K	512K	1M	1M
	01011	1M	1M	1M	1M
	01100	256K	256K	2M	2M
	01101	512K	512K	2M	2M
	01110	1M	1M	2M	2M
	01111	2M	2M	2M	2M
	10000	256K	256K	4M	4M
	10001	512K	512K	4M	4M
	10010	1M	1M	4M	4M
	10011	2M	2M	4M	4M
	10100	4M	4M	4M	4M
	10101	256K	256K	8M	8M
	10110	512K	512K	8M	8M
	10111	1M	1M	8M	8M
	11000	2M	2M	8M	8M
	11001	4M	4M	8M	8M
	11010	8M	8M	8M	8M
Note:	these settings maintain backward compatibility with the "Python"
	  (82C546/82C547) chipset, and they do not allow for much flexibility
SeeAlso: #P0189

Bitfields for OPTi "Viper" (82C557) DRAM Control register 1:
Bit(s)	Description	(Table P0192)
 7	row address hold after RAS# active in CLKs
	0 2 CLKs
	1 1 CLK
 6	RAS# active/inactive on entering master mode
	0 normal page mode when starting a master cycle, RAS# will remain
	1 RAS# inactive when starting a master cycle
 5-4	RAS pulse width used during refresh
	00 7 CLKs
	01 6 CLKs
	10 5 CLKs
	11 4 CLKs
 3	CAS pulse width during reads
	0 3 CLKs
	1 2 CLKs
 2	CAS pulse width during writes 
	0 3 CLKs
	1 2 CLKs
 1-0	RAS precharge time
	00 6 CLKs
	01 5 CLKs
	10 4 CLKs
	11 3 CLKs
SeeAlso: #P0189,#P0193,#P0219

Bitfields for OPTi "Viper" (82C557) Cache Control register 1:
Bit(s)	Description	(Table P0193)
 7-6	cache size selection; determines size of the L2 cache, along with
	  register 0Fh bit 0. When set, it works as a *16 multiplier
	00 (Viper)  64K (1M when register 0Fh bit 0 set)
	   (Vendetta) reserved
	01 (Viper) 128K (2M when register 0Fh bit 0 set)
	   (Vendetta) reserved
	10 256K (reserved when register 0Fh bit 0 set)
	11 512K (reserved when register 0Fh bit 0 set)
 5-4	cache write policy; determines the write policy for the L2 cache
	00 L2 cache write-through
	01 Adaptive Write-back Mode 1
	10 Adaptive Write-back Mode 2
	11 L2 cache write-back
 3-2	cache mode select; determines the operating mode of the L2 cache
	00 disable
	01 Test Mode 1, External Tag Write (Tag data write-through reg. 07h)
	10 Test Mode 2, External Tag Read (Tag data read from register 07h)
	11 enable L2 cache
 1	enable DRAM posted write
 0	CAS precharge time
	0 2 CLKs
	1 1 CLK
SeeAlso: #P0189,#P0199,#P0207,#P0194,#P0219

Bitfields for OPTi "Viper" (82C557) Cache Control register 2:
Bit(s)	Description	(Table P0194)
 7-6	L2 cache write burst mode timings
	00 X-4-4-4
	01 X-3-3-3
	10 X-2-2-2
	11 X-1-1-1
 5-4	L2 cache write lead-off cycle timings
	00 5-X-X-X
	01 4-X-X-X
	10 3-X-X-X
	11 2-X-X-X
 3-2	L2 cache read burst mode timings
	00 X-4-4-4
	01 X-3-3-3
	10 X-2-2-2
	11 X-1-1-1
 1-0	L2 cache read lead-off cycle timings
	00 5-X-X-X
	01 4-X-X-X
	10 3-X-X-X
	11 2-X-X-X
Note:	SRAM double bank implementation does not support lead-off timing
SeeAlso: #P0189,#P0193,#P0219

Bitfields for OPTi "Viper"/"Vendetta" Shadow RAM Control register 1:
Bit(s)	Description	(Table P0195)
 7-6	CC000-CFFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM (see #P0196)
 5-4	C8000-CBFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM (see #P0196)
 3	enable synchronous SRAM pipelined read cycle 1-1-1-1
 2	E0000-EFFFF range selection
	0 area will always be non-cacheable
	1 are will be treated like the F0000h BIOS area
 1-0	C0000-C7FFF read/write control; determines the R/W control for these
	  segments of the shadow RAM (see #P0196)
Note:	bit 3 will act only when register 11h bit 3 and register 03h bits 3-2
	  are all set
	when bit 2 is set, register 06h bits 3-0 should be set identically
SeeAlso: #P0189,#P0197,#P0219

(Table P0196)
Values for OPTi "Viper"/"Vendetta" Shadow RAM Control setting:
 00	read/write PCI bus
 01	read from DRAM/write to PCI
 10	read from PCI/write to DRAM
 11	read from/write to DRAM
SeeAlso: #P0195,#P0197,#P0198,#P0219

Bitfields for OPTi "Viper"/"Vendetta" Shadow RAM Control register 2:
Bit(s)	Description	(Table P0197)
 7-6	DC000-DFFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM (see #P0196)
 5-4	D8000-DBFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM (see #P0196)
 3-2	D4000-D7FFF read/write control; determines the R/W control for these
	  segments of the shadow RAM (see #P0196)
 1-0	D0000-D3FFF read/write control; determines the R/W control for these
	  segments of the shadow RAM (see #P0196)
SeeAlso: #P0189,#P0195,#P0198,#P0219

Bitfields for OPTi "Viper"/"Vendetta" Shadow RAM Control register 3:
Bit(s)	Description	(Table P0198)
 7	DRAM hole in system memory from 80000-9FFFF; gives the user the option
	  to have some other device in this address range instead of system
	  memory. When set, the SYSC will not start the system DRAM controller
	  for accesses to this particular address range
	0 no memory hole
	1 enable memory hole
 6	wait state addition for PCI master snooping
	0 do not add a wait state
	1 add a wait state for the cycle access to finish and then do snooping
 5	enable C0000-C7FFF cacheability in L1 and L2 cache memory
 4	enable F0000-FFFFF cacheability in L1 and L2 cache memory
 3-2	F0000-FFFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM (see #P0196)
 1-0	E0000-EFFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM (see #P0196)
Note:	L1 cacheability can be disabled thru register 08h bit 0
	If register 04h bit 2 is set, then F0000-FFFFF and E0000-EFFFF R/W
	control settings should have similar values
SeeAlso: #P0189,#P0197,#P0219

Bitfields for OPTi "Viper"/"Vendetta" Tag Test register:
Bit(s)	Description	(Table P0199)
 7-0	Tag Test register; when in cache Test Mode, data is read from/written
	  to this register
SeeAlso: #P0189,#P0193,#P0219

Bitfields for OPTi "Viper"/"Vendetta" CPU Cache Control register:
Bit(s)	Description	(Table P0200)
 7	L2 cache single/double bank select
	0 (Viper) two banks of L2 cache
	  (Vendetta) reserved
	1 single bank of L2 cache (non-interleaved)
 6	enable snoop filtering for bus masters
 5	CPU HITM# pin sample timing
	0 (Viper) delay one clock, therefore HITM# sampled on the third rising
	    edge of LCLK after EADS# has been asserted
	  (Vendetta) reserved
	1 do not delay, therefore HITM# sampled on the second rising edge
 4	enable parity checking
 3	Tag/Dirty RAM implementation
	0 (Viper) Tag and Dirty are on separate chips
	  (Vendetta) reserved
	1 Tag and Dirty are on the same chip
 2	enable CPU address pipelining
 1	enable L1 cache write-back and write-through control
	0 write-through only
	1 write-back enabled
 0	disable BIOS and Video BIOS areas cacheability in L1 cache
Notes:	If asynchronous SRAM, then cache memory banks (when two are present)
	  are interleaved, otherwise, they are not
	When register 04h bit 2 is set, bit 0 affects BIOS area
	  E0000-EFFFF; when clear, bit 0 affects area F0000-FFFFF
SeeAlso: #P0189,#P0201,#P0219

Bitfields for OPTi "Viper" (82C557) System Memory Function register:
Bit(s)	Description	(Table P0201)
 7-6	DRAM Hole B size
	(address specified by register 0Bh, and register 0Ch bits 3-2)
	00 512K
	01   1M
	10   2M
	11   4M
 5-4	DRAM Hole B control mode
	00 disable
	01 write-through for L1 and L2 cache
	10 non-cacheable for L1 and L2 cache
	11 enable hole in DRAM
 3-2	DRAM Hole A size (settings same as bits 7-6)
	(address specified by register 0Ah, and register 0Ch bits 1-0)
 1-0	DRAM Hole A control mode (settings same as bits 5-4)
SeeAlso: #P0189,#P0203,#P0204,#P0219

Bitfields for OPTi "Viper" (82C557) DRAM Hole A Address Decode register 1:
Bit(s)	Description	(Table P0202)
 7-0	DRAM Hole A address, bits 26-19
	(bits 1-0 of register 0Ch map onto bits 28-27 of HA lines)
SeeAlso: #P0189,#P0204,#P0203,#P0219

Bitfields for OPTi "Viper" (82C557) DRAM Hole B Address Decode register 2:
Bit(s)	Description	(Table P0203)
 7-0	DRAM Hole B address, bits 26-19
	(bits 3-2 of register 0Ch map onto bits 28-27 of HA lines)
SeeAlso: #P0189,#P0204,#P0202,#P0219

Bitfields for OPTi "Viper" (82C557) Extended DMA register:
Bit(s)	Description	(Table P0204)
 7	reserved (0)
 6	Fast BRDY# generation for DRAM write page hits
	0 BRDY# for DRAM writes generated on the fourth clock
	1 BRDY# for DRAM writes generated on the third clock
 5	(Viper) HACALE one-half a clock cycle earlier
	    0 HACALE normal timing
	    1 HACALE one-half a clock cycle early enabled
	(Vendetta) reserved
 4	(Viper) wider cache WE# pulse
	    0 cache WE# pulse width is normal (~15ns)
	    1 cache WE# pulse is wider (~17.5ns)
	(Vendetta) reserved
 3-2	DRAM Hole B starting address, bits 28-27 (see also #P0202)
 1-0	DRAM Hole A starting address, bits 28-27 (see also #P0203)
Note:	bits 26-19 of memory holes A and B are mapped from Indices 0Ah and 0Bh
SeeAlso: #P0189,#P0219

Bitfields for OPTi "Viper" (82C557) Clock Control register:
Bit(s)	Description	(Table P0205)
 7	(Viper) clock source for generation the syncronous SRAM timing
	    0 CPU clock is the source for the timing and control signals
	    1 ECLK is the source for the timing and control signals
	(Vendetta) reserved (1)
 6	(Viper) this bit is set if the skew between ECLK and CPU clock is too
	  large (read-only bit, set by the 82C557 chip)
	(Vendetta) reserved (read-only)
 5	(Viper) enable auto skew detect; when this bit is set, bit 4 will be
	  set automatically if the skew between CLK and ECLK is too large
	(Vendetta) BRDY# PCI-to-ISA bridge request remove BOFF# disable
 4	(Viper) ECLK - CLK skew, activated when synchronou SRAMs are being used
	    0 skew between CLK and ECLK is not too large
	    1 skew is too large
	(Vendetta) 
	    0 preemption when CPU needs memory
	    1 reserved
 3	enable A0000-BFFFF as system memory
 2	wait state addition for PCI master doing address toggling as a 486
	0 linear burst mode style address toggling - no wait state addition
	1 i486 burst style address toggling - one wait state needs to be added
 1	(Viper) PCI cycle claimed by the 82C557 during PCI pre-snoop cycle
	    0 82C557 does not claim the PCI cycle after it asserts STOP#
	    1 82C557 claims the PCI cycle after it asserts STOP#
	(Vendetta) reserved
 0	slow CPU clock; should be set if the CPU clock frequency has been
	  reduced
	    0 CPU clock frequency is normal
	    1 CPU clock has been slowed down
	(Vendetta) reserved
SeeAlso: #P0189,#P0219

Bitfields for OPTi "Viper" (82C557) Cycle Control register 1:
Bit(s)	Description	(Table P0206)
 7-6	(Viper) PCI master read burst wait state control
	    00 4 cycles
	    01 3 cycles
	    10 2 cycles
	    11 reserved
	(Vendetta) reserved
 5-4	(Viper) PCI master write burst wait state control (same settings as
	  bits 7-6)
	(Vendetta) reserved
 3	master cycle parity enable; this bit becomes applicable when bit 4 of
	  register 08h is set
	0 enable parity check during master cycles
	1 disable parity check during master cycles
 2	(Viper) HACALE timing control
	    0 HACALE high during HITM# before CPU ADS#
	    1 HACALE low and CA4 always enabled during HITM cycle
	(Vendetta) fast NA# generation enable
 1	enable write protection for L1 BIOS
 0	PCI line comparator; this bit is only valid when bit 6 of register 08h
	  is set
	0 use line comparator in PCI master
	1 generate inquire cycle for every new FRAME#
SeeAlso: #P0189,#P0219

Bitfields for OPTi "Viper" (82C557) Cycle Control register 2:
Bit(s)	Description	(Table P0207)
 7	enable PCI pre-snooping feature
 6	(Viper) AT master wait state control
	    0 do not add any wait states for AT master cycles
	    1 add wait wait states for AT master cycles
	(Vendetta) ISA master access wait states enable (use if PCICLK <33MHz)
 5	(Viper) wait state addition for synchronous SRAM even byte access
	    0 do not add a wait state for a synchronous SRAM even byte access
	    1 add one wait state for a synchronous SRAM even byte access
	(Vendetta) L2 write-through mode CPU-to-DRAM deep buffer enable
 4	PCI wait state addition for synchronous SRAM L2 cache implementation
	0 master does not wait for end of current cycle + CPU-PCI clock to
	  become synchronous
	1 master waits for end of current cycle + wait for CPU-PCI clock to
	  become synchronous
 3	(Viper) reserved
	(Vendetta) L2 single cycle write hit when line already dirty
	    0 = 5 CLKs
	    1 = 3 CLKs
 2	(Viper) ADSC# generation for synchronous SRAM read cycle
	    0 generate ADSC# immediately after CPU ADS# goes active
	    1 generate ADSC# one clock after CPU ADS# goes active
	(Vendetta) CPU to L2 cache hit cycle chipset ADSC# generation disable
 1	(Viper) reserved
	(Vendetta) two-PCI master fix
	    0 revision 2.0
 0	L2 cache size selector; works along with bits 1-0 of register 02h
	0 below 1M
	1 1M and above (Viper only)
SeeAlso: #P0189,#P0193,#P0219

Bitfields for OPTi "Viper" (82C557) Miscellaneous Control register 1:
Bit(s)	Description	(Table P0208)
 7	(Viper) early decode of PCI/VL/AT cycle
	(Vendetta) early decode of PCI/ISA cycle
	0 CPU to <bus> slave cycle triggered after second T2
	1 CPU to <bus> slave cycle triggered after first T2
 6	(Viper) cache modified write cycle timing
	    0 use the old address changing method, as in the 82C546/82C547
	    1 two bank cache, CA4 delayed one-half a clock for write cycles
	(Vendetta) reserved
 5	pipelined read cycle timing; determines the lead-off cycle
	0 3-X-X-X read followed by a 3-X-X-X piped read cycle
	1 3-X-X-X read followed by a 2-X-X-X piped read cycle
 4	(Viper) enable write hit pipelined
	    0 do not enable 2-X-X-X pipelined write hit cycles
	    1 enable 2-X-X-X pipelined write hit cycles
	(Vendetta) reserved
 3	(Viper) write pulse timing control for cache write hit cycles
	    0 do not change the write pulse timing during X-2-2-2 write hit
	      cycles
	    1 move the write pulse one-half a clock later in X-2-2-2 write hit
	      cycles
	(Vendetta) reserved
 2	(Viper) write pulse timing control for cache write hit cycles
	    0 do not change the write pulse timing during 3-X-X-X write hit
	      cycles
	    1 move the write pulse one-half a clock later in 3-X-X-X write hit
	      cycles
	(Vendetta) reserved
 1	(Viper) external 74F126 select
	    0 an external 74F126 is installed for CA3 and CA4
	    1 an external 74F126 is not installed for CA3 and CA4
	(Vendetta) reserved (1)
 0	LCLK select control; when this bit is set, the timing constraints
	  between the LCLK and the CPUCLK inputs to the SYSC need to be met.
	  This constraints are: LCLK <= 1/2 CPUCLK period before CPUCLK, and
	  LCLK <= 0.5ns after CPUCLK
	0 LCLK is asynchronous to the CPUCLK
	1 LCLK is synchronous to the CPUCLK; LCLK = CPUCLK/2
Note:	bit 1 should always be set to 1
SeeAlso: #P0189,#P0219

Bitfields for OPTi "Viper" (82C557) Miscellaneous Control register 2:
Bit(s)	Description	(Table P0209)
 7-6	reserved; must be set to 0
 5	cache inactive during Idle state control
	0 SRAM always active
	1 SRAM inactive during Idle state (Viper only)
 4	next address (NA#) mode control
	0 normal NA# timing used with asynchronous SRAMs
	1 new NA# timing for synchronous SRAMs; used only when CPU operating
	  at 50MHz
 3	SRAM type
	0 asynchronous SRAM (Viper only)
	1 synchronous SRAM
 2	(Viper) enable page miss posted write
	(Vendetta) reserved
 1	(Viper) ISA/DMA IOCHRDY control
	    0 old mode, no IOCHRDY during line hit
	    1 drive IOCHRDY low until cycle is finished
	(Vendetta) reserved
 0	(Viper) delay start
	    0 old mode, do not delay internal master cycle after an inquire
	      cycle
	    1 delay internal master cycles by one LCLK after an inquire cycle
	(Vendetta) reserved
SeeAlso: #P0189,#P0219

Bitfields for OPTi "Viper" (82C557) Refresh Control register:
Bit(s)	Description	(Table P0210)
 7	REFRESH#/32KHz source selection
	0 REFRESH# source is REFRESH# pulse from the 82C558 or the ISA master
	1 REFRESH# pulse source is a 32KHz clock
 6	reserved; must be written to 0
 5-4	suspend mode refresh
	00 from CLK state machine
	01 slef refresh based on 32KHz only
	10 normal refresh based on 32KHz only
	11 undefined
 3-2	slow refresh
	00 refresh on every REFRESH#/32KHz falling edge
	01 refresh on alternate REFRESH#/32KHz falling edge
	10 refresh on one in four REFRESH#/32KHz falling edge
	1 refresh on every REFRESH#/32KHz toggle
 1	enable bits 23-17 of LA from Refresh Page register (8Fh) during refresh
 0	enable output of bits 7-4 of DBC MP during master write
	0 disable the DBC from generation the MP[7:4] lines during PCI master
	  writes; there must be a pull-up on MP0
	1 enable the DBC to generate the MP[7:4] lines during PIC master
	  writes; there must be a pull-down on MP0
SeeAlso: #P0189,#P0211

Bitfields for OPTi "Viper" (82C557) Memory Decode Control register 1:
Bit(s)	Description	(Table P0211)
 7	(Viper) memory decode select
	0 Byte Merge/Prefetch and Sony Cache Module Control register is
	  available in register 00h; compatible to 82C547 DRAM configurations
	1 Compatible DRAM Configuration register is available in register 00h;
	  full decode option; this gives the user maximum flexibility in
	  choosing different DRAM configurations
	(Vendetta) reserved (1)
 6-4	full decode for logical bank 1 (RAS#1), if bit 7 set. This settings
	  apply to 36-pin banks only (see #P0212)
 3	enable SMRAM
 2-0	full decode for logical bank 0 (RAS#0), if bit 7 set. This settings
	  apply to 36-pin banks only (see #P0212)
SeeAlso: #P0189,#P0190,#P0191,#P0219

(Table P0212)
Values for OPTi "Viper" (82C557) Memory Bank Decode Control registers:
 000	  0K
 001	256K
 010	512K
 011	  1M
 100	  2M
 101	  4M
 110	  8M
 111	 16M
SeeAlso: #P0211,#P0213,#P0216

Bitfields for OPTi "Viper" (82C557) Memory Decode Control register 2:
Bit(s)	Description	(Table P0213)
 7	(Viper) reserved; must be written to 0
	(Vendetta) reserved (1)
 6-4	full decode for logical bank 3 (RAS#3), if register 13h bit 7 is set
	  (see #P0212)
 3	SMRAM control
	0 disable SMRAM (enable SMRAM for both Code and Data if SMIACT# is
	  active and register 13h bit 3 is set)
	1 enable SMRAM (enable SMRAM for Code only if SMIACT# is active and
	  register 13h bit 3 is set)
 2-0	full decode for logical bank 2 (RAS#2), if register 13h bit 7 is set
	  (see #P0212)
SeeAlso: #P0189,#P0219

Bitfields for OPTi "Viper" (82C557) PCI Cycle Control register 1:
Bit(s)	Description	(Table P0214)
 7-6	CPU master to PCI memory slave, write IRDY# control
	00 3 LCLKs after end of address phase
	01 2 LCLKs after end of address phase
	10 1 LCLK after end of address phase
	11 0 LCLK after end of address phase
 5-4	CPU master to PCI slave write posting, bursting control
	00 PCI slave write, no posting, no bursting
	01 PCI slave write, posting enabled, no bursting
	10 PCI slave write, posting enabled, conservative bursting
	11 PCI slave write, posting enabled, aggressive bursting
 3-2	master retry timer
	00 retries unmasked after 10 PCICLKs
	01 retries unmasked after 18 PCICLKs
	10 retries unmasked after 34 PCICLKs
	11 retries unmasked after 66 PCICLKs
 1	reserved; must be written to 0
 0	PCI cycle, FRAME# timing control for pipelined cycles
	0 PCI cycle FRAME# assertion is done in the conservative mode style
	1 PCI cycle FRAME# assertion is done in the aggressive mode style
SeeAlso: #P0189,#P0216,#P0219

Bitfields for OPTi "Viper"/"Vendetta" Dirty/Tag RAM Control register:
Bit(s)	Description	(Table P0215)
 7	(Viper) Dirty pin selection; reflects the kind of SRAM chosen to
	  implement the Dirty RAM; it also determines the functionality of the
	  DIRTYI pin of the 82C557
	    0 DIRTYI pin is input-only
	    1 DIRTYI pin is bidirectional
	(Vendetta) reserved (1)
 6	reserved; must be written to 0
 5	Tag RAM size
	0 = 8-bit Tag (Viper only)
	1 = 7-bit Tag
 4	write hit cycle lead-off time when combining Dirty/Tag RAM
	0 single write hit lead-off cycle = 5 cycles
	1 single write hit lead-off cycle = 4 cycles
 3	pre-snoop control
	0 pre-snoop for starting address 0 only
	1 pre-snoop for all addresses except those on the line boundary
 2	(Viper) reserved; must be written to 0
	(Vendetta) synchronization between LCLK and CLK
	    0 LCLK is asynchronous to CLK
	    1 LCLK is synchronous to CLK
 1	(Viper) CPU to VL read access, DBC DLE# bits 1-0 timing
	    0 LCLK high
	    1 LCLK low
	(Vendetta) reserved
 0	(Viper) HDOE# timing control
	    0 HDOE# is negated normally
	    1 HDOE# is negated one clock before the cycle finishes
	(Vendetta) reserved
Note:	(Vendetta) bit 4 should be set same as register 22h bit 0
SeeAlso: #P0189,#P0219

Bitfields for OPTi "Viper"/"Vendetta" PCI Cycle Control register 2:
Bit(s)	Description	(Table P0216)
 7	(Vipder) NA# assertion control for PCI slave accesses when synchronous
	  PCI clock is used
	    0 no pipelining for accesses to PCI slave
	    1 pipelining enabled for accesses to PCI slave for both synchronous
	      and asynchronous PCI solutions; if set, overrides bit 6
	(Vendetta) MD drive strength
	    0 =	 8 mA
	    1 = 12 mA
 6	NA# assertion control for PCI slave accesses when asynchronous PCI
	  clock is used
	0 no pipelining for accesses to PCI slave
	1 pipelining enabled for accesses to PCI slave for an asynchronous PCI
	  implementation; this bit is overridden if bit 7 is set
 5	(Viper) enable support for Intel standard BSRAM
	    0 no support for Intel standard BSRAM
	    1 support for Intel standard BSRAM; should be set only if using two
	      banks of synchronous SRAM
	(Vendetta) reserved
 4	(Viper only) enable fast BRDY# generation for PCI cycles
 3	(Viper only) enable fast FRAME# generation for PCI cycles	    
 2	(Viper only) byte merging/piping control
	0 no pipelining when byte merging is on
	1 pipelining enabled along with byte merging
 1	pipelined synchronous SRAM support; this bit is applicable only if
	  register 11h bit 3 is set
	0 standard synchronous SRAM installed (Viper only)
	1 pipelined synchronous SRAM installed
 0	Cyrix linear burst mode support
	0 normal Intel standard burst mode
	1 support for Cyrix linear burst mode
SeeAlso: #P0189,#P0214,#P0219

Bitfields for OPTi "Viper"/"Vendetta" Tristate Control register:
Bit(s)	Description	(Table P0217)
  7	(Viper) reserved; must be written to 0
	(Vendetta) ISA retry (1)
 6	(Viper) reserved; must be written to 0
	(Vendetta) RAS line drive strength
	    0 = 16 mA
	    1 =	 4 mA
 5	(Viper) voltage selection for the CAS# lines 7-0
	    0 CAS# lines 7-0 are driven out at 5.0V logic level
	    1 CAS# lines 7-0 are driven out at 3.3V logic level
	(Vendetta) CAS1# and CAS5# drive strength
	    0 =	 8 mA
	    1 = 16 mA
 4	(Viper) programmable current drive for the MA[X], RAS[X]# and the DWE#
	  lines
	(Vendetta) memory address lines and write enable line drive strength
	0 driving capability on these lines is 4mA
	1 driving capability on these lines is 16mA
 3	enable tristate CPU interface during Suspend and during CPU power-off
 2	enable tristate PCI interface during Suspend and during PCI power-off
 1	enable tristate cache interface during Suspend and cache power-off
 0	enable the pull-up/pull-down resistors during Suspend and power-off
SeeAlso: #P0189,#P0219

Bitfields for OPTi "Viper" (82C557) Memory Decode Control register 3:
Bit(s)	Description	(Table P0218)
 7	DIRTYWE# RAS5# selection; if six DRAM banks are chosen, then the line
	  will become RAS#5, if this bit is set
	0 DIRTYWE# functions as DIRTYWE# (six banks of DRAM are not chosen)
	1 DIRTYWE# functions as RAS#5 (six banks of DRAM are chosen)
	(Vendetta must be set to RAS5# function (1))
 6-4	(Viper) full decode for logical bank 5 (RAS#5) if register 13h bit 7
	  and register 19h bit 7 are set (see #P0212)
	(Vendetta) full decode for logical bank 5 (RAS5#) if register 13h
	  bit 7 set (see #P0212)
 3	MA11/RAS#4 selection; if five DRAM banks are chosen, then the MA11 line
	  will become RAS#4, if this bit is set
	0 MA11 functions as MA11 (the fifth bank of DRAM is not chosen)
	1 MA11 functions as RAS#4 (five banks of DRAM have been chosen)
	(Vendetta must be set to RAS4# function (1))
 2-0	(Viper) full decode for logical bank 4 (RAS#4) if register 13h bit 7
	  and register 19h bit 3 are set (see #P0212)
	(Vendetta) full decode for logical bank 4 (RAS4#) if register 13h
	  bit 7 set (see #P0212)
Notes:	(Viper) if bit 7 is set, then a combined Dirty/Tag SRAM solution must
	   be implemented or else it will not have a Dirty RAM
	(Viper) if bit 3 is set, then none of the DRAM banks will support the
	  8M*36 or 16M*36 options
SeeAlso: #P0189,#P0219
----------P00220024--------------------------
PORT 0022-0024 - OPTi "Vendetta" (82C750) CHIPSET - SYSTEM CONTROL REGISTERS
Note:	every access to PORT 0024h must be preceded by a write to PORT 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"

0022  ?W  index for accesses to data port (see #P0219)
0023  RW  DMA clock select (see #P0087)
0024  RW  chip set data

(Table P0219)
Values for OPTi "Vendetta" (82C750) system control registers:
 00h	DRAM control register 1 (see #P0220)
 01h	DRAM control register 2 (see #P0192)
 02h	cache control register 1 (see #P0193)
 03h	cache control 2 (see #P0194)
 04h	shadow RAM control register 1 (see #P0195)
 05h	shadow RAM control register 2 (see #P0197)
 06h	shadow RAM control register 3 (see #P0198)
 07h	tag test register (see #P0199)
 08h	CPU cache control register (see #P0200)
 09h	system memory function register (see #P0201)
 0Ah	DRAM hole A address decode register 1 (see #P0202)
 0Bh	DRAM hole B address decode register 2 (see #P0203)
 0Ch	DRAM hole higher address (see #P0204)
 0Dh	clock control register (see #P0205)
 0Eh	PCI master burst control register 1 (see #P0206)
 0Fh	PCI master burst control register 2 (see #P0207)
 10h	miscellaneous control register 1 (see #P0208)
 11h	miscellaneous control register 2 (see #P0209)
 12h	miscellaneous control register 3 (see #P0221)
 13h	memory decode control register 1 (see #P0211)
 14h	memory decode control register 2 (see #P0213)
 15h	PCI cycle control register 1 (see #P0214)
 16h	dirty/tag RAM control register (see #P0215)
 17h	PCI cycle control register 2 (see #P0216)
 18h	tristate control register (see #P0217)
 19h	memory decode control register 3 (see #P0218)
 1Ah	memory shadow control register 1 (see #P0222)
 1Bh	memory shadow control register 2 (see #P0223)
 1Ch	EDO SDRAM control register (see #P0224)
 1Dh	miscellaneous control register 4 (see #P0225)
 1Eh	BOFF# control register (see #P0226)
 1Fh	EDO timing control register (see #P0227)
 20h	DRAM burst control register (see #P0228)
 21h	PCI concurrence control register (see #P0229)
 22h	inquire cycle control register (see #P0230)
 23h	pre-snoop control register (see #P0231)
 24h	asymmetric DRAM configuration register (see #P0232)
 25h	GUI memory location register (see #P0233)
 26h	UMA control register (see #P0234)
 27h	self refresh timing register (see #P0235)
 28h	SDRAM burst and latency control register (see #P0236)
 29h	SDRAM selection register (see #P0237)
 2Ah	PCI-to-DRAM deep buffer size register (see #P0238)
 2Bh	EDO/SDRAM time-out register (see #P0239)
 2Ch	CPU-to-DRAM buffer control register (see #P0240)
 2Dh	bank-wise EDO timing selection register (see #P0241)
 2Eh	PCI master - GUI retry control register (see #P0242)
 2Fh	CAS address setup time control register (see #P0243)
 30h-7Fh reserved
 80h	PIC 1 ICW1 read-back register (read-only)
 81h	PIC 1 ICW2 read-back register (read-only)
 82h	PIC 1 ICW3 read-back register (read-only)
 83h	PIC 1 ICW4 read-back register (read-only)
 84h	reserved
 85h	PIC 1 OCW2 read-back register (read-only)
 86h	PIC 1 OCW3 read-back register (read-only)
 87h	reserved
 88h	PIC 2 ICW1 read-back register (read-only)
 89h	PIC 2 ICW2 read-back register (read-only)
 8Ah	PIC 2 ICW3 read-back register (read-only)
 8Bh	PIC 2 ICW4 read-back register (read-only)
 8Ch	reserved
 8Dh	PIC 2 OCW2 read-back register (read-only)
 8Eh	PIC 2 OCW3 read-back register (read-only)
 8Fh	refresh address register (see #P0244)
 90h	CTSC0LB (PIT counter 0 low byte) read-back register (read-only)
 91h	CTSC0HB (PIT counter 0 high byte) read-back register (read-only)
 92h	CTSC1LB (PIT counter 1 low byte) read-back register (read-only)
 93h	CTSC1HB (PIT counter 1 high byte) read-back register (read-only)
 94h	CTSC2LB (PIT counter 2 low byte) read-back register (read-only)
 95h	CTSC2HB (PIT counter 2 high byte) read-back register (read-only)
 96h	byte pointer register (read-only)
	(byte 2 pointer value)
 97h-ACh reserved
 ADh	general purpose chip select control register (see #P0270)
 AEh-DFh reserved
 E0h	GREEN mode control/enable status (see #P0245)
 E1h	EPMI control/GREEN event timer (see #P0246)
 E2h	GREEN event timer initial count register (see #P0247)
 E3h	IRQ event enable register 1 (see #P0248)
 E4h	IRQ event enable register 2 (see #P0249)
 E5h	DREQ event enable register (see #P0250)
 E6h	device cycle monitor enable register (see #P0251)
 E7h	wake-up source/programmable IO/memory address mask register (see #P0252)
 E8h	programmable I/O/MEM address range register (see #P0253)
 E9h	programmable I/O/MEM address range register (see #P0254)
 EAh	enter GREEN state port register (see #P0255)
 EBh	return to NORMAL state configuration port register (see #P0256)
 ECh	shadow register for external power control latch register (see #P0257)
 EDh	device cycle detection enable/status register (see #P0258)
 EEh	STPCLK# modulation register (see #P0259)
 EFh	miscellaneous register (see #P0260)
 F0h	device timer CLK select/enable status register (see #P0261)
 F1h	device timer 0 initial count register
 F2h	device timer 1 initial count register
 F3h	device timer IO/MEM select, mask bits register (see #P0262)
 F4h	device 0 IO/MEM address register (see #P0263)
 F5h	device 0 IO/MEM address register (see #P0264)
 F6h	device 1 IO/MEM address register (see #P0265)
 F7h	device 1 IO/MEM address register (see #P0266)
 FAh-FBh reserved
 FCh	power management control register 1 (see #P0267)
 FDh	power management control register 2 (see #P0268)
 FEh	power management control register 3 (see #P0269)
 FFh	general purpose chip select control register (see #P0270)

Bitfields for OPTi "Vendetta" DRAM control register 1:
Bit(s)	Description	(Table P0220)
 7	reserved
 6	SDRAM pipeline fix (1)
 5-0	reserved
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" miscellaneous control register 3:
Bit(s)	Description	(Table P0221)
 7	buffered DMA register 8Fh latch to bits 23-16 of SA lines disable
 6-0	reserved
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" memory shadow control register 1:
Bit(s)	Description	(Table P0222)
 7	reserved
 6-5	CPU bus utilization time guarantee
	00 = no guarantee
	01 = 1 of every 15 microseconds
	10 = 2 of every 15 microseconds
	11 = 4 of every 15 microseconds
 4	C8000-DFFFF shadow granularity
	0 = 16 KB
	1 =  8 KB
 3-2	CE000-CFFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM; applicable if bit 4 is set (see #P0196)
 1-0	CA000-CBFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM; applicable if bit 4 is set (see #P0196)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" memory shadow control register 2:
Bit(s)	Description	(Table P0223)
 7-6	DE000-DFFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM; applicable if register 1Ah bit 4 is set
	  (see #P0196)
 5-4	DA000-DBFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM; applicable if register 1Ah bit 4 is set
	  (see #P0196)
 3-2	D6000-D7FFF read/write control; determines the R/W control for these
	  segments of the shadow RAM; applicable if register 1Ah bit 4 is set
	  (see #P0196)
 1-0	D2000-D3FFF read/write control; determines the R/W control for these
	  segments of the shadow RAM; applicable if register 1Ah bit 4 is set
	  (see #P0196)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" EDO SDRAM control register:
Bit(s)	Description	(Table P0224)
 7-2	bank 5-0 EDO SDRAM usage
	0 = standard page mode DRAM
	1 = EDO SDRAM
 1	reserved
 0	DRAM access CAS pulse width
	0 = determined by register 01h bit 3
	1 = 1 CPUCLK
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" miscellaneous control register 4:
Bit(s)	Description	(Table P0225)
 7-6	reserved
 5	DWE# timing
	0 = normal
	1 = removed 1 CLK earlier
 4	DRAM read leadoff cycle
	0 = normal
	1 = 1 CLK reduced
 3	system memory DMA access disable
 2	reserved
 1	SMM mode B0000-BFFFF access
	0 = main memory
	1 = PCI bus
 0	SMM mode A0000-AFFFF access
	0 = main memory
	1 = PCI bus
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" BOFF# control register:
Bit(s)	Description	(Table P0226)
 7	PCI master read cycle
	0 = wait IRDY# assert before TRDY# assert
	1 = generate TRDY# when checking IRDY# status
 6	reserved (1)
 5	reserved
 4	A0000-BFFFF PCI retry cycle BOFF# generation
	0 = not generated if bit 3 set
	1 = generated if bit 3 set
 3	deadlock situation avert
	0 = no avert
	1 = assert BOFF#
 2	reserved (1)
 1-0	reserved
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" EDO timing control register:
Bit(s)	Description	(Table P0227)
 7	0 = normal
	1 = EDO detection conflict generation (bit 6 set)
 6	0 = normal fast page mode
	1 = detect EDO
 5	NA# generation
	0 = aggresive
	1 = normal
 4	DRAM read cycle lead-off 1 CLK reduce enable
 3-2	reserved
 1	hidden refresh block AHOLD disable
 0	D0000-DFFFF cacheable in L1 and L2
	0 = not cacheable
	1 = cacheable; area has to be read/writable and shadowed
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" DRAM burst control register:
Bit(s)	Description	(Table P0228)
 7	reserved (1)
 6	PCI master access HITM# cycle DRAM write post enable
 5	reserved
 4	PCI master parity enable
 3-2	PCI master cycle DRAM write burst cycle
	00 = reserved
	01 = X-3-3-3
	10 = X-2-2-2
	11 = X-1-1-1
 1-0	PCI master cycle DRAM read burst cycle
	00 = reserved
	01 = X-3-3-3
	10 = X-2-2-2
	11 = X-1-1-1
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" PCI concurrence control register:
Bit(s)	Description	(Table P0229)
 7	concurrence timer
	0 = conservative
	1 = aggressive
 6-5	PCI master and CPU/L2 concurrence
	00 = no concurrence
	x1 = PCI write invalid cycles
	1x = PCI read multiple and read line cycles
 4-3	reserved
 2	0 = if tag = 11011111b => invalid combination
	1 = if cache = 256K, tag = 00001100b => invalid combination (CF0000h).
	    if cache > 256K, tag = 10111111b => invalid combination
	  (valid only when bit 1 set)
 1-0	reserved (1)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" inquire cycle control register:
Bit(s)	Description	(Table P0230)
 7	reserved
 6-5	new mode pre-snoop function
	00 = disable
	11 = enable
 4	HRQ synchronous to LCLK enable (must be 1 for ISA retry)
 3-1	reserved
 0	write hit cycle lead-off time when combining Dirty/Tag RAM
	0 = single write hit lead-off cycle = 5 cycles
	1 = single write hit lead-off cycle = 4 cycles
Note:	bit 0 should be set same as register 16h bit 4
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" pre-snoop control register:
Bit(s)	Description	(Table P0231)
 7	reserved
 6	0 = bank 0 selected as first bank
	1 = bank 0 selected as last bank
 5	PCI X-1-1-1 write invalidate pre-snoop enable
 4	PCI X-1-1-1 read multiple and read line pre-snoop enable
 3	fast NA cache hit half clock shift enable
 2-1	reserved (1)
 0	reserved
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" asymmetric DRAM configuration register:
Bit(s)	Description	(Table P0232)
 7-6	logical bank 3 DRAM type
	00 = symmetric
	01 = asymmetric x8
	10 = asymmetric x9
	11 = asymmetric x10
 5-4	logical bank 2 DRAM type
 3-2	logical bank 1 DRAM type
 1-0	logical bank 0 DRAM type
Note:	banks 4 and 5 do not support asymmetric DRAM
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" GUI memory location register:
Bit(s)	Description	(Table P0233)
 7-3	GUI memory location bits 31-27
 2	UMA size
	0 = decided by register 26h bits 5-4
	1 = 0.5MB (register 26h bits 5-4 = 00)
 1-0	reserved
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" UMA control register:
Bit(s)	Description	(Table P0234)
 7	ISA master to DRAM cycle CAS width
	0 = controlled by ISA read/write command pulse width
	1 = 2 LCLKs
 6	ISA SA address latch
	0 = pass-through
	1 = on only for retry
 5-4	GUI memory size
	00 = 1MB (0.5MB if register 25h bit 2 set)
	01 = 2MB
	10 = 3MB
	11 = 4MB
 3	66MHz 5-2-2-2 EDO DRAM read timing enable
 2-1	GUI priority
	00 = normal
	01 = wait 2 CLKs for low priority GUI request
	11 = high
 0	UMA support enable
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" self refresh timing register:
Bit(s)	Description	(Table P0235)
 7-6	reserved
 5	PCI master write line invalid cycle HITM# or L2 dirty no stop enable
 4	CPU single write hit not dirty cycle second T2 AHOLD generate enable
 3	fast NA# with L2 cache enable
 2-0	self refresh
	000 = disable, use external refresh pin
	001-011 = reserved
	100 = 66MHz external CPU clock
	101 = 60MHz external CPU clock
	110 = 50MHz external CPU clock
	111 = 40MHz external CPU clock
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" SDRAM burst and latency control register:
Bit(s)	Description	(Table P0236)
 7	CS# delay enable
 6-4	SDRAM CAS# latency
	000 = reserved
	001 = 1
	010 = 2
	011 = 3
	100-111 = reserved
 3	0 = sequential write-through
	1 = interleaved write-through
 2-0	SDRAM burst length
	000 = 1
	001 = reserved
	010 = 4
	011-111 = reserved
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" SDRAM selection register:
Bit(s)	Description	(Table P0237)
 7	pipeline read
	0 = 7-1-1-1-5-1-1-1-1
	1 = 7-1-1-1-2-1-1-1-1
 6	reserved
 5	timing
	     tRP     tRAS    tMRS
	00 = 2 CLKs  4 CLKs  3 CLKs
	01 = 4 CLKs  5 CLKs  3 CLKs
	10 = 3 CLKs  6 CLKs  2 CLKs
	11 = rsvd    7 CLKs  rsvd
	tRP: command activate precharge time
	tRAS: command precharge RAS active time
	tMRS: mode register set cycle time
 4-0	bank 4-0 SDRAM enable
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" PCI-to-DRAM deep buffer size register:
Bit(s)	Description	(Table P0238)
 7	reserved
 6-5	PCI master read cycle GUI request time-out
	00 = FP mode, grant DRAM bus when possible
	01 = SDRAM or EDO time-out
	10-11 = FP mode, SDRAM, or EDO time-out
 4	PCI-to-DRAM deep buffer PCI TRDY# wait state
	0 = 0 wait state (X-1-1-1)
	1 = 1 wait state (X-2-2-2)
 3	PCI-to-DRAM deep buffer write burst enable
 2	PCI-to-DRAM deep buffer read burst enable
 1-0	PCI-to-DRAM deep buffer size
	00 = 16 dwords
	01 = 24 dwords
	10-11 = reserved
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" EDO/SDRAM time-out register:
Bit(s)	Description	(Table P0239)
 7-4	SDRAM time-out count on GUI request - 9 CLKs
	  (delay count +9 CLKs)
 3-0	EDO time-out count on GUI request
	  (delay count +6 CLKs)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" CPU-to-DRAM buffer control register:
Bit(s)	Description	(Table P0240)
 7	concurrent CPU-to-PCI read and CPU-to-DRAM write enable
 6	reserved
 5	cache miss dirty cycle CPU-to-DRAM buffer control
	1 = supply data to CPU before previous data write-back
	  (CPU-to-DRAM buffer must be enabled)
 4-3	reserved
 2	DRAM read cycle BOFF# assert enable
 1	CPU DRAM bus ownership data merge enable
 0	write data while buffer flush enable
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" bank-wise EDO timing selection register:
Bit(s)	Description	(Table P0241)
 7	reserved
 6	predictive reading enable
 5-0	bank 5-0 EDO DRAM read cycle
	0 = default
	1 = 5-X-X-X (66MHz)/4-X-X-X (50MHz) enable
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" PCI master - GUI retry control register:
Bit(s)	Description	(Table P0242)
 7-6	reserved
 5	USB module enable
 4	reserved
 3	CPU-to-PCI FIFO control module enable
 2	reserved
 1	PCI master HITM# cycle, GUI high priority request before first BRDY#
	0 = retry all
	1 = retry only PCI master read
 0	GUI cycle PCI master request retry
	0 = retry all
	1 = retry reads, accept writes
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" CAS address setup time control register:
Bit(s)	Description	(Table P0243)
 7	page miss cycle CAS column address delay
	0 = default
	1 = 1 CLK
 6	burst mode and length
 5	reserved
 4-3	burst mode and length
	bits 6 and 4-3:
	000 = mode 0, RWM 5
	001 = mode 1, RWM 5, BLEN 2
	010 = BLEN 3
	011 = BLEN 4
	100 = mode 0, RWM 4
	101 = mode 2, RWM 4, BLEN 1
	110 = BLEN 2
	111 = BLEN 3
	RWM: refresh request water mark
	BLEN: minimum number of burst refresh cycles
	mode 0: generate refresh request on RWM reach/cross; if high priority
		GUI request pending, preempt refresh burst at end of current
		cycle; if CPU/PCI request pending, preempt refresh burst when
		count<RWM; else refresh until count=0, then refresh ahead up
		to 3/7
	mode 1: generate refresh request on RWM reach/cross; if high priority
		GUI request pending, preempt refresh burst at end of current
		cycle; if CPU/PCI request pending, preempt refresh burst when
		count<RWM and performed refresh cycles>=BLEN; else refresh
		until count=0, then refresh ahead up to 3/7
	mode 2: generate refresh request on RWM reach/cross; if high priority
		GUI request pending, preempt refresh burst at end of current
		cycle; if CPU request pending, preempt refresh burst when
		performed refresh cycles>=BLEN; if PCI request pending,
		preempt refresh burst when count<RWM and performed refresh
		cycles>=BLEN; else refresh until count=0, then refresh ahead
		up to 3/7
 2-0	refresh ahead
	000 = burst refresh disable
	001 = starting bank 0, no refresh ahead
	010 = starting bank 0, refresh ahead up to 3
	011 = starting bank 0, refresh ahead up to 7
	100 = burst refresh disable
	101 = starting bank dynamic, no refresh ahead
	110 = starting bank dynamic, refresh ahead up to 3
	111 = starting bank dynamic, refresh ahead up to 7
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" refresh address register:
Bit(s)	Description	(Table P0244)
 7-0	during buffered DMA cycle reflected on bits 23-16 of SA lines,
	  bits 15-10 of SA lines cleared
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" GREEN mode control/enable status:
Bit(s)	Description	(Table P0245)
 7	power management SMI# generation enable
 6	GREEN event SMI# generation
	(read)
	0 = GREEN event did not generate SMI#
	1 = GREEN event generated SMI#
	(write)
	0 = disable GREEN event SMI# generation
	1 = enable GREEN event SMI# generation (if bit 7 set)
 5	reload GREEN event timer/wake-up event SMI# generation
	(read)
	0 = wake-up event did not generate SMI#
	1 = wake-up event generated SMI#
	(write)
	0 = disable wake-up event SMI# generation
	1 = enable wake-up event SMI# generation (if bit 7 set)
 4	power management status (read-only)
	0 = NORMAL
	1 = GREEN
 3	power management PPWRL# generation enable
 2	GREEN event PPWRL# generation enable (if bit 3 set)
 1	reload GREEN event timer/wake-up event PPWRL# generation enable
	  (if bit 3 set)
 0	software generation of GREEN event
	0 = no action
	1 = generate GREEN event (if register E1h bit 0 set)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" EPMI control/GREEN event timer:
Bit(s)	Description	(Table P0246)
 7-6	GREEN event timer CLK period
	00 = 119 microseconds
	01 = 12.25 ms
	10 = 1.94 s
	11 = 62.5 s
 5	EPMI0# polarity
	0 = EPMI0# triggered on falling edge
	1 = EPMI0# triggered on rising edge
 4	EPMI0# debounce enable
 3	EPMI0# polarity
	0 = determined by bit 5
	1 = EPMI0# triggered on transition
 2	GREEN event timer time-out GREEN event generation
	(read)
	0 = GREEN event timer time-out did not cause GREEN event
	1 = GREEN event timer time-out did cause GREEN event
	(write)
	0 = disable GREEN event timer time-out GREEN event generation
	1 = enable GREEN event timer time-out GREEN event generation
 1	EPMI0# trigger GREEN event generation
	(read)
	0 = EPMI0# trigger did not cause GREEN event
	1 = EPMI0# trigger did cause GREEN event
	(write)
	0 = disable EPMI0# trigger GREEN event generation
	1 = enable EPMI0# trigger GREEN event generation
 0	software trigger GREEN event generation
	(read)
	0 = software trigger did not cause GREEN event
	1 = software trigger did cause GREEN event
	(write)
	0 = disable software trigger GREEN event generation
	1 = enable software trigger GREEN event generation
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" GREEN event timer initial count register:
Bit(s)	Description	(Table P0247)
 7-0	time-out timer count - 2
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" IRQ event enable register 1:
Bit(s)	Description	(Table P0248)
 7-3	IRQ7-IRQ3 monitoring enable
 2	IRQ15-IRQ0 deglitch enable
 1-0	IRQ1-IRQ0 monitoring enable
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" IRQ event enable register 2:
Bit(s)	Description	(Table P0249)
 7-0	IRQ15-IRQ8 monitoring enable
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" DREQ event enable register:
Bit(s)	Description	(Table P0250)
 7-5	DREQ7-DREQ5 monitoring enable (if register EFh bit 6 set)
 4	reserved
 3-0	DREQ3-DREQ0 monitoring enable (if register EFh bit 6 set)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" device cycle monitor enable register:
Bit(s)	Description	(Table P0251)
 7	programmable IO/MEM monitoring enable
 6	parallel ports monitoring enable
 5	video monitoring enable
 4	hard disk monitoring enable
 3	floppy disk monitoring enable
 2	keyboard monitoring enable
 1	COM1/COM3 monitoring enable
 0	COM2/COM4 monitoring enable
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" wake-up source/programmable IO/memory address:
Bit(s)	Description	(Table P0252)
 7	PREQ# monitoring enable (if register EFh bit 7 set)
 6	LDEV#/DEVSEL# monitoring enable
 5	EPMI0# trigger monitoring enable
 4	reserved
 3	programmable IO/MEM address type
	0 = I/O
	1 = non-system memory
 2-0	programmable IO/MEM address mask bits 2-0 (bit 3 = register FFh bit 0)
	  (mask lowest n bits)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" programmable I/O/MEM address range register:
Bit(s)	Description	(Table P0253)
 7-0	I/O address bits 7-0 or non-system memory address bits 23-16
	  (use register E7h bit 3 to select I/O or non-system memory address)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" programmable I/O/MEM address range register:
Bit(s)	Description	(Table P0254)
 7-0	I/O address bits 15-8 or non-system memory address bits 31-24
	  (use register E7h bit 3 to select I/O or non-system memory address)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" enter GREEN state port register:
Bit(s)	Description	(Table P0255)
 7-0	GREEN state values for external power control latch
	  (transfered to register ECh on enter GREEN state PPWRL#)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" return to NORMAL state configuration port:
Bit(s)	Description	(Table P0256)
 7-0	NORMAL state values for external power control latch
	  (transfered to register ECh on return to NORMAL state PPWRL#)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" shadow register for external power control latch:
Bit(s)	Description	(Table P0257)
 7-0	external power control latch value
	  (write generates PPWRL#)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" device cycle detection enable/status register:
Bit(s)	Description	(Table P0258)
 7	programmed range access SMI# generation
	(read)
	0 = programmed range access did not generate SMI#
	1 = programmed range access generated SMI#
	(write)
	0 = disable programmed range access SMI# generation
	1 = enable programmed range access SMI# generation
 6	LPT access SMI# generation
	(read)
	0 = LPT access did not generate SMI#
	1 = LPT access generated SMI#
	(write)
	0 = disable LPT access SMI# generation
	1 = enable LPT access SMI# generation
 5	video access SMI# generation
	(read)
	0 = video access did not generate SMI#
	1 = video access generated SMI#
	(write)
	0 = disable video access SMI# generation
	1 = enable video access SMI# generation
 4	hard disk access SMI# generation
	(read)
	0 = hard disk access did not generate SMI#
	1 = hard disk access to generated SMI#
	(write)
	0 = disable hard disk access SMI# generation
	1 = enable hard disk access SMI# generation
 3	floppy disk access SMI# generation
	(read)
	0 = floppy disk access did not generate SMI#
	1 = floppy disk access generated SMI#
	(write)
	0 = disable floppy disk access SMI# generation
	1 = enable floppy disk access SMI# generation
 2	keyboard access SMI# generation
	(read)
	0 = keyboard access did not generate SMI#
	1 = keyboard access generated SMI#
	(write)
	0 = disable keyboard access SMI# generation
	1 = enable keyboard access SMI# generation
 1	COM1/COM3 access SMI# generation
	(read)
	0 = COM1/COM3 access did not generate SMI#
	1 = COM1/COM3 access generated SMI#
	(write)
	0 = disable COM1/COM3 access SMI# generation
	1 = enable COM1/COM3 access SMI# generation
 0	COM2/COM4 access SMI# generation
	(read)
	0 = COM2/COM4 access did not generate SMI#
	1 = COM2/COM4 access generated SMI#
	(write)
	0 = disable COM2/COM4 access SMI# generation
	1 = enable COM2/COM4 access SMI# generation
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" STPCLK# modulation register:
Bit(s)	Description	(Table P0259)
 7	CPU STOPCLK state support enable
 6	STOPCLK state CPU hold enable
 5-4	reserved
 3	STPCLK# modulation enable
 2-0	STPCLK# modulation duty cycle; in effect if bit 3 set
	000 = STPCLK# = 1 always (no modulation)
	001 = STPCLK# = 1 for 1/2 period
	010 = STPCLK# = 1 for 1/4 period
	011 = STPCLK# = 1 for 1/8 period
	100 = STPCLK# = 1 for 1/16 period
	101-111 = reserved
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" miscellaneous register:
Bit(s)	Description	(Table P0260)
 7	PREQ# wake-up enable
 6	DREQ# wake-up enable
 5	reserved
 4	GPCS1# and GPCS#2 generation for addresses in registers F4h-F7h enable
 3	reserved
 2	PPWRL# inititiate clock
	0 = 14 MHz
	1 = 33 KHz
 1	timer count read (registers E0h-E2h, EDh, F0h-F2h, FCh-FEh)
	0 = return current value
	1 = return original value
 0	reserved
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" device timer CLK select/enable status register:
Bit(s)	Description	(Table P0261)
 7-6	device timer 1 CLK period
	00 = 119 microseconds
	01 = 12.25 ms
	10 = 1.94 s
	11 = 62.5 s
 5-4	device timer 0 CLK period
	00 = 119 microseconds
	01 = 12.25 ms
	10 = 1.94 s
	11 = 62.5 s
 3	device timer 1 time-out GREEN event generation
	(read)
	0 = device timer 1 time-out did not cause GREEN event
	1 = device timer 1 time-out did cause GREEN event
	(write)
	0 = disable device timer 1 time-out GREEN event generation
	1 = enable device timer 1 time-out GREEN event generation
 2	device timer 0 time-out GREEN event generation
	(read)
	0 = device timer 0 time-out did not cause GREEN event
	1 = device timer 0 time-out did cause GREEN event
	(write)
	0 = disable device timer 0 time-out GREEN event generation
	1 = enable device timer 0 time-out GREEN event generation
 1	device 1 access wake-up event generation
	(read)
	0 = device 1 access did not cause wake-up event
	1 = device 1 access did cause wake-up event
	(write)
	0 = disable device 1 access wake-up event generation
	1 = enable device 1 access wake-up event generation
 0	device 0 access wake-up event generation
	(read)
	0 = device 0 access did not cause wake-up event
	1 = device 0 access did cause wake-up event
	(write)
	0 = disable device 0 access wake-up event generation
	1 = enable device 0 access wake-up event generation
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" device timer IO/MEM select, mask bits register:
Bit(s)	Description	(Table P0262)
 7	device 1 address type
	0 = I/O
	1 = memory
 6-4	device 1 IO/MEM address mask bits 2-0 (bit 3 = register FFh bit 2)
	  (mask lowest n bits)
 3	device 0 address type
	0 = I/O
	1 = memory
 2-0	device 0 IO/MEM address mask bits 2-0 (bit 3 = register FFh bit 2)
	  (mask lowest n bits)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" device 0 IO/MEM address register:
Bit(s)	Description	(Table P0263)
 7-0	I/O address bits 7-0 or memory address bits 23-16
	  (use register F3h bit 3 to select I/O or memory address)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" device 0 IO/MEM address register:
Bit(s)	Description	(Table P0264)
 7-0	I/O address bits 15-8 or memory address bits 31-24
	  (use register F3h bit 3 to select I/O or memory address)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" device 1 IO/MEM address register:
Bit(s)	Description	(Table P0265)
 7-0	I/O address bits 7-0 or memory address bits 23-16
	  (use register F3h bit 7 to select I/O or memory address)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" device 1 IO/MEM address register:
Bit(s)	Description	(Table P0266)
 7-0	I/O address bits 15-8 or memory address bits 31-24
	  (use register F3h bit 7 to select I/O or memory address)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" power management control register 1:
Bit(s)	Description	(Table P0267)
 7	EPMI1# GREEN event generation
	(read)
	0 = EPMI1# did not cause GREEN event
	1 = EPMI1# caused GREEN event
	(write)
	0 = disable EPMI1# GREEN event generation
	1 = enable EPMI1# GREEN event generation
 6	EPMI1# reload wake-up GREEN state timer enable
 5	EPMI1# polarity
	0 = determined by bit 4
	1 = EPMI1# triggered on transition
 4	EPMI1# polarity
	0 = EPMI1# triggered on falling edge
	1 = EPMI1# triggered on rising edge
 3	EPMI1# debounce enable
 2-0	reserved
Note:	bits 7 and 6 cannot both be set at the same time
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" power management control register 2:
Bit(s)	Description	(Table P0268)
 7	EPMI2# GREEN event generation
	(read)
	0 = EPMI2# did not cause GREEN event
	1 = EPMI2# caused GREEN event
	(write)
	0 = disable EPMI2# GREEN event generation
	1 = enable EPMI2# GREEN event generation
 6	EPMI2# reload wake-up GREEN state timer enable
 5	EPMI2# polarity
	0 = determined by bit 4
	1 = EPMI2# triggered on transition
 4	EPMI2# polarity
	0 = EPMI2# triggered on falling edge
	1 = EPMI2# triggered on rising edge
 3	EPMI2# debounce enable
 2-0	reserved
Note:	bits 7 and 6 cannot both be set at the same time
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" power management control register 3:
Bit(s)	Description	(Table P0269)
 7	EPMI3# GREEN event generation
	(read)
	0 = EPMI3# did not cause GREEN event
	1 = EPMI3# caused GREEN event
	(write)
	0 = disable EPMI3# GREEN event generation
	1 = enable EPMI3# GREEN event generation
 6	EPMI3# reload wake-up GREEN state timer enable
 5	EPMI3# polarity
	0 = determined by bit 4
	1 = EPMI3# triggered on transition
 4	EPMI3# polarity
	0 = EPMI3# triggered on falling edge
	1 = EPMI3# triggered on rising edge
 3	EPMI3# debounce enable
 2-0	reserved
Note:	bits 7 and 6 cannot both be set at the same time
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" general purpose chip select control register:
Bit(s)	Description	(Table P0270)
 7	CPU type
	0 = Intel/AMD
	1 = Cyrix M1
 6	reserved
 5-4	IDE module device ID
	00 = C621h
	01 = D568h
	10 = D768h (ultra DMA)
	11 = reserved
 3	reserved
 2	GPCS2# address bit masking (fourth bit to register F3h bits 6-4)
 1	GPCS1# address bit masking (fourth bit to register F3h bits 2-0)
 0	GPCS0# address bit masking (fourth bit to register E7h bits 2-0)
Note:	indexes ADh and FFh address same register
SeeAlso: #P0219
----------P00220025--------------------------
PORT 0022-0025 - INTEL 82360SL CHIPSET (FOR 386SL)

0022  -W  CPU write mode register
0023  R-  configuration status register
		bit 7: 82360 configuration is open
0024  -W  82360 configuration index
0025  RW  82360 configuration data

Bitfields for Intel 82360SL CPU write mode register:
Bit(s)	Description	(Table P0271)
 0	unlock configuration space
 1	enable selected unit
 3-2	unit
	00 memory configuration
	01 cache
	10 internal bus
	11 external bus
----------P0022002B--------------------------
PORT 0022-002B - INTEL 82355, PART OF CHIPSET FOR 386sx
Note:	initialisation in POST will disable these addresses, only a hard
	  reset will enable them again.

0022w RW  82335 MCR memory configuration register (if LOCK=0) (see #P0272)
0024w RW  82335 RC1 roll compare register (if LOCK=0) (see #P0273)
0026w RW  82335 RC2 roll compare register (if LOCK=0) (see #P0273)
0028w RW  82335 CC0 address range compare register (if LOCK=0) (see #P0274)
002Aw RW  82335 CC1 address range compare register (if LOCK=0) (see #P0274)

Bitfields for 82335 MCR memory configuration register:
Bit(s)	Description	(Table P0272)
 15-12	reserved
 11	"VRO"	video read only (0=r/w, 1=r/o)
 10	"EN#"
	0=enable video RAM accesses (A0000h-8FFFFh)
	1=disable accesses
 9	"ENADP#"
	0=enable adapter ROM accesses (C0000h-8FFFFh)
	1=disable adapter ROM accesses, shadow enabled
 8	"ROMSIZE" 0=256KB ROM, 1=512KB ROM
 7-6	"INTERL" memory interleaving
	00 = 1 memory bank installed (no interleave)
	01 = 2 memory banks installed
	10 = 3 memory banks installed
	11 = 4 memory banks installed
 5	reserved
 4	"DSIZE"	 0=1MBx1DRAMs, 1=256KBx1 or 256KBx4 DRAMs
 3	"S640"	 base memory size is 0=512KB, 1=640KB
 2-1	reserved
 0	"ROMEN#" ROM enable
	0 enable BIOS ROM accesses (E0000h-FFFFFh)
	1 disable BIOS ROM accesses, enable shadow
Note:	One of the remaining reserved bits is the LOCK bit, which will be set
	  during power on, disabling access to the 82335s registers.

Bitfields for 82335 roll compare register:
Bit(s)	Description	(Table P0273)
 15-9	selects address range to be remapped (C23-C17)
 8	reserved
 7-1	selects address bits to be included in re-mapping comparision (M23-M17)
 0	"EN" enables roll address mapping

Bitfields for 82335 address range compare register:
Bit(s)	Description	(Table P0274)
 15-11	specifies top of address range (C23-C19)
 10-8	reserved
 7-3	selects address bits to be included in address range comparision
	  (M23-M19)
 2-1	reserved
 0	"EN" enable address range comparision
----------P00240025--------------------------
PORT 0024-0025 - Intel 82091AA Advanced Integrated Peripheral
Range:	PORT 0022h (X-Bus), PORT 0024h (X-Bus), PORT 026Eh (ISA), or
	  PORT 0398h (ISA)
SeeAlso: PORT 0022h"82091AA",PORT 026Eh"82091AA",PORT 0398h"82091AA"

0024  ?W  configuration register index
0025  RW  configuration register data
----------P00240026--------------------------
PORT 0024-0026 - PicoPower Vesuvius - V3-LS
Note:	software must use 8-bit accesses to these ports; 16-bit accesses will
	  be directed to the V1-LS chip in the chipset instead of the V3-LS
SeeAlso: PORT 0024h"V1-LS"

0024b  ?W  V3-LS register index (see #P0275)
0026b  RW  V3-LS register data

(Table P0275)
Values for PicoPower Vesuvius V3-LS register index:
 00h	revision ID register (see #P0276)
 01h	AT control register 1 (see #P0277)
 02h	AT control register 2 (see #P0278)
 03h	BIOS CS# control register (see #P0279)
 05h	port 92h control register (see #P0280)
 06h	GPEXT low byte register (write high byte into register 07h before
	  writing low byte)
 07h	GPEXT high byte register (write high byte before writing low byte into
	  register 06h)
 08h	miscellaneous configuration register (see #P0281)
 10h	PCI interrupt mapping register 1 (see #P0282)
 11h	PCI interrupt mapping register 2 (see #P0283)
 12h	PCI INT# configuration register (see #P0284)
 13h	serial IRQ control register (see #P0285)
 14h	serial IRQ control register 2 (see #P0286)
 20h	power management control register (see #P0287)
 21h	primary activity IRQ mask register 1 (see #P0288)
 22h	primary activity IRQ mask register 2 (see #P0289)
 23h	PMI trigger IRQ mask register 1 (see #P0290)
 24h	PMI trigger IRQ mask register 2 (see #P0291)
 25h	PMI trigger source register 1 (see #P0292)
 26h	PMI trigger source register 2 (see #P0293)
 30h	8254 counter 0 initial count low byte shadow
 31h	8254 counter 0 initial count high byte shadow
 32h	8254 counter 1 initial count low byte shadow
 33h	8254 counter 1 initial count high byte shadow
 34h	8254 counter 2 initial count low byte shadow
 35h	8254 counter 2 initial count high byte shadow
 36h	8254 counter 0 control word shadow
 37h	8254 counter 1 control word shadow
 38h	8254 counter 2 control word shadow
 39h	8237 DMA controller mode register for channel 0 shadow
 3Ah	8237 DMA controller mode register for channel 1 shadow
 3Bh	8237 DMA controller mode register for channel 2 shadow
 3Ch	8237 DMA controller mode register for channel 3 shadow
 3Dh	8237 DMA controller mode register for channel 4 shadow
 3Eh	8237 DMA controller mode register for channel 5 shadow
 3Fh	8237 DMA controller mode register for channel 6 shadow
 40h	8237 DMA controller mode register for channel 7 shadow
 41h	8259 PIC 1 ICW 1 shadow
 42h	8259 PIC 1 ICW 2 shadow
 43h	8259 PIC 1 ICW 3 shadow
 44h	8259 PIC 1 ICW 4 shadow
 45h	8259 PIC 1 OCW 2 shadow
 46h	8259 PIC 1 OCW 3 shadow
 47h	8259 PIC 2 ICW 1 shadow
 48h	8259 PIC 2 ICW 2 shadow
 49h	8259 PIC 2 ICW 3 shadow
 4Ah	8259 PIC 2 ICW 4 shadow
 4Bh	8259 PIC 2 OCW 2 shadow
 4Ch	8259 PIC 2 OCW 3 shadow
 4Dh	RTC index register shadow
 4Eh	reserved
 4Fh	fixed disk register (port 3F6h) shadow
 50h	hard disk write precompression register (port 1F1h) shadow
 51h	DMA controller 1 status register shadow
 52h	DMA controller 2 status register shadow
 53h	DMAC mask register shadow
 54h	DMA channel 0 base address low byte shadow
 55h	DMA channel 0 base address high byte shadow
 56h	DMA channel 0 base count low byte shadow
 57h	DMA channel 0 base count high byte shadow
 58h	DMA channel 1 base address low byte shadow
 59h	DMA channel 1 base address high byte shadow
 5Ah	DMA channel 1 base count low byte shadow
 5Bh	DMA channel 1 base count high byte shadow
 5Ch	DMA channel 2 base address low byte shadow
 5Dh	DMA channel 2 base address high byte shadow
 5Eh	DMA channel 2 base count low byte shadow
 5Fh	DMA channel 2 base count high byte shadow
 60h	DMA channel 3 base address low byte shadow
 61h	DMA channel 3 base address high byte shadow
 62h	DMA channel 3 base count low byte shadow
 63h	DMA channel 3 base count high byte shadow
 64h	DMA channel 5 base address low byte shadow
 65h	DMA channel 5 base address high byte shadow
 66h	DMA channel 5 base count low byte shadow
 67h	DMA channel 5 base count high byte shadow
 68h	DMA channel 6 base address low byte shadow
 69h	DMA channel 6 base address high byte shadow
 6Ah	DMA channel 6 base count low byte shadow
 6Bh	DMA channel 6 base count high byte shadow
 6Ch	DMA channel 7 base address low byte shadow
 6Dh	DMA channel 7 base address high byte shadow
 6Eh	DMA channel 7 base count low byte shadow
 6Fh	DMA channel 7 base count high byte shadow
 70h	DMA controller 1 command register shadow
 71h	DMA controller 2 command register shadow
Note:	shadow registers (30h-71h) are read-only
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V3-LS revision ID register:
Bit(s)	Description	(Table P0276)
 7-4	V3-LS revision ID
	1h = revision A
	2h = revision B
	3h = revision C
 3-0	V3-LS metal-mask version ID
	0h = version A
	1h = version B
	3h = version C
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS AT control register 1:
Bit(s)	Description	(Table P0277)
 7-6	(revision BB and later) back-to-back delay for 8-bit I/O cycle
	00 = 0.5 SYSCLKs
	01 = 2.5 SYSCLKs
	10 = 4.5 SYSCLKs
	11 = 6.5 SYSCLKs
 5-4	(revision BB and later) back-to-back delay for 16-bit I/O cycle
	00 = 0.5 SYSCLKs
	01 = 1.5 SYSCLKs
	10 = 2.5 SYSCLKs
	11 = 3.5 SYSCLKs
 3	reserved
 2-0	SYSCLK divisor select
	000 = BSERCLK/2
	001 = BSERCLK/3
	010 = BSERCLK/4
	011 = BSERCLK/5
	100 = BSERCLK/6
	101-110 = reserved
	111 = 14MHZCLK/2
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS AT control register 2:
Bit(s)	Description	(Table P0278)
 7	reserved
 6	(revision BB and later) external keyboard chip select
	0 = ROM_KBCS# decodes ports 60h/64h as keyboard ports
	1 = ROM_KBCS# decodes ports 60h/62h/64h/66h as keyboard ports
 5-4	reserved
 3	(revision BB and later) EISA type CMOS RAM interface control enable
 2	(revision BB and later) V3-LS internal I/O port option
	0 = normal V3-LS internal I/O port access
	1 = speed up V3-LS internal I/O port access
 1	extended AT address
 0	AT bus refresh enable
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS BIOS CS# control register:
Bit(s)	Description	(Table P0279)
 7	reserved
 6	flash enable
 5	E8000h-EFFFFh ROMCS# enable
 4	E0000h-E7FFFh ROMCS# enable
 3	D8000h-DFFFFh ROMCS# enable
 2	D0000h-D7FFFh ROMCS# enable
 1	C8000h-CFFFFh ROMCS# enable
 0	C0000h-C7FFFh ROMCS# enable
Notes:	FE000000h-FFFFFFFFh access always generates ROMCS#
	F0000h-FFFFFh access generates ROMCS# if not shadowed
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS port 92h control register:
Bit(s)	Description	(Table P0280)
 7-2	reserved
 1	security lock 1 (port 92h bit 3) function enable
 0	port 92h enable
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS miscellaneous configuration register:
Bit(s)	Description	(Table P0281)
 7	reserved
 6	reserved (ISA master I/O command synchronizer disable)
 5	reserved (timer synchronous IOW# fix disable)
 4	reserved
 3	(revision BB and later) DDMA grant
	0 = V3-LS uses REQ#/GNT# for DDMA retry cycle
	1 = V3-LS does not use REQ#/GNT# for DDMA retry cycle
 2	BSER interrupt enable
 1	(revision BB and later) DDMARETRY
	0 = pin 44 (176-pin) / pin 48 (208-pin) is DDMA_RETRY
	1 = pin 44 (176-pin) / pin 48 (208-pin) is ISA_WAKE
 0	BSER arbitration enable
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS PCI interrupt mapping register 1:
Bit(s)	Description	(Table P0282)
 7-4	map INTB# to IRQ
	0000 = disabled
	0001-0010 = reserved
	0011-0111 = IRQ3-IRQ7
	1000 = reserved
	1001-1100 = IRQ9-IRQ12
	1101 = reserved
	1110-1111 = IRQ14-IRQ15
 3-0	map INTA# to IRQ (same values as bits 7-4)
SeeAlso: #P0275,#P0283

Bitfields for PicoPower Vesuvius V3-LS PCI interrupt mapping register 2:
Bit(s)	Description	(Table P0283)
 7-4	map INTD# to IRQ
	0000 = disabled
	0001-0010 = reserved
	0011-0111 = IRQ3-IRQ7
	1000 = reserved
	1001-1100 = IRQ9-IRQ12
	1101 = reserved
	1110-1111 = IRQ14-IRQ15
 3-0	map INTC# to IRQ (same values as bits 7-4)
SeeAlso: #P0275,#P0282,#P0284

Bitfields for PicoPower Vesuvius V3-LS PCI INT# configuration register:
Bit(s)	Description	(Table P0284)
 7-4	reserved
 3	interrupt D / mappable IRQ 3 configuration
	0 = INTD#, go through level-to-edge conversion
	1 = MIRQ3, bypass level-to-edge conversion
 2	interrupt C / mappable IRQ 2 configuration
	0 = INTC#, go through level-to-edge conversion
	1 = MIRQ2, bypass level-to-edge conversion
 1	interrupt B / mappable IRQ 1 configuration
	0 = INTB#, go through level-to-edge conversion
	1 = MIRQ1, bypass level-to-edge conversion
 0	interrupt A / mappable IRQ 0 configuration
	0 = INTA#, go through level-to-edge conversion
	1 = MIRQ0, bypass level-to-edge conversion
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS serial IRQ control register:
Bit(s)	Description	(Table P0285)
 7	reserved
 6	serial IRQ mode
	0 = host (primary V3-LS)
	1 = source (secondary V3-LS)
 5-4	reserved
 3-2	start cycle length = 2N+4 clocks
 1	host poll
 0	serial IRQ bus enable
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS serial IRQ control register 2:
Bit(s)	Description	(Table P0286)
 7-4	reserved
 3-0	(revision BB and later) serial IRQ sampling slot length
	1111 = 32 slots
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS power management control register:
Bit(s)	Description	(Table P0287)
 7	secondary activity triggered by IRQ1 (write 0 to clear)
 6	secondary activity triggered by IRQ0 (write 0 to clear)
 5	mask IRQ1 from secondary activity
 4	mask IRQ0 from secondary activity
 3	(revision BB and later) IMR disable
 2	primary activity enables PMI
 1	reserved
 0	burst serial bus enable
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS primary activity IRQ mask register 1:
Bit(s)	Description	(Table P0288)
 7-3	mask IRQ7 - IRQ3 from primary activity
 2	mask NMI from primary activity
 1	mask IRQ1 from primary activity
 0	reserved
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS primary activity IRQ mask register 2:
Bit(s)	Description	(Table P0289)
 7-1	mask IRQ15 - IRQ9 from primary activity
 0	mask IRQ8 from primary activity
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS PMI trigger IRQ mask register 1:
Bit(s)	Description	(Table P0290)
 7-3	mask IRQ7 - IRQ3 from PMI
 2	reserved
 1	mask IRQ1 from PMI
 0	mask DDMA slave lock from PMI
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS PMI trigger IRQ mask register 2:
Bit(s)	Description	(Table P0291)
 7-1	mask IRQ15 - IRQ9 from PMI
 0	mask IRQ8 from PMI
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS PMI trigger source register 1:
Bit(s)	Description	(Table P0292)
 7-3	PMI trigger source IRQ7 - IRQ3 active (write 0 to clear)
 2	reserved
 1	PMI trigger source IRQ1 active (write 0 to clear)
 0	PMI trigger source DDMA slave lock active (write 0 to clear)
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS PMI trigger source register 2:
Bit(s)	Description	(Table P0293)
 7-1	PMI trigger source IRQ15 - IRQ9 active (write 0 to clear)
 0	PMI trigger source IRQ8 active (write 0 to clear)
SeeAlso: #P0275
----------P00240027--------------------------
PORT 0024-0027 - PicoPower Vesuvius - V1-LS
Note:	software must use 16-bit accesses to these ports; 8-bit accesses will
	  be directed to the V3-LS chip in the chipset instead of the V1-LS
SeeAlso: PORT 0024h"V3-LS"

0024w  ?W  V1-LS register index (see #P0294)
0026w  RW  V1-LS register data

(Table P0294)
Values for PicoPower Vesuvius V1-LS register index:
 01xxh	(reset sampling and miscellaneous)
 0100h	revision ID register (see #P0295)
 0101h	V1 power on register (see #P0296)
 0108h	V2 version ID register (see #P0297)
 0109h	V2 configuration register (see #P0298)
 010Ah	V2 miscellaneous status register (see #P0299)
 0110h	programmable region 1 register (see #P0300)
 0111h	programmable region 2 register (see #P0300)
 0112h	programmable region 3 register (see #P0300)
 0113h	programmable region 4 register (see #P0300)
 0114h	programmable region control register (see #P0301)
 0118h	SMM control register (see #P0302)
 0119h	processor control register (see #P0303)
 011Ah	write FIFO control register (see #P0304)
 011Bh	PCI control register (see #P0305)
 011Ch	clock skew adjust register (see #P0306)
 011Dh	bus master and snooping control register (see #P0307)
 011Eh	arbiter control register (see #P0308)
 011Fh	docking control register (see #P0309)
 02xxh	(DRAM registers)
 0200h	shadow RAM read enable control register (see #P0310)
 0201h	shadow RAM write enable control register (see #P0311)
 0202h	bank 0 control register (see #P0312)
 0203h	bank 1 control register (see #P0312)
 0204h	bank 0/1 timing control register (see #P0313)
 0205h	bank 2 control register (see #P0312)
 0206h	bank 3 control register (see #P0312)
 0207h	bank 2/3 timing control register (see #P0313)
 0208h	bank 4 control register (see #P0312)
 0209h	bank 5 control register (see #P0312)
 020Ah	bank 4/5 timing control register (see #P0313)
 020Bh	bank 6 control register (see #P0312)
 020Ch	bank 7 control register (see #P0312)
 020Dh	bank 6/7 timing control register (see #P0313)
 020Eh	DRAM configuration register 1 (see #P0314)
 020Fh	DRAM configuration register 2 (see #P0315)
 0210h	DRAM configuration register 3 (see #P0316)
 0211h	DRAM refresh control register (see #P0317)
 0212h	burst EDO control register (see #P0318)
 03xxh	(Power Management control)
 0300h	clock control register (see #P0319)
 0301h	clock throttling period control register (see #P0320)
 0302h	conserve clock throttling ratio/control register (see #P0321)
 0303h	heat regulator clock throttling ratio/control register (see #P0322)
 0304h	doze/sleep mode clock throttling ratio/control register (see #P0323)
 0310h	wake/SMI source register (see #P0324)
 0311h	power management timer status register (see #P0326)
 0312h	power management pin status register (see #P0327)
 0313h	wake mask control register (see #P0328)
 0314h	activity flag register 1 (see #P0329)
 0315h	activity flag register 2 (see #P0330)
 0316h	I/O trap SMI mask register (see #P0331)
 0317h	external SMI trigger mask register (see #P0332)
 0318h	internal SMI trigger mask register (see #P0333)
 0319h	software SMI trigger mask register (see #P0334)
 031Ah	primary activity option control register (see #P0335)
 031Bh	primary activity mask register 1 (see #P0336)
 031Ch	primary activity mask register 2 (see #P0337)
 031Dh	secondary activity mask register (see #P0338)
 031Eh	RING count control register (see #P0339)
 0320h	programmable range monitor control register 1 (see #P0340)
 0321h	programmable range monitor control register 2 (see #P0341)
 0322h	programmable range monitor 0 address register (see #P0342)
 0323h	programmable range monitor 0 compare register (see #P0343)
 0324h	programmable range monitor 1 address register (see #P0342)
 0325h	programmable range monitor 1 compare register (see #P0343)
 0326h	programmable range monitor 2 address register (see #P0342)
 0327h	programmable range monitor 2 compare register (see #P0343)
 0328h	programmable range monitor 3 address register (see #P0342)
 0329h	programmable range monitor 3 compare register (see #P0343)
 032Ah	programmable range monitor 4 address register (see #P0342)
 032Bh	programmable range monitor 4 compare register (see #P0343)
 032Ch	programmable range monitor 5 address register (see #P0342)
 032Dh	programmable range monitor 5 compare register (see #P0343)
 0330h	power management mode register (see #P0344)
 0331h	on/doze mode power control register (see #P0345)
 0332h	sleep mode power control register (see #P0346)
 0333h	suspend mode power control register (see #P0347)
 0335h	doze mode timer register (see #P0348)
 0336h	sleep mode timer register (see #P0349)
 0337h	suspend mode timer register (see #P0349)
 0338h	secondary activity timer register (see #P0350)
 0339h	power on demand primary activity timer register (see #P0351)
 0340h	general purpose control register (see #P0352)
 0341h	general purpose counter/timer control register (see #P0353)
 0342h	general purpose counter/timer current value register (see #P0354)
 0343h	general purpose counter/timer compare register (see #P0355)
 0344h	device timer 0 time-out register (see #P0356)
 0345h	device timer 1 time-out register (see #P0356)
 0346h	device timer 2 time-out register (see #P0356)
 0347h	device timer 3 time-out register (see #P0356)
 0348h	device timer 4 time-out register (see #P0356)
 0349h	device timer 5 time-out register (see #P0356)
 034Ah	device timer time-out source register 1 (see #P0357)
 034Bh	device timer time-out source register 2 (see #P0358)
 034Ch	device timer time-out source register 3 (see #P0359)
 034Dh	device timer time-out source register 4 (see #P0360)
 0350h	LED indicator control register (see #P0361)
 0351h	leakage control register (see #P0362)
 0352h	pin multiplexing control register (see #P0363)
 0353h	debounce control register (see #P0364)
 0354h	edge detect control register (see #P0365)
 04xxh	(Level-2 Cache)
 0400h	L2 cache configuration register (see #P0366)
 0401h	L2 cache timing register (see #P0367)
 0402h	L2 cache miscellaneous register (see #P0368)
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V1-LS revision ID register:
Bit(s)	Description	(Table P0295)
 15-4	reserved
 3-0	V1-LS metal-mask version ID
	3h = revision AA
	4h = revision BB
	5h = revision CC
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS V1 power on register:
Bit(s)	Description	(Table P0296)
 15-12	reserved
 11	use internal clocks for simulation
	0 = internal clock speedup disabled
	0 = internal clock speedup enabled
 10	tristate all outputs
	0 = no tristate condition
	1 = tristate condition
 9	reserved
 8	(revision CC and later) snooping scheme
	0 = HOLD/HLDA
	1 = BOFF#/LOCK#
 7	(revision BB and later) PCI power plane voltage
	0 = 3.3 V
	1 = 5 V
 6	(revision BB and later) DRAM power plane voltage
	0 = 3.3 V
	1 = 5 V
 5-3	clock skew adjust
	000 = 0.0 ns
	001 = +0.55 ns
	010 = +1.10 ns
	011 = +1.65 ns
	100 = -2.20 ns
	101 = -1.65 ns
	110 = -1.10 ns
	111 = -0.55 ns
 2-0	miscellaneous configuration
Note:	this register is read-only
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V2-LS V2 version ID register:
Bit(s)	Description	(Table P0297)
 15-12	reserved
 11-8	V2-LS version ID (even)
	3h = revision AA
	4h = revision BB
 7-4	reserved
 3-0	V2-LS version ID (odd) (same values as bits 11-8)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V2-LS V2 configuration register:
Bit(s)	Description	(Table P0298)
 15	V2-LS process monitor enable (odd)
 14-9	reserved
 8	fast PCI master address transfer enable (odd)
 7	V2-LS process monitor enable (even)
 6-1	reserved
 0	fast PCI master address transfer enable (even)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V2-LS V2 miscellaneous status register:
Bit(s)	Description	(Table P0299)
 15-10	reserved
 9	(revision BB & later) PCI power plane voltage (odd)
	0 = 3.3 V
	1 = 5 V
 8	(revision BB & later) DRAM power plane voltage (odd) (as for bit 9)
 7-2	reserved
 1	(revision BB & later) PCI power plane voltage (even) (as for bit 9)
 0	(revision BB & later) DRAM power plane voltage (even) (as for bit 9)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS programmable region register:
Bit(s)	Description	(Table P0300)
 15-3	programmable region starting address bits 27-15 (bits 31-28 = 0)
	(starting address must be a multiple of block size)
 2-0	programmable region block size
	000 = 32 KB
	001 = 64 KB
	010 = 128 KB
	011 = 256 KB
	100 = 512 KB
	101 = 1 MB
	110-111 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS programmable region control register:
Bit(s)	Description	(Table P0301)
 15-8	reserved
 7-6	programmable region 4 select
	00 = disable
	01 = write-through
	10 = non-cacheable
	11 = reserved
 5-4	programmable region 3 select (same values as bits 7-6)
 3-2	programmable region 2 select (same values as bits 7-6)
 1-0	programmable region 1 select (same values as bits 7-6)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS SMM control register:
Bit(s)	Description	(Table P0302)
 15	SMM RAM access in normal mode lock (can only be written once)
	0 = bit 14 not locked
	1 = bit 14 locked to disabled
 14	load SMI handler into SMM RAM
	0 = access to SMM RAM during normal cycle disabled
	1 = access to SMM RAM during normal cycle enabled
 13	(revision BB and later) swap SMM D/E mapping
	0 = D0000h-DFFFFh mapped to A0000h-AFFFFh and E0000h-EFFFFh mapped to
	  B0000h-BFFFFh
	1 = D0000h-DFFFFh mapped to B0000h-BFFFFh and E0000h-EFFFFh mapped to
	  A0000h-AFFFFh
 12	(revision BB and later) swap SMM 2/3 mapping
	0 = 20000h-2FFFFh mapped to A0000h-AFFFFh and 30000h-3FFFFh mapped to
	  B0000h-BFFFFh
	1 = 20000h-2FFFFh mapped to B0000h-BFFFFh and 30000h-3FFFFh mapped to
	  A0000h-AFFFFh
 11-10	SMM E8000h-EFFFFh select
	00 = normal memory space
	01 = reserved
	10 = SMM space (remap to B8000h-BFFFFh; E8000h-EFFFFh automatically set
	  to non-cacheable)
	11 = reserved
 9-8	SMM E0000h-E7FFFh select
	00 = normal memory space
	01 = reserved
	10 = SMM space (remap to B0000h-B7FFFh; E0000h-E7FFFh automatically set
	  to non-cacheable)
	11 = reserved
 7-6	SMM D8000h-DFFFFh select
	00 = normal memory space
	01 = reserved
	10 = SMM space (remap to A8000h-AFFFFh; D8000h-DFFFFh automatically set
	  to non-cacheable)
	11 = reserved
 5-4	SMM D0000h-D7FFFh select
	00 = normal memory space
	01 = reserved
	10 = SMM space (remap to A0000h-A7FFFh; D0000h-D7FFFh automatically set
	  to non-cacheable)
	11 = reserved
 3	reserved
 2	20000h-3FFFFh remap to A0000h-BFFFFh in SMM mode disable
	(can be used only when L1 and L2 are disabled)
 1	SMRAM KEN disable
 0	reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS processor control register:
Bit(s)	Description	(Table P0303)
 15-10	reserved
 9	FPU error clearing by writing to I/O port F1h disable
 8	FPU error clearing by writing to I/O port F0h disable
 7	reserved
 6	assert INV for write cycle only
 5	write FIFO
	0 = disabled (FIFO forced to one level)
	1 = enabled (FIFO forced to eight level)
 4	combine KEN# and INV pins
 3	linear burst enable
 2	processor pipeline mode enable
 1	L1 write-back enable
 0	CACHE enable
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS write FIFO control register:
Bit(s)	Description	(Table P0304)
 15-7	reserved
 6-5	PCI write buffering select
	00 = disable
	01 = post-write PCI IO write cycle only
	10 = post-write PCI memory write cycle only
	11 = post-write all PCI write cycles
 4	(revision BB and later) PCI read reordering enable
 3	(revision BB and later) DRAM read reordering enable
 2-0	reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS PCI control register:
Bit(s)	Description	(Table P0305)
 15-4	reserved
 3	optimized address transfer between V1-LS and V2-LS enable
 2	reserved
 1	PCI master-to-DRAM burst enable
 0	reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS clock skew adjust register:
Bit(s)	Description	(Table P0306)
 15-3	reserved
 2-0	L2CLK skew adjust
	000 = 0.0 ns
	001 = +0.55 ns
	010 = +1.10 ns
	011 = +1.65 ns
	100 = -2.20 ns
	101 = -1.65 ns
	110 = -1.10 ns
	111 = -0.55 ns
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS bus master and snooping control register:
Bit(s)	Description	(Table P0307)
 15-14	reserved
 13	early DRAM cycle when PCI master accessing DRAM disable
 12-0	reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS arbiter control register:
Bit(s)	Description	(Table P0308)
 15-7	reserved
 6	REQ2# as FLOAT_REQ# and GNT2# as FLOAT_GNT# enable
 5-4	SIO request/grant source
	00 = none
	01 = BSER interface (normal operation)
	10-11 = reserved
 3	preemptability of PCI request/grant 3 disable
 2	preemptability of PCI request/grant 2 disable
 1	preemptability of PCI request/grant 1 disable
 0	preemptability of PCI request/grant 0 disable
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS docking control register:
Bit(s)	Description	(Table P0309)
 15	system docked
 14-4	reserved
 3	DOCK_PCICLK follows state of PCICLK enable
 2	deassert DOCK_PCIRST#
 1	reserved
 0	tristate DOCK_PCIRST# and DOCK_PCICLK in normal operating mode enable
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS shadow RAM read enable control register:
Bit(s)	Description	(Table P0310)
 15	local memory FC000h-FFFFFh read enable
 14	local memory F8000h-FBFFFh read enable
 13	local memory F4000h-F7FFFh read enable
 12	local memory F0000h-F3FFFh read enable
 11	local memory EC000h-EFFFFh read enable
 10	local memory E8000h-EBFFFh read enable
 9	local memory E4000h-E7FFFh read enable
 8	local memory E0000h-E3FFFh read enable
 7-4	local memory Dx000h-DyFFFh read enable
	  (x/y = 0/3 for bit 4, 4/7 for bit 5, etc.)
 3-0	local memory Cx000h-CyFFFh read enable
	  (x/y = 0/3 for bit 0, 4/7 for bit 1, etc.)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS shadow RAM write enable control:
Bit(s)	Description	(Table P0311)
 15	local memory FC000h-FFFFFh write enable
 14	local memory F8000h-FBFFFh write enable
 13	local memory F4000h-F7FFFh write enable
 12	local memory F0000h-F3FFFh write enable
 11	local memory EC000h-EFFFFh write enable
 10	local memory E8000h-EBFFFh write enable
 9	local memory E4000h-E7FFFh write enable
 8	local memory E0000h-E3FFFh write enable
 7-4	local memory Dx000h-DyFFFh write enable
	  (x/y = 0/3 for bit 4, 4/7 for bit 5, etc.)
 3-0	local memory Cx000h-CyFFFh write enable
	  (x/y = 0/3 for bit 0, 4/7 for bit 1, etc.)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS bank control register:
Bit(s)	Description	(Table P0312)
 15	reserved
 14-12	number of column address bits for bank
	000 = 8 bits
	001 = 9 bits
	010 = 10 bits
	011 = 11 bits
	100 = 12 bits
	101-111 = reserved
 11-9	bank DRAM size
	000 = 1 MB
	001 = 2 MB
	010 = 4 MB
	011 = 8 MB
	100 = 16 MB
	101 = 32 MB
	110 = 64 MB
	111 = reserved
 8	reserved
 7-0	bank starting address bits 27-20
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS bank timing control register:
Bit(s)	Description	(Table P0313)
 15-14	reserved
 13-12	bank 0/2/4/6 and 1/3/5/7 CAS write pulse width
	00 = 0.5T (EDO or burst EDO only)
	01 = 1.0T
	10 = 1.5T
	11 = 2.0T
 11-9	bank 0/2/4/6 and 1/3/5/7 CAS read pulse width
	000 = 0.5T (EDO or burst EDO only)
	001 = 1.0T
	...
	111 = 4.0T
 8	bank 0/2/4/6 and 1/3/5/7 CAS precharge time
	0 = 0.5T
	1 = 1.0T
 7	bank 0/2/4/6 and 1/3/5/7 CAS address hold time (same values as bit 8)
 6-5	bank 0/2/4/6 and 1/3/5/7 RAS address setup time
	00 = 0.0T
	01 = 0.5T
	10 = 1.0T
	11 = 1.5T
 4-3	bank 0/2/4/6 and 1/3/5/7 RAS address hold time = N/2 + 0.5T
 2-0	bank 0/2/4/6 and 1/3/5/7 RAS precharge time    = N/2 + 1.5T
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS DRAM configuration register 1:
Bit(s)	Description	(Table P0314)
 15-9	reserved
 8	fast cacheless read enable (L2 must be disabled and L2 read lead-off
	  must be 2T)
 7-6	DRAM auto-detect mode
	00 = normal mode
	01 = setup for auto-detect
	10 = reserved
	11 = auto-detect read mode
 5-3	DRAM inactive time-out
	000 = never
	001 = 8 T
	010 = 32 T
	011 = 128 T
	100 = 512 T
	101-110 = reserved
	111 = immediate
 2-0	reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS DRAM configuration register 2:
Bit(s)	Description	(Table P0315)
 15-12	reserved
 11	banks 6 and 7
	0 = two 32-bit banks
	1 = one 64-bit bank (bits 7-6 ignored; bank 6 DRAM parameters used;
	  programmed bank 6 size doubled)
 10	banks 4 and 5 (same settings as for bit 11)
 9	banks 2 and 3 (same settings as for bit 11)
 8	banks 0 and 1
	0 = two 32-bit banks
	1 = one 64-bit bank (bits 1-0 ignored; bank 0 DRAM parameters used;
	  programmed bank 0 size doubled)
 7-0	corresponding bank enable
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS DRAM configuration register 3:
Bit(s)	Description	(Table P0316)
 15-14	bank 7 DRAM type
	00 = standard
	01 = EDO
	10 = burst EDO
	11 = reserved
 13-12	bank 6 DRAM type (same values as bits 15-14)
 11-10	bank 5 DRAM type (same values as bits 15-14)
 9-8	bank 4 DRAM type (same values as bits 15-14)
 7-6	bank 3 DRAM type (same values as bits 15-14)
 5-4	bank 2 DRAM type (same values as bits 15-14)
 3-2	bank 1 DRAM type (same values as bits 15-14)
 1-0	bank 0 DRAM type (same values as bits 15-14)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS DRAM refresh control register:
Bit(s)	Description	(Table P0317)
 15-14	reserved
 13-12	refresh stagger select
	00 = no staggering
	01 = reserved
	10 = stagger active edge of RAS
	11 = stagger both edges of RAS
 11	reserved
 10	suspend mode self-refresh enable
 9-8	reserved
 7-5	refresh period
	000 = 3.75 æs
	001 = 7.5 æs
	010 = 15 æs
	011 = 30 æs
	100 = 120 æs
	101 = stopped
	110-111 = reserved
 4-3	RAS pulse width for refresh cycles
	00 = 6T
	01 = 5T
	10 = 4T
	11 = 3T
 2-1	RAS precharge time for refresh cycles
	00 = 5T
	01 = 4T
	10 = 3T
	11 = 2T
 0	DRAM refresh scheme
	0 = CAS-before-RAS
	1 = RAS-only
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS burst EDO control register:
Bit(s)	Description	(Table P0318)
 15-4	MA setting during write CAS-before-RAS cycle
 3	trigger write CAS-before-RAS configuration cycle
 2-1	DRAM bank configuration select
	00 = bank 0/1
	01 = bank 2/3
	10 = bank 4/5
	11 = bank 6/7
 0	burst EDO write CAS-before-RAS configuration cycle enable
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS clock control register:
Bit(s)	Description	(Table P0319)
 15	modular clocking on V2 clock enable
 14-12	reserved
 11	PCI clock control CLKRUN# method enable
 10	reserved
 9	PCI clock goes back to full speed on PCI LOCK# enable
 8	PCI clock goes back to full speed on PCI request/grant enable
 7-6	reserved
 5-4	PCI idle count (PCI clocks)
	00 = immediate
	01 = 8
	10 = 32
	11 = 256
 3-2	reserved
 1-0	PCI clock divisor during idle
	00 = 1
	01 = 2
	10 = 32
	11 = 256
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS clock throttling period control:
Bit(s)	Description	(Table P0320)
 15-3	reserved
 2-0	clock throttling period select (T = CPU bus frequency period)
	000 = 800T
	001 = 1600T
	010 = 3200T
	011 = 6400T
	100 = 12800T
	101 = 25600T
	110 = 102400T
	111 = 409600T
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS conserve clock throttling ratio/control register:
Bit(s)	Description	(Table P0321)
 15-5	reserved
 4	conserve clock throttling enable
 3-0	conserve clock throttling ratio
	0000 = 5% duty cycle
	0001-1001 = 10%-90% duty cycle
	1010-1111 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS heat regulator clock throttling:
Bit(s)	Description	(Table P0322)
 15-13	reserved
 12	THERM input enable
 11-4	reserved
 3-0	heat regulator clock throttling ratio
	0000 = 5% duty cycle
	0001-1001 = 10%-90% duty cycle
	1010-1111 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS doze/sleep mode clock throttling:
Bit(s)	Description	(Table P0323)
 15-11	reserved
 10-8	STPCLK release latency (PLL stabilization delay)
	000 = 0 s
	001 = 1 æs
	010 = 45 æs
	011 = 1 ms
	100 = 2 ms
	101-111 = reserved
 7-5	sleep mode clock throttling enable
	000 = disable
	001 = enable in ratio set in bits 3-0
	010 = enable LessStop mode (CPU stop grant state)
	011 = enable MoreStop mode (CPU stop clock state)
	100 = enable Deep Sleep mode (MoreStop and high speed oscillator off,
	  only 32 kHz running)
 4	doze mode clock throttling enable
 3-0	doze/sleep mode clock throttling ratio
	0000 = 5% duty cycle
	0001-1001 = 10%-90% duty cycle
	1010-1111 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS wake/SMI source register:
Bit(s)	Description	(Table P0324)
 15-11	reserved
 10-8	wake-up source
	000 = none
	001 = RING
	010 = SWTCH
	011 = GP timer compare
	100 = WAKE0
	101 = WAKE1
	110 = reserved
	111 = clear wake-up source (write to clear)
 7-5	reserved
 4-0	SMI source (see #00671)
SeeAlso: #P0294

(Table P0325)
Values for PicoPower Vesuvius V1-LS SMI source:
 00h	none
 01h	primary activity
 02h	I/O trap
 03h	device timer time-out
 04h	doze time-out
 05h	sleep time-out
 06h	suspend time-out
 07h	GP timer compare
 08h	SWTCH input toggling
 09h	reserved
 0Ah	WAKE0 input toggling
 0Bh	WAKE1 input toggling
 0Ch	EXTACT0 toggling
 0Dh	reserved
 0Eh	rescheduled SMI
 0Fh	software SMI
 10h	V3-LS INT SMI
 11h-1Eh reserved
 1Fh	clear SMI source (write to clear)
SeeAlso: #P0324

Bitfields for PicoPower Vesuvius V1-LS power management timer status register:
Bit(s)	Description	(Table P0326)
 15-3	reserved
 2	suspend time-out status (write 0 to clear)
 1	sleep time-out status (write 0 to clear)
 0	doze time-out status (write 0 to clear)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS power management pin status register:
Bit(s)	Description	(Table P0327)
 15-6	reserved
 5	SWTCH pin status (read-only)
 4	RING pin status (read-only)
 3	reserved
 2	EXTACT0 pin status (read-only)
 1	WAKE1 pin status (read-only)
 0	WAKE0 pin status (read-only)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS wake mask control register:
Bit(s)	Description	(Table P0328)
 15-5	reserved
 4	mask GP timer compare from resume
 3	mask RING from resume
 2	mask SWTCH from resume
 1	mask WAKE1 from resume
 0	mask WAKE0 from resume
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS activity flag register 1:
Bit(s)	Description	(Table P0329)
 15-10	programmable range 5-0 monitor active (write 0 to clear)
 9	reserved
 8	HOLD active (write 0 to clear)
 7	parallel I/O active (write 0 to clear)
 6	serial I/O 2 active (write 0 to clear)
 5	serial I/O 1 active (write 0 to clear)
 4	keyboard active (write 0 to clear)
 3	floppy disk active (write 0 to clear)
 2	hard disk 2 active (write 0 to clear)
 1	hard disk 1 active (write 0 to clear)
 0	video active (write 0 to clear)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS activity flag register 2:
Bit(s)	Description	(Table P0330)
 15-14	reserved
 13-8	device timer 5-0 time-out (write 0 to clear)
 7	FLOAT_REQ# active (write 0 to clear)
 6	EXTACT0 active (write 0 to clear)
 5	WAKE1 active (write 0 to clear)
 4	WAKE0 active (write 0 to clear)
 3	SWTCH active (write 0 to clear)
 2	RING active (write 0 to clear)
 1	reserved
 0	V3-LS active (write 0 to clear)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS I/O trap SMI mask register:
Bit(s)	Description	(Table P0331)
 15-10	programmable range 5-0 device on
 9-8	reserved
 7	parallel I/O on
 6	serial I/O 2 on
 5	serial I/O 1 on
 4	keyboard on
 3	floppy disk on
 2	hard disk 2 on
 1	hard disk 1 on
 0	video on
Note:	No group mask for I/O trap.
	SMI generated if a bit is 0 and corresponding device is accessed.
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS external SMI trigger mask register:
Bit(s)	Description	(Table P0332)
 15-4	reserved
 3	mask EXTACT0 from SMI
 2	mask SWTCH from SMI
 1	mask WAKE1 from SMI
 0	mask WAKE0 from SMI
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS internal SMI trigger mask register:
Bit(s)	Description	(Table P0333)
 15-10	reserved
 9	mask GP timer compare from SMI
 8	mask suspend time-out from SMI
 7	mask sleep time-out from SMI
 6	mask doze time-out from SMI
 5-0	mask device timer 5-0 time-out from SMI
Note:	Primary activity mask is in register 31Ah bit 1.
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS software SMI trigger mask register:
Bit(s)	Description	(Table P0334)
 15-10	reserved
 9	soft SMI on I/O write to port B0h enable
 8	soft SMI immediate (write 1 to trigger SMI; read value has no meaning)
 7-5	reserved
 4	reschedule SMI prescalar
	0 = 10 ms
	1 = 100 ms
 3-0	reschedule SMI select
	0000 = disable
	0001-1001 = 1-9
	1010-1111 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS primary activity option control:
Bit(s)	Description	(Table P0335)
 15-5	reserved
 4	(revision BB and later) mask SMI from primary activity
 3	primary activity on disable
 2	primary activity latching in SMM mode enable
 1	mask primary activity from SMI
 0	primary activity flag enable
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS primary activity mask register 1:
Bit(s)	Description	(Table P0336)
 15-10	primary activity mask programmable range 5-0 accesses
 9	reserved
 8	primary activity mask HOLD
 7	primary activity mask parallel I/O accesses
 6	primary activity mask serial I/O 2 accesses
 5	primary activity mask serial I/O 1 accesses
 4	primary activity mask keyboard accesses
 3	primary activity mask floppy disk accesses
 2	primary activity mask hard disk 2 accesses
 1	primary activity mask hard disk 1 accesses
 0	primary activity mask video accesses
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS primary activity mask register 2:
Bit(s)	Description	(Table P0337)
 15-13	reserved
 12	primary activity mask FLOAT_REQ#
 11	primary activity mask SWTCH
 10	primary activity mask WAKE1
 9	primary activity mask WAKE0
 8	primary activity mask RING
 7	reserved
 6	primary activity mask EXTACT0
 5-0	reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS secondary activity mask register:
Bit(s)	Description	(Table P0338)
 15-7	reserved
 6	mask EXTACT0 from secondary activity
 5-2	reserved
 1	mask HOLD from secondary activity
 0	mask SMI from secondary activity
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS RING count control register:
Bit(s)	Description	(Table P0339)
 15-5	reserved
 4	RINGS ten's digit
	0 = 0
	1 = 1
 3-0	RINGS one's digit
	0000 = disabled (ring counter reset, if bit 4 = 0)
	0001-1001 = 1-9
	1010-1111 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS programmable range monitor control 1:
Bit(s)	Description	(Table P0340)
 15-14	reserved
 13-8	programmable range monitor 5-0 enable
 7-6	reserved
 5-0	programmable range monitor 5-0 memory or I/O compare
	0 = I/O
	1 = memory
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS programmable range monitor control 2:
Bit(s)	Description	(Table P0341)
 15-14	reserved
 13-8	programmable range monitor 5-0 read enable
 7-6	reserved
 5-0	programmable range monitor 5-0 write enable
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS programmable range monitor address:
Bit(s)	Description	(Table P0342)
 15-0	programmable range monitor address (I/O address bits 15-0; memory
	  address bits 31-16)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS programmable range monitor compare:
Bit(s)	Description	(Table P0343)
 15-0	programmable range monitor compare enable (I/O address bits 15-0;
	  memory address bits 31-16)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS power management mode register:
Bit(s)	Description	(Table P0344)
 15-4	reserved
 3	resume
 2-0	system management mode
	000 = on
	001 = doze
	010 = sleep or deep sleep
	011 = suspend
	100-111 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS on/doze mode power control register:
Bit(s)	Description	(Table P0345)
 15-6	reserved
 5-0	power control on/doze mode (if on/doze mode active, 1 means
	  corresponding power control pin is active)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS sleep mode power control register:
Bit(s)	Description	(Table P0346)
 15-6	reserved
 5-0	power control sleep mode (if sleep mode active, 1 means corresponding
	  power control pin is active)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS suspend mode power control register:
Bit(s)	Description	(Table P0347)
 15-6	reserved
 5-0	power control suspend mode (if suspend mode active, 1 means
	  corresponding power control pin is active)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS doze mode timer register:
Bit(s)	Description	(Table P0348)
 15-10	reserved
 9	doze mode timer enable
 8	doze mode timer reset by primary activity enable
 7	doze mode timer clock prescalar
	0 = 100 ms
	1 = 1 s
 6-4	doze mode timer ten's digit
	000-111 = 0-7
 3-0	doze mode timer one's digit
	0000-1001 = 0-9
	1010-1111 = reserved
Note:	the timer is disabled when both ten's and one's digits are 0
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS sleep/suspend mode timer register:
Bit(s)	Description	(Table P0349)
 15-10	reserved
 9	sleep/suspend mode timer enable
 8-7	reserved
 6-4	sleep/suspend mode timer ten's digit (0-7)
 3-0	sleep/suspend mode timer one's digit
	0000-1001 = 0-9
	1010-1111 = reserved
Note:	the timer is disabled when both ten's and one's digits are 0
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS secondary activity timer register:
Bit(s)	Description	(Table P0350)
 15-10	reserved
 9	secondary activity timer enable
 8	reset secondary activity on SMI
 7	secondary activity timer clock prescalar
	0 = 100 æs
	1 = 1 ms
 6-4	secondary activity timer ten's digit (0-7)
 3-0	secondary activity timer one's digit
	0000-1001 = 0-9
	1010-1111 = reserved
Note:	the timer is disabled when both ten's and one's digits are 0
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS power on demand primary activity timer:
Bit(s)	Description	(Table P0351)
 15-10	reserved
 9	primary activity timer enable
 8	reserved
 7	primary activity timer clock prescalar
	0 = 100 æs
	1 = 1 ms
 6-4	primary activity timer ten's digit (0-7)
 3-0	primary activity timer one's digit
	0000-1001 = 0-9
	1010-1111 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS general purpose control register:
Bit(s)	Description	(Table P0352)
 15-14	reserved
 13-8	general purpose I/O 5-0 direction
	0 = corresponding GPIO pin is an input
	1 = corresponding GPIO pin is an output
 7-6	reserved
 5-0	general purpose I/O 5-0 data
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS general purpose counter/timer control:
Bit(s)	Description	(Table P0353)
 15-8	reserved
 7	general purpose counter/timer enable
 6-5	general purpose counter/timer select
	     bit 4 = 0	     bit 4 = 1
	00 = 16-bit counter  16-bit counter  (GPIO3 is counter clock)
	01 = 24-bit counter  24-bit counter  (GPIO3 is counter clock)
	10 = 1 second timer  31.25 æs timer
	11 = 1 minute timer  1.875 ms timer
 4	general purpose counter/timer clock select
	0 = 1 Hz
	1 = 32 kHz
 3-0	reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS general purpose counter/timer value:
Bit(s)	Description	(Table P0354)
 15-0	general purpose counter/timer current value (24-bit counter bits
	  23-8, otherwise counter/timer bits 15-0; any write resets
	  counter/timer)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS general purpose counter/timer compare:
Bit(s)	Description	(Table P0355)
 15-0	general purpose counter/timer compare (24-bit counter compare value
	  bits 23-8, otherwise compare value bits 15-0)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS device timer 5-0 time-out register:
Bit(s)	Description	(Table P0356)
 15-6	reserved
 5-4	device timer time-out prescalar
	00 = 1 s
	01 = 10 s
	10 = 1 min.
	11 = 10 min.
 3-0	device timer time-out select
	0000 = disable
	0001-1001 = 1-9
	1010-1111 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS device timer time-out source register 1:
Bit(s)	Description	(Table P0357)
 15	reserved
 14-12	keyboard activity device timer select
	000 = none
	001-110 = 0-5
	111 = reserved
 11-9	floppy disk activity device timer select (same values as bits 14-12)
 8-6	hard disk 2 activity device timer select (same values as bits 14-12)
 5-3	hard disk 1 activity device timer select (same values as bits 14-12)
 2-0	video activity device timer select (same values as bits 14-12)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS device timer time-out source register 2:
Bit(s)	Description	(Table P0358)
 15	reserved
 14-12	programmable range 1 activity device timer select
	000 = none
	001-110 = 0-5
	111 = reserved
 11-9	programmable range 0 activity device timer select (same values as
	  bits 14-12)
 8-6	parallel port activity device timer select (same values as bits 14-12)
 5-3	serial port 2 activity device timer select (same values as bits 14-12)
 2-0	serial port 1 activity device timer select (same values as bits 14-12)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS device timer time-out source register 3:
Bit(s)	Description	(Table P0359)
 15-12	reserved
 11-9	programmable range 5 activity device timer select
	000 = none
	001-110 = 0-5
	111 = reserved
 8-6	programmable range 4 activity device timer select (same values as
	  bits 11-9)
 5-3	programmable range 3 activity device timer select (same values as
	  bits 11-9)
 2-0	programmable range 2 activity device timer select (same values as
	  bits 11-9)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS device timer time-out source register 4:
Bit(s)	Description	(Table P0360)
 15-3	reserved
 2-0	EXTACT0 activity device timer select
	000 = none
	001-110 = 0-5
	111 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS LED indicator control register:
Bit(s)	Description	(Table P0361)
 15-13	reserved
 12-11	LED1 flash duration
	00 = 256 ms (cannot be set if flash rate is 2 or 4 Hz)
	01 = 128 ms (cannot be set if flash rate is 4 Hz)
	10 = 62.5 ms
	11 = 31.25 ms
 10-9	LED1 flash rate select
	00 = 0.5 Hz
	01 = 1 Hz
	10 = 2 Hz
	11 = 4 Hz
 8	LED1 flasher enable
 7-5	reserved
 4-3	LED0 flash duration (same values as bits 12-11)
 2-1	LED0 flash rate select (same values as bits 10-9)
 0	LED0 flasher enable
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS leakage control register:
Bit(s)	Description	(Table P0362)
 15-2	reserved
 1	input leakage control during 5 V suspend enable
 0	output leakage control during 5 V suspend enable
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS pin multiplexing control register:
Bit(s)	Description	(Table P0363)
 15	PC5 function
	0 = PC5
	1 = reserved
 14	PC4 function
	0 = PC4
	1 = LED1 output
 13	PC3 function
	0 = PC3
	1 = LED0 output
 12	reserved
 11-10	GPIO5 function
	00 = GPIO5
	01 = reserved
	10 = THERM input active-high
	11 = THERM input active-low
 9-8	GPIO4 function
	00 = GPIO4
	01 = reserved
	10 = (revision BB and later) SUSPA# input
	11 = reserved
 7-6	GPIO3 function
	00 = GPIO3
	01 = SUPPRESS_RESUME input
	10-11 = reserved
 5-4	GPIO2 function
	00 = GPIO2
	01 = DDMA_RETRY input
	10 = DPSLP_IRQPA input
	11 = reserved
 3-2	GPIO1 function
	00 = GPIO1
	01 = LED1 output
	10 = (revision BB and later) FLOAT_GNT# output
	11 = reserved
 1-0	GPIO0 function
	00 = GPIO0
	01 = LED0 output
	10 = (revision BB and later) FLOAT_REQ# input
	11 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS debounce control register:
Bit(s)	Description	(Table P0364)
 15-5	reserved
 4	EXTACT0 debounce select
	0 = 0 s
	1 = 20 ms
 3	RING debounce select (same values as bit 4)
 2	WAKE1 debounce select (same values as bit 4)
 1	WAKE0 debounce select (same values as bit 4)
 0	SWTCH debounce select (same values as bit 4)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS edge detect control register:
Bit(s)	Description	(Table P0365)
 15-10	reserved
 9-8	EXTACT0 edge detect
	00 = reserved
	01 = falling
	10 = rising
	11 = rising and falling
 7-6	RING edge detect
	00 = reserved
	01 = falling
	10 = rising
	11 = reserved
 5-4	WAKE1 edge detect (same values as bits 9-8)
 3-2	WAKE0 edge detect (same values as bits 9-8)
 1-0	SWTCH edge detect (same values as bits 9-8)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS L2 cache configuration register:
Bit(s)	Description	(Table P0366)
 15-10	reserved
 9	TAG initialization enable
 8	NALE mode select
	0 = TAGCS#/NALE# pin is in TAGCS# mode
	1 = TAGCS#/NALE# pin is in NALE# mode
 7	pipelined burst SRAM enable (if bits 5-4 = 01)
 6	reserved
 5-4	L2 cache type
	00 = standard asynchronous
	01 = standard synchronous
	10-11 = reserved
 3-1	L2 cache size select
	000 = 128 KB
	001 = 256 KB
	010 = 512 KB
	011 = 1 MB
	100-111 = reserved
 0	L2 cache enable
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS L2 cache timing register:
Bit(s)	Description	(Table P0367)
 15-8	reserved
 7-6	L2 cache write follow-on
	00 = 1T
	01-11 = reserved
 5-4	L2 cache write leadoff
	00 = 2T
	01 = 3T
	10 = 4T
	11 = reserved
 3-2	L2 cache read follow-on (same values as bits 7-6)
 1-0	L2 cache read leadoff (same values as bits 5-4)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS L2 cache miscellaneous register:
Bit(s)	Description	(Table P0368)
 15-10	reserved
 9-8	(revision BB and later) pipeline on memory read-miss cycle enable
	x0 = disable
	01 = enable (NA generated same time as first BRDY#)
	11 = enable (NA generated as soon as internal read request recognized)
 7	power management on CE# only for 50 MHz operation disable
 6	advanced synchronous power enhanced cache timing enable
 5-2	reserved
 1	invalidation of ROM address disable
 0	dead clock enable
SeeAlso: #P0294
----------P00240029--------------------------
PORT 0024-0029 - HEADLAND HTK340 SHASTA 386/486 CHIPSET

0024  Rw  data port
0028  ?W  index port to chipset registers (see #P0369,#P0370)

(Table P0369)
Values for Headland HT321 register index:
 00h R	chip/revision,read-only
	  bit7-4: reserved (=0)
	  bit3-0: chip revision, 0=A, 1=B, 3=D
 01h RW system clocking (default=00h)
	  bit7-4: reserved (=0)
	  bit3-0: ISA speed set
 02h RW system parameters (default=00h) (see #P0371)
 04h RW co-processor (default=00h)
	  bit7-3: reserved (=0)
	  bit2=1: soft-NPU reset blocked (386 only)
	  bit1=1: weitek installed
	  bit0=1: 387 installed
 06h RW DMA (default=00h) (see #P0372)
 07h RW EPROM (default=00h) (see #P0373)
 08h RW I/O and memory map holes (default=00h)
	  bit7-4: reserved (=0)
	  bit3	: 0/1 I/O map hole-A
	  bit2	: reserved (=0)
	  bit1	: 0/1 memory map hole-B
	  bit0	: reserved (=0)
 10h RW hole-A low address (default=00h)
 11h RW hole-A high address (default=00h)
 19h RW mem hole-B start address, lower (default=00h)
 1Ah RW mem hole-B start address, higher (default=00h)
	  bit7-6: reserved (=0)
	  bit5-0: address of mem hole-B start
 1Ch RW mem hole-B end address, lower (default=00h)
 1Dh RW mem hole-B end address, higher (default=00h)
	  bit7-6: reserved (=0)
	  bit5-0: address of mem hole-B end
SeeAlso: #P0370

(Table P0370)
Values for Headland HT342 register index:
 20h R	identifier port read
	  bit7-4: DRAM controller identifier (0010b)
	  bit3-0: revision number (0=A)
 21h R	feature port read    (default=00h)
 24h RW DRAM options port #1 (default=00h)
	  bit7	: 0/1 staggered refresh
	  bit6	: refresh type
	  bit5	: 0/1 DRAM paging
	  bit4-2: CAS interleave
	  bit1-0: banks
 25h	DRAM options port #2 (default=00h)
	  bit7-6: DRAM bank 1 type
	  bit5-4: DRAM bank 2 type
	  bit3-2: DRAM bank 1?? type
	  bit1-0: DRAM bank 0 type
 26h RW DRAM options port #3 (default=FFh) (see #P0374)
 27h RW DRAM options port #4 (default=FFh) (see #P0375)
 28h RW data transfer control port (default=00h)
	doubled indexed registers (28h-2Ah)
	  bit7	: initiate transfer
	  bit6	: read/write transfer
	  bit5-4: reserved
	  bit3-0: transfer/destination
 29h RW RAM address register (default=00h)
	doubled indexed registers (28h-2Ah)
	  bit7-5: reserved
	  bit4-0: RAM address registers contents
 2Ah RW data transfer port   (default=00h)
	doubled indexed registers (28h-2Ah)
	  bit7-6: reserved
	  bit5	: EMS translation
	  bit4	: reserved
	  bit3	: 0/1 cacheing
	  bit2	: 0/1 write
	  bit1	: 0/1 read
	  bit0	: 0/1 shadow
 2Bh RW other options	      (default=00h) (see #P0376)
 2Dh RW DRAM options port #5 (default=03h)
	  bit7-5: reserved
	  bit4	: 0/1 10æs RAS timeout
	  bit3-2: BUS speed
	  bit1-0: BUS recovery for DRAM cycles
		   00b=0: 4-1-1-1    10b=0.5
		   01b=1: 4-2-2-2    11b=1??
 82h	read transfer
 C2h	write transfer
SeeAlso: #P0369

Bitfields for Headland HT321 register 02h (system parameters):
Bit(s)	Description	(Table P0371)
 7-6	IO recovery time (rev. D+)
 5	parity override
 4-3	cycle-width
 2	0/1 PORT 0092h functionality
 1	IO decode
 0	0/1 posted backplane MEMWN cycles
SeeAlso: #P0369

Bitfields for Headland HT321 register 06h (DMA control):
Bit(s)	Description	(Table P0372)
 7	reserved (=0)
 6	1/0 IOCHRDY during master cycle (rev. C+)
 5	0/1 fast sample DMA
 4-3	DMA waitstate 00b=3 .. 11b=0
 2	0/1 DMA flow-through mode
 1	0/1 extended DMA page register
 0	DMA clock
SeeAlso: #P0369

Bitfields for Headland HT321 register 07h (EPROM control):
Bit(s)	Description	(Table P0373)
 7-6	reserved (=0)
 5	0/1 EADS CACHE invalidation for EPROM writes (rev. D+)
 4	0/1 ROMEN for EPROM writes (rev. C+)
 3	0/1 middle BIOS region of 64KB space below 16MB
 2	ROM-size (0=64KB, 1=128KB)
 1	V-BIOS-add (0=separate, 1=same device)
 0	ROM-access time (0=250ns, 1=125ns)
SeeAlso: #P0369

Bitfields for Headland HT342 register 26h (DRAM CAS control):
Bit(s)	Description	(Table P0374)
 7	CAS hold on RAS (CAS before RAS refresh)
 6	CAS precharge
 5	CAS burst delay
 4	CAS delay (writes)
 3	CAS delay (reads)
 2	CAS active time (writes)
 1-0	CAS active time (reads)
SeeAlso: #P0370,#P0375

Bitfields for Headland HT342 register 27h (DRAM RAS control):
Bit(s)	Description	(Table P0375)
 7	RAS delay
 6-5	RAS active (writes)
 4-2	RAS active (reads)
 1-0	RAS precharge
SeeAlso: #P0370,#P0374

Bitfields for Headland HT342 register 2Bh (other options):
Bit(s)	Description	(Table P0376)
 7	reserved
 6	0/1 middle BIOS
 5	0/1 data pipeline
 4	0/1 data pipeline
 3	IO-decode
 2	reserved
 1	16bit DMA bridge
 0	0/1 write buffering
SeeAlso: #P0370
----------P00260027--------------------------
PORT 0026-0027 - INTEL 82347 POWER MANAGEMENT PERIPHERAL
SeeAlso: PORT 0178h-0179h

0026  -W  index for data port (see #P0377)
0027  RW  power management data

(Table P0377)
Values for Intel 82437 Power Management Peripheral register index:
 C0h	suspend/wakeup status, system state
 C1h	power supply and activity status, general-purpose output/control
 C2h	control bits
 C3h	activity mask
 C4h	NMI mask
 C5h	I/O range for activity monitor
 C6h	power output control bits, ON state
 C7h	power output control bits, Doze state
 C8h	power output control bits, Sleep state
 C9h	power output control bits, Suspend state
 CAh	power control bits polarity control
 CBh	current output bits
 CCh	Doze timeout
 CDh	Sleep timeout
 CEh	Suspend timeout
 CFh	LCD display power timeout
 D0h	EL display power timeout
----------P00260027--------------------------
PORT 0026-0027 - Chips&Technologies CS4021 - "SuperState V" ALTERNATE CONFIG
Desc:	alternate copy of the configuration register access at PORT 0022h/0023h
	  which may be used by system software in "SuperState V" to configure
	  the chipset without disturbing accesses to PORT 0022h by user code
Notes:	SuperState V is an early version of system management mode
	these ports can only be accessed while the system is in SuperState V;
	  similarly, some configuration registers are read-only via PORT 0022h
	  and others can optionally be made read-only
SeeAlso: PORT 0022h"Chips&Technologies"
!!!chips\cs4021.pdf p.149

0026  -W  configuration register index
0027  RW  configuration register data
----------P0028002A--------------------------
PORT 0028-002A - 80486 "Deep Green" motherboard - ???

0028  ?W  index for data port
002A  RW  ??? data port

Note:	in order to access to the registers available through PORT 002A,
	  an unlocking sequence must be written via PORT 0028:	write
	  A0h, 05h, index to PORT 0028, then read/write PORT 002A, then
	  write A5h to PORT 0028
----------P002E002F--------------------------
PORT 002E-002F - DELL ENHANCED PARALLEL PORT
SeeAlso: PORT 015Ch,PORT 026Eh,PORT 0398h

002E  -W  index for data port (see #P0378)
002F  RW  EPP command data

(Table P0378)
Values for Dell Enhanced Parallel Port register index:
 00h	bit 0: ???
 02h	bit 7: port in bidirectional mode
 04h	bits 0 and 2: ECP/EPP mode control
----------P002E002F--------------------------
PORT 002E-002F - Intel "Nonolet" Motherboard - POWER MANAGEMENT

002E  ?W  index for data port
002F  ?W  data port

code sequence posted in fido7.nice.sources by Konstantin Mohorea:
     out 2Eh,0Ch
     out 2Fh,75h
     out 2Eh,11h
     out 2Fh,00h
     out 2Eh,0Dh
     out 2Fh,A0h
----------P002E002F--------------------------
PORT 002E-002F - NS PC87306 SuperI/O - CONFIGURATION REGISTERS
InstallCheck: after a hardware reset, the first read of the index port returns
	  88h, and a second consecutive read always returns 00h (while
	  read-after-write always returns the written value)
Range:	PORT 002Eh, PORT 015Ch, PORT 026Eh, or PORT 0398h, depending on
	  external strapping
Note:	to set a register, the data port must be written twice in a row; the
	  value is latched on the second write

002E  RW  configuration register index
002F  RW  configuration register data
----------P0038003F--------------------------
PORT 0038-003F - PC radio by CoZet Info Systems
Notes:	The I/O address range is dipswitch selectable from:
	   038-03F and 0B0-0BF
	   078-07F and 0F0-0FF
	   138-13F and 1B0-1BF
	   178-17F and 1F0-1FF
	   238-23F and 2B0-2BF
	   278-27F and 2F0-2FF
	   338-33F and 3B0-3BF
	   378-37F and 3F0-3FF
	All of these addresses show a readout of FF in initial state.
	Once started, all of the addresses show	 FB, whatever might happen.
----------P0040005F--------------------------
PORT 0040-005F - PIT - PROGRAMMABLE INTERVAL TIMER (8253, 8254)
Notes:	XT & AT use ports 40h-43h; PS/2 uses ports 40h, 42h-44h, and 47h
	the counter chip is driven with a 1.193 MHz clock (1/4 of the
	original PC's 4.77 MHz CPU clock)
SeeAlso: PORT 0044h,PORT 0048h

0040  RW  PIT  counter 0, counter divisor	      (XT, AT, PS/2)
	Used to keep the system time; the default divisor of (1)0000h
	produces the 18.2Hz clock tick.
0041  RW  PIT  counter 1, RAM refresh counter	(XT, AT)
	don't set below 3 on PCs (default 12h), and don't mess with this
	counter at all unless you really know what you're doing....
0042  RW  PIT  counter 2, cassette & speaker	(XT, AT, PS/2)
	During normal operation mode (8253) 40h-42h set the counter values on
	write and get the current counter value on read. In 16bit modes two
	consequtive writes/reads must be issued, first with the low byte,
	followed by the high byte. In 8254 read back modes, all selected
	counters and status are latched and must be read out completely
	before normal operation is valid again.	 Each counter switches back
	to normal operation after read out.  In 'get status and counter'
	mode the first byte read is the status, followed by one or two
	counter values. (see #P0379)  Note that 16-bit reads performed
	without using the "latch" command will get the current high/low
	portion of the counter at the instant of the port read, so it is
	possible for the low part of the counter to wrap around before the
	high part gets read, resulting in a significant measurement error
0043  RW  PIT  mode port, control word register for counters 0-2 (see #P0380)
	Once a control word has been written (43h), it must be followed
	immediately by performing the corresponding action to the counter
	registers (40h-42h), else the system may hang!!

Bitfields for 8254 PIT counter status byte:
Bit(s)	Description	(Table P0379)
 7	PIN status of OUTx Pins (1=high, 0=low)
 6	counter start value loaded
	=0: yes, so counter latch is valid to be read
	=1: no, wait for counter latch to be set (may last a while)
5-0	counter mode, same as bit5-0 at 43h
SeeAlso: #P0380

Bitfields for 8253/8254 PIT mode control word:
Bit(s)	Description	(Table P0380)
 7-6	counter select
	00  counter 0 select
	01  counter 1 select	  (not PS/2)
	10  counter 2 select
	11  (8253) reserved
	    (8254) read back counter (see #P0379)
---if counter select---
 5-4	counter access
	00  counter latch command
		BUG:	Intel Neptune/Mercury/Aries Chipset 8237IB (SIO) needs
			  a short delay after issuing this command, else the
			  latched MSB may be outdated with respect to the LSB,
			  resulting in large measuring errors.
			Workaround: Check for this condition by comparing
			  results with last results and don't use erroneous
			  results.
	01  read/write counter bits 0-7 only
	10  read/write counter bits 8-15 only
	11  read/write counter bits 0-7 first, then 8-15
 3-1	counter mode
	000 mode 0 select - zero detection interrupt
	001 mode 1 select - programmable one shot
	x10 mode 2 select - rate generator
	x11 mode 3 select - square wave generator
		counts down twice by two at a time; latch status and check
		  value of OUT pin to determine which half-cycle is active
		divisor factor 3 not allowed!
	100 mode 4 select - software triggered strobe
	101 mode 5 select - hardware triggered strobe
 0	counting style
	0  binary counter 16 bits
	1  BCD counter (4 decades)
---if read back---
 5-4	what to read
	00 counter status, then value
	01 counter value
	10 counter status
	11 reserved
 3	select counter 2
 2	select counter 1
 1	select counter 0
 0	reserved (0)
Note:	after issuing a read back 'get status' command, any new read back
	  command is ignored until the status is read from all selected
	  counters.
----------P00440047--------------------------
PORT 0044-0047 - Microchannel - PROGRAMMABLE INTERVAL TIMER 2
SeeAlso: PORT 0040h,PORT 0048h

0044  RW  PIT  counter 3 (PS/2)
		used as fail-safe timer. generates an NMI on time out.
		for user generated NMI see at 0462.
0047  -W  PIT  control word register counter 3 (PS/2, EISA)
	bit 7-6 = 00  counter 3 select
		= 01  reserved
		= 10  reserved
		= 11  reserved
	bit 5-4 = 00  counter latch command counter 3
		= 01  read/write counter bits 0-7 only
		= 1x  reserved
	bit 3-0 = 00
----------P0048004B--------------------------
PORT 0048-004B - EISA - PROGRAMMABLE INTERVAL TIMER 2
Note:	this second timer is also supported by many Intel chipsets
SeeAlso: PORT 0040h,PORT 0044h

0048  RW  EISA PIT2 counter 3 (Watchdog Timer)
0049  ??  EISA 8254 timer 2, not used (counter 4)
004A  RW  EISA PIT2 counter 5 (CPU speed control)
004B  -W  EISA PIT2 control word
--------K-P0060006F--------------------------
PORT 0060-006F - KEYBOARD CONTROLLER 804x (8041, 8042) (or PPI (8255) on PC,XT)
Note:	XT uses ports 60h-63h, AT uses ports 60h-64h

0060  RW  KB controller data port or keyboard input buffer (ISA, EISA)
		should only be read from after status port bit0 = 1
		should only be written to if status port bit1 = 0
0060  R-  KeyBoard or KB controller data output buffer (via PPI on XT)
		PC: input from port A of 8255, if bit7 in 61h set (see #P0396)
		get scancodes, special codes (in PC: with bit7 in 61h cleared)
		  (see #P0390)

0061  R-  KB controller port B control register (ISA, EISA)
		system control port for compatibility with 8255 (see #P0393)
0061  -W  KB controller port B (ISA, EISA)   (PS/2 port A is at 0092)
		system control port for compatibility with 8255 (see #P0392)
0061  -W  PPI Programmable Peripheral Interface 8255 (XT only)
		system control port (see #P0394)
0062  RW  PPI (XT only) data port C (see #P0395)
0063  RW  PPI (XT only) command mode register (see #P0397)

0064  R-  keyboard controller read status (see #P0398,#P0399,#P0400)
0064  -W  keyboard controller input buffer (ISA, EISA) (see #P0401)

0064  -W  (Amstrad/Schneider PC1512) set 'DIP switch S1' setting
	  stored in CMOS RAM that PPI should report for compatibility
0065  -W  (Amstrad/Schneider PC1512) set 'DIP switch S2' RAM size setting
	  stored in CMOS RAM, that PPI port C (PORT 0064h) should report for
	  compatibility

0065  R-  communications port (Olivetti M24)

Bitfields for AT keyboard controller input port:
Bit(s)	Description	(Table P0381)
 7	keyboard enabled
 6	=0  CGA, else MDA
 5	=0  manufacturing jumper installed
 4	=0  system RAM 512K, else 640K
 3-0	reserved
SeeAlso: #P0382,#P0384

Bitfields for AT keyboard controller input port (Compaq):
Bit(s)	Description	(Table P0382)
 7	security lock is unlocked
 6	=0  Compaq dual-scan display, 1=non-Compaq display
 5	system board dip switch 5 is OFF
 4	=0  auto speed selected, 1=high speed selected
 3	=0  slow (4MHz), 1 = fast (8MHz)
 2	no math coprocessor installed
 1-0	reserved
SeeAlso: #P0383

Bitfields for AT keyboard controller output port:
Bit(s)	Description	(Table P0383)
 7	keyboard data output
 6	keyboard clock output
 5	input buffer NOT full
 4	output buffer NOT empty
 3	reserved (see note)
 2	reserved (see note)
 1	gate A20
 0	system reset
Note:	bits 2 and 3 are the turbo speed switch or password lock on
	  Award/AMI/Phoenix BIOSes.  These bits make use of nonstandard
	  keyboard controller BIOS functionality to manipulate
		pin 23 (8041 port 22) as turbo switch for AWARD
		pin 35 (8041 port 15) as turbo switch/pw lock for Phoenix
SeeAlso: #P0381,#P0384

Bitfields for HP Vectra keyboard controller output port:
Bit(s)	Description	(Table P0384)
 7-5	reserved
 4	output buffer full (OBF) interrupt
 3	HP SVC interrupt
 2	HP-HIL controller AutoPoll
 1	A20 gate
 0	system reset
SeeAlso: #P0383,#P0385

Bitfields for HP Vectra command byte:
Bit(s)	Description	(Table P0385)
 7	reserved (0)
 6	scancode conversion mode (1 = PC/XT, 0 = PC/AT)
 5	unused
 4	disable keyboard (unless bit 3 set)
 3	override keyboard disable
 2	System Flag (may be read from PORT 0060h)
 1	reserved
 0	OBF interrupt enable
SeeAlso: #P0384

(Table P0386)
Values for keyboard commands (data also goes to PORT 0060h):
Value	Count	Description
 EDh	double	set/reset mode indicators Caps Num Scrl
		bit 2 = CapsLk, bit 1 = NumLk, bit 0 = ScrlLk
		all other bits must be zero.
 EEh	sngl	diagnostic echo. returns EEh.
 EFh	sngl	NOP (No OPeration). reserved for future use
 EF+26h	double	[Cherry MF2 G80-1501HAD] read 256 bytes of chipcard data
		keyboard must be disabled before this and has to
		be enabled after finished.
 F0h	double	get/set scan code set
		00h get current set
		01h scancode set 1 (PCs and PS/2 mod 30, except Type 2 ctrlr)
		02h scancode set 2 (ATs, PS/2, default)
		03h scancode set 3
 F2h	sngl	read keyboard ID (read two ID bytes)
		AT keyboards returns FA (ACK)
		MF2 returns AB 41 (translation) or
			    AB 83 (pass through)
 F3h	double	set typematic rate/delay
		format of the second byte:
		bit7=0 : reserved
		bit6-5 : typemativ delay
			 00b=250ms     10b= 750ms
			 01b=500ms     11b=1000ms
		bit4-0 : typematic rate (see #P0391)
 F4h	sngl	enable keyboard
 F5h	sngl	disable keyboard. set default parameters (no keyboard scanning)
 F6h	sngl	set default parameters
 F7h	sngl	[MCA] set all keys to typematic (scancode set 3)
 F8h	sngl	[MCA] set all keys to make/release
 F9h	sngl	[MCA] set all keys to make only
 FAh	sngl	[MCA] set all keys to typematic/make/release
 FBh	sngl	[MCA] set al keys to typematic
 FCh	double	[MCA] set specific key to make/release
 FDh	double	[MCA] set specific key to make only
 FEh	sngl	resend last scancode
 FFh	sngl	perform internal power-on reset function
Note:	each command is acknowledged by FAh (ACK), if not mentioned otherwise.
	  See PORT 0060h-R for details.
SeeAlso: #P0387

(Table P0387)
Values for Mouse functions (for PS/2-like pointing devices):
Value	Count	Description
 E6h	sngl	set mouse scaling to 1:1
 E7h	sngl	set mouse scaling to 2:1
 E8h	double	set mouse resolution
		(00h=1/mm, 01h=2/mm, 02h=4/mm, 03h=8/mm)
 E9h	sngl	get mouse information
		read two status bytes:
		  byte 0: flags (see #P0388)
		  byte 1: resolution
 EAh	sngl	set mouse to stream mode (mouse sends data on any changes)
 EBh	sngl	get mouse data (from mouse to controller) (see #P0389)
		on reading, each data packet consists of 8 bytes:
 ECh	sngl	reset mouse wrap mode (to normal mode)
 EEh	sngl	set wrap mode
 F0h	sngl	set remote mode (instead of stream mode), mouse sends data
		  only on issueing command EBh.
 F2h	sngl	read mouse ID (read one, two?? ID bytes)
		00h=mouse
 F3h	double	set mouse sample rate in reports per second
		0Ah=10/s	   50h= 80/s
		14h=20/s	   64h=100/s
		28h=40/s	   C8h=200/s
		3Ch=60/s
 F4h	sngl	enable mouse (in stream mode)
 F5h	sngl	disable mouse (in steam mode), set default parameters
 F6h	sngl	reset to defaults: 100/s, scaling 1:1, stream-mode, 4/mm,
		  disabled
 FEh	sngl	resend last mouse data (8 bytes, see EBh)
 FFh	sngl	reset mouse
Notes:	 must issue command D4h to PORT 0064h first to access mouse functions
	 all commands except ECh and FFh are acknowledged by FAh (ACK) or
	   FEh (Resend); get mouse ID (F2h) returns mouse ID.
SeeAlso: #P0386

Bitfields for mouse status byte 0:
Bit(s)	Description	(Table P0388)
 7	unused
 6	remote rather than stream mode
 5	mouse enabled
 4	scaling set to 2:1
 3	unused
 2	left button pressed
 1	unused
 0	right button pressed
SeeAlso: #P0387,#P0389

Format of mouse data packet:
Offset	Size	Description	(Table P0389)
 00h	BYTE	status
		bit7	: y-data overrun
		bit6	: x-data overrun
		bit5	: y-data negative
		bit4	: x-data negative
		bit3-2=0: reserved
		bit1	: right button pressed
		bit0	: left button pressed
 01h	BYTE	reserved
 02h	BYTE	x-data
 03h	BYTE	reserved
 04h	BYTE	y-data
 05h	BYTE	reserved
 06h	BYTE	z-data (0)
 07h	BYTE	reserved
SeeAlso: #P0387,#P0388

(Table P0390)
Values for keyboard special codes:
 00h	(MF2 in codeset2&3 or AT keyboards) keydetection/overrun error
 00h	(mouse) ID
 AAh	BAT completion code (sent after errorfree Basic Assurance Test)
 ABh	first byte of general MF2 keyboard ID
 EEh	Echo command return
 FAh	Acknowledge (all general commands except Resend and Echo)
 FAh	(mouse) Acknowledge (all commands except commands ECh,F2h,FFh)
 FCh	(MF2) BAT Failure Code (error in second half of the power on self test)
 FDh	(AT-keyboard) BAT Failure Code (error in the second half of the
	  power-on self test)
 FEh	Resend: CPU to controller should resend last keyboard-command
 FEh	(mouse) CPU to controller should resend last mouse-command
 FFh	(MF2 in codeset1) keydetection/overrun error
Note:	keyboard stops scanning and waits for next command after returning
	  code FCh or FDh
SeeAlso: PORT 0060h-R

(Table P0391)
Values for keyboard typematic rate:
 00000b=30.0   10000b=7.5
 00001b=26.7   10001b=6.7
 00010b=24.0   10010b=6.0
 00011b=21.8   10011b=5.5
 00100b=20.0   10100b=5.0
 00101b=18.5   10101b=4.6
 00110b=17.1   10110b=4.3
 00111b=16.0   10111b=4.0
 01000b=15.0   11000b=3.7
 01001b=13.3   11001b=3.3
 01010b=12.0   11010b=3.0
 01011b=10.9   11011b=2.7
 01100b=10.0   11100b=2.5
 01101b= 9.2   11101b=2.3
 01110b= 8.5   11110b=2.1
 01111b= 8.0   11111b=2.0
SeeAlso: #P0386

Bitfields for KB controller port B (system control port) [output]:
Bit(s)	Description	(Table P0392)
 7	pulse to 1 for IRQ1 reset (PC,XT)
 6-4	reserved
 3	I/O channel parity check disable
 2	RAM parity check disable
 1	speaker data enable
 0	timer 2 gate to speaker enable
SeeAlso: PORT 0061h-W,#P0393

Bitfields for KB ctrller port B control register (system control port) [input]:
Bit(s)	Description	(Table P0393)
 7	RAM parity error occurred
 6	I/O channel parity error occurred
 5	mirrors timer 2 output condition
 4	toggles with each refresh request
 3	NMI I/O channel check status
 2	NMI parity check status
 1	speaker data status
 0	timer 2 clock gate to speaker status
Note:	also supported by OPTi 82C392
SeeAlso: PORT 0061h-R,#P0392

Bitfields for Progr. Peripheral Interface (8255) system control port [output]:
Bit(s)	Description	(Table P0394)
 7	clear keyboard (only pulse, normally kept at 0)
 6	=0  hold keyboard clock low
 5	NMI I/O parity check disable
 4	NMI RAM parity check disable
 3	=0 read low nybble of switches S2
	=1 read high nybble of switches S2
 2	reserved, often used as turbo switch
	original PC: cassette motor off
 1	speaker data enable
 0	timer 2 gate to speaker enable
Note:	bits 2 and 3 are sometimes used as turbo switch
SeeAlso: PORT 0061h-W,#P00051,#P0395,#P0396,#P0397

Bitfields for PPI (XT only) data port C:
Bit(s)	Description	(Table P0395)
 7	RAM parity error occurred
 6	I/O channel parity error occurred
 5	timer 2 channel out
 4	reserved
	original PC: cassette data input
---
 3	system board RAM size type 1
 2	system board RAM size type 2
 1	coprocessor installed
 0	loop in POST
---
 3-0	DIL switch S2 high/low nybble (depending on PORT 0061h bit 3)
SeeAlso: PORT 0062h-RW,#P0394,#P0396,#P0397

Bitfields for PPI (PC,XT only) equipment switches [input]:
Bit(s)	Description	(Table P0396)
 7-6	number of disk drives
	00  1 diskette drive
	01  2 diskette drives
	10  3 diskette drives
	11  4 diskette drives
 5-4	initial video
	00  reserved (video adapter has on-board BIOS)
	01  40*25 color (mono mode)
	10  80*25 color (mono mode)
	11  MDA 80*25
 3-2	memory size (using 256K chips)
	00  256K
	01  512K
	10  576K
	11  640K
 3-2	memory size (using 64K chips)
	00  64K
	01  128K
	10  192K
	11  256K
 3-2	memory size (original PC)
	00  16K
	01  32K
	10  48K
	11  64K
 1-0	reserved
 1	NPU (math coprocessor) present
 0	boot from floppy
SeeAlso: #P0395,#P0397,PORT 0060h-R

Bitfields for PPI (8255) command mode register:
Bit(s)	Description	(Table P0397)
 7	activation function (0 = bit set/reset, 1 = mode set function)
 6,5	port A mode: 00 = mode0, 01 = mode1, 1x = mode2
 4	port A direction: 0 = output, 1 = input
 3	port C bits 7-4 direction: 0 = output, 1 = input
 2	port B mode: 0 = mode0, 1 = mode1
 1	port B direction: 0 = output, 1 = input
 0	port C bits 3-0 direction: 0 = output, 1 = input
Note:	Attention: Never write anything other than 99h to this port
	  (better: never write anything to this port, only during BIOS
	  init), as other values may connect multiple output drivers
	  and will cause hardware damage in PC/XTs!  By setting command
	  word to 99h, PPI will be set in input/output modes as it is
	  necessary to support the commonly known IO-ports 60, 61, 62
	  as desired.
SeeAlso: #P0394,#P0395,#P0396

Bitfields for keyboard controller read status (ISA, EISA):
Bit(s)	Description	(Table P0398)
 7	parity error on transmission from keyboard
 6	receive timeout
 5	transmit timeout
 4	keyboard interface inhibited by keyboard lock
 3	=1 data written to input register is command (PORT 0064h)
	=0 data written to input register is data (PORT 0060h)
 2	system flag status: 0=power up or reset	 1=selftest OK
 1	input buffer full (input 60/64 has data for 8042)
	no write access allowed until bit clears
 0	output buffer full (output 60 has data for system)
	bit is cleared after read access
SeeAlso: PORT 0064h-R,#P0399,#P0400,#P0401

Bitfields for keyboard controller read status (MCA):
Bit(s)	Description	(Table P0399)
 7	parity error on transmission from keyboard
 6	general timeout
 5	mouse output buffer full
 4	keyboard interface inhibited by keyboard lock
 3	=1 data written to input register is command (PORT 0064h)
	=0 data written to input register is data (PORT 0060h)
 2	system flag status: 0=power up or reset	 1=selftest OK
 1	input buffer full (60/64 has data for 804x)
	no write access allowed until bit clears
 0	output buffer full (output 60 has data for system)
	bit is cleared after read access
SeeAlso: #P0398,#P0400,#P0401

Bitfields for keyboard controller read status (Compaq):
Bit(s)	Description	(Table P0400)
 7	parity error detected (11-bit format only). If an
	  error is detected, a Resend command is sent to the
	  keyboard once only, as an attempt to recover.
 6	receive timeout. transmission didn't finish in 2mS.
 5	transmission timeout error
	bit 5,6,7  cause
		1 0 0  No clock
		1 1 0  Clock OK, no response
		1 0 1  Clock OK, parity error
 4	=0 security lock engaged
 3	=1 data in OUTPUT register is command
	=0 data in OUTPUT register is data
 2	system flag status: 0=power up or reset	 1=soft reset
 1	input buffer full (60/64 has data for 804x)
	no write access allowed until bit clears
 0	output buffer full (PORT 0060h has data for system)
	bit is cleared after read access
SeeAlso: #P0398,#P0399,#P0401

(Table P0401)
Values for keyboard controller commands (data goes to PORT 0060h):
Value		Description
 20h	read	read byte zero of internal RAM, this is the last KB command
		  sent to the 8041/8042
	Compaq	put current command byte on PORT 0060h (see #P0403,#P0404)
 21-3F	read	reads the byte specified in the lower 5 bits of the command
		  in the 804x's internal RAM (see #P0407)
 60-7F	double	writes the data byte to the address specified in the 5 lower
		  bits of the command
 60h	Compaq	Load new command (60 to [64], command to [60]) (see #P0404)
		(also general AT-class machines)
 A0h	AMI	get ASCIZ copyright message on PORT 0060h
 A1h	AMI	get controller version byte on PORT 0060h
 A1h	Compaq	unknown speedfunction ??
 A1h	C&T	CHIPS extensions (see #P0402)
 A2h	Compaq	unknown speedfunction ??
 A2h	AMI	set keyboard controller pins 22 and 23 low
 A2h	C&T	turn on turbo LED
 A3h	Compaq	Enable system speed control
 A3h	AMI	set keyboard controller pins 22 and 23 high
 A3h	C&T	turn off turbo LED
 A4h	MCA	check if password installed
		returns PORT 0060h code F1h if no password, FAh if installed
 A4h	Compaq	Toggle speed
 A4h	AMI	set internal system speed flag to low
 A5h	MCA	load password
		write successive scan codes to PORT 0060h, terminate with 00h
 A5h	AMI	set internal system speed flag to high
 A5h	Compaq	Special read. the 8042 places the real values of port 2
		  except for bits 4 and 5 wich are given a new definition in
		  the output buffer. No output buffer full is generated.
			if bit 5 = 0, a 9-bit keyboard is in use
			if bit 5 = 1, an 11-bit keyboard is in use
			if bit 4 = 0, output-buff-full interrupt disabled
			if bit 4 = 1, output-buffer-full interrupt enabled
 A6h	MCA	check password
 A6h	AMI	get internal system speed flag on PORT 0060h
 A6h	Compaq	unknown speedfunction ??
 A7h	MCA	disable mouse port
 A7h	AMI	set internal flag indicating bad write cache
 A8h	MCA	enable mouse port
 A8h	AMI	set internal flag indicating good write cache
 A9h	MCA	test mouse port, return test result on PORT 0060h (see #P0406)
 A9h	AMI	get internal flag indicating cache OK to PORT 0060h
 AAh	sngl	initiate self-test. will return 55h to data port if self-test
		  successful, FCh if failed
 AAh	Compaq	initializes ports 1 and 2, disables the keyboard and clears
		  the buffer pointers. It then places 55h in the output buffer.
 ABh	sngl	initiate interface test, return result value on PORT 0060h
		  (see #P0406)
 ACh	read	diagnostic dump. the contents of the 804x RAM, output port,
		  input port, status word are sent to PORT 0060h in scan-code
		  format; Chips&Technologies 8042's append "CHIPS Vxxx" where
		  "xxx" is the controller version number
 ADh	sngl	disable keyboard (sets bit 4 of commmand byte)
 ADh	Vectra	HP Vectra diagnostic dump
 AEh	sngl	enable keyboard	 (resets bit 4 of commmand byte)
 AFh	AWARD	Enhanced Command: read keyboard version
 AFh	AMI	set extended controller RAM
		write address to PORT 0060h, wait for controller ready, then
		  write value to PORT 0060h
 B1h	AMI	set keyboard controller P11 line low
 B2h	AMI	set keyboard controller P12 line low
 B3h	AMI	set keyboard controller P13 line low
 B4h	AMI	set keyboard controller P22 line low
 B5h	AMI	set keyboard controller P23 line low
 B8h	AMI	set keyboard controller P10 line high
 B9h	AMI	set keyboard controller P11 line high
 BAh	AMI	set keyboard controller P12 line high
 BBh	AMI	set keyboard controller P13 line high
 BCh	AMI	set keyboard controller P22 line high
 BDh	AMI	set keyboard controller P23 line high
 C0h	read	read input port and place on PORT 0060h
		bit 7	keyboard NOT locked
		bit 6	=0 first video is CGA
			=1 first video is MDA
		bit 5	=0 factory testmode
			=1 normal
		bit 4	=0 256KB RAM, 1=512KB
		bit 5,3-0 are used in Intel chipset 386sx machines with
			AMI/Phoenix BIOSes for BIOS specific hardware settings
		bit 2	(MCA) no keyboard power
		bit 1	(MCA) current mouse serial data input state
		bit 0	(MCA) current keyboard serial input state
 C0h	Compaq	places status of input port in output buffer.  Use this
		  command only when the output buffer is empty
 C1h	MCA	Enhanced Command: poll input port Low nibble, continuously
		  place in PORT 0064h bits 7-4 until next command
 C2h	MCA	Enhanced Command: poll input port High nibble, continuously
		  place in PORT 0064h bits 7-4 until next command
 C8h	AMI	unblock keyboard controller lines P22 and P23
 C9h	AMI	block keyboard controller lines P22 and P23
 CAh	AMI	read keyboard mode, return in 0060 bit 0
		  (bit clear if ISA mode, set if PS/2 mode)
 CBh	AMI	set keyboard mode (write back mode byte returned by CAh,
		  modifying only bit 0)
 CCh	AMI	??? (used by AMI BIOS v1.00.12.AX1T APM code)
 D0h	read	read output port and place on PORT 0060h (see #P0405)
 D0h	Compaq	places byte in output port in output buffer. Use this command
		  only when the output buffer is empty
 D1h	double	write output port.  The next byte written to PORT 0060h will
		  be written to the 804x output port; the original IBM AT and
		  many compatibles such as the OPTi 82C392 use bit 1 of the
		  output port to control the A20 gate.
		Important: bit 0 (system reset) should always be set here, as
			  the system may hang constantly; use pulse output port
			  (FEh) instead.
 D1h	Compaq	the system speed bits are not set by this command use
		  commands A1-A6 (!) for speed functions.
 D2h	MCA	Enhanced Command: write keyboard output buffer
 D3h	MCA	Enhanced Command: write pointing device out.buf.
 D4h	MCA	write to mouse/pointing device instead of to keyboard; this
		  controller command must precede every PORT 0060h command
		  directed to the mouse, otherwise it will be sent to the
		  keyboard
 D4h	AWARD	Enhanced Command: write to auxiliary device
 DDh	sngl	disable address line A20 (HP Vectra only???)
		default in Real Mode
 DFh	sngl	enable address line A20 (HP Vectra only???)
 E0h	read	read test inputs, and place in PORT 0060h
		bit0 = kbd clock, bit1 = kbd data
 Exxx	AWARD	Enhanced Command: active output port
 E5h	GoldStar set turbo LED color to yellow (turbo off)
 E7h	GoldStar set turbo LED color to yellow (turbo off)
 E8h	GoldStar set turbo LED color to green (turbo on)
 EAh	GoldStar set turbo LED color to green (turbo on)
 EDh	double	this is a two part command to control the state of the
		  NumLock, CpasLock and ScrollLock LEDs
		The second byte contains the state to set LEDs.
		    bit 7-3	reserved. should be set to 0.
		    bit 2 = 0	Caps Lock LED off
		    bit 1 = 0	Num Lock LED off
		    bit 0 = 0	Scroll Lock LED off
 F0-FF	sngl	pulse output port low for 6 microseconds.
		bits 0-3 contain the mask for the bits to be pulsed.  A bit is
		  pulsed if its mask bit is zero
		bit0=system reset. Don't set to zero. Pulse only!
Note:	 keyboard controllers are widely different from each other.  You
	   cannot generally exchange them between different machines.
	 (Award) Derived from Award's Enhanced KB controller advertising sheet.
	 (Compaq) Derived from the Compaq Deskpro 386 Tech. Ref. Guide.

(Table P0402)
Values for Chips&Technologies extension commands:
 00h	return ID - returns A6h for a C&T controller, part # N93N8042/A
 02h	write input port
	next data byte to PORT 0060h is written to the controller's input port
	Warning: the system must be designed to support output devices
		  connected to the input port to avoid potential damage
 04h	select turbo switch input
	next byte selects input:
	    bit 7: switch polarity
		(=0 input low = high speed, =1 input low = low speed)
	    bits 6-0: one bit set selects corresponding bit in Port1 as turbo
 05h	select turbo LED output
	next byte selects output:
	    bit 7: LED polarity	(=0 output low=LED on, =1 output low=LED off)
	    bit 6: LED port (=0 Port1, =1 Port2)
	    bits 5-0: one bit set selects corresponding bit in Port1/Port2 as
		LED output
Note:	these commands and any arguments are sent to PORT 0060h after writing
	  command A1h to PORT 0064h
SeeAlso: #P0401

Bitfields for Compaq keyboard command byte:
Bit(s)	Description	(Table P0403)
 7	reserved
 6	=1 convert KB codes to 8086 scan codes
 5	=0 use 11-bit codes, 1=use 8086 codes
 4	=0 enable keyboard, 1=disable keyboard
 3	ignore security lock state
 2	this bit goes into bit2 status reg.
 1	reserved (0)
 0	generate interrupt (IRQ1) when output buffer full
SeeAlso: #P0404

Bitfields for keyboard command byte (alternate description):
Bit(s)	Description	(Table P0404)
 7	reserved (0)
 6	IBM PC compatibility mode
 5	IBM PC mode
	no parity, no stop bits, no translation
	(PS/2) force mouse clock low
 4	disable keyboard (clock)
 3	(AT) inhibit override -- ignore keyboard lock switch
	(PS/2) reserved
 2	system flag
 1	(AT) reserved (0)
	(PS/2) enable mouse output buffer full interrupt (IRQ12)
 0	enable output buffer full interrupt (IRQ1)
SeeAlso: #P0403,#P0405

Bitfields for keyboard controller output port:
Bit(s)	Description	(Table P0405)
 7	keyboard data (output)
 6	keyboard clock (output)
 5	(AT) =0 input buffer empty
	(MCA) outptu buffer full with mouse byte (connected to IRQ12)
 4	output buffer full with keyboard byte (connected to IRQ1)
 3	(MCA) mouse data (output)
 2	(MCA) mouse clock (output)
	used by Intel 386sx Chipset with AMI/Phoenix BIOSes for BIOS-specific
	  configuration of turbo switch
 1	gate address A20
 0	system reset
Note:	bit 0 (system reset) should always be set when writing the output
	  port, as the system may hang constantly; use pulse output port
	  (command FEh) instead.
SeeAlso: #P0404

(Table P0406)
Values for keyboard/mouse test result on PORT 0060h:
 00h	no error
 01h	keyboard clock line stuck low
 02h	keyboard clock line stuck high
 03h	keyboard data line is stuck low
 04h	keyboard data line stuck high
 05h	(Compaq only) diagnostic feature
SeeAlso: #P0401

(Table P0407)
Values for keyboard controller RAM location:
 00h	command byte (see #P0403,#P0404)
---MCA systems---
 13h	security on
	nonzero if password enabled
 14h	security off
	nonzero if password matched
 16h	password discard scancode 1
 17h	password discard scancode 2
Note:	make codes matching either discard scancode are ignored during password
	  entry
----------P0065------------------------------
PORT 0065 - AT&T 6300+ - HIGH/LOW CHIP SELECT
----------P0065------------------------------
PORT 0065 - ???

0065  RW  ???
		bit 2: A20 gate control (set = A20 enabled, clear = disabled)
----------P00660067--------------------------
PORT 0066-0067 - AT&T 6300+ - SYSTEM CONFIGURATION SWITCHES
----------P0066------------------------------
PORT 0066 - IBM 4717 Magnetic Stripe Reader - ???
SeeAlso: PORT 0069h"Magnetic Stripe"
----------P0068------------------------------
PORT 0068 - C&T CHIPSETS - TURBO MODE CONTROL

Note:	  on Micronics 386-25/386-33/486-25 motherboards, setting this port to
	    00h enables full speed; setting it to C0h slows the system down by
	    a factor corresponding to the value programmed into the EISA
	    interval timer 2 at ports 004Ah and 004Bh
--------K-P0068006F--------------------------
PORT 0068-006F - HP Vectra Human Interface Link
SeeAlso: PORT 0060h"KEYBOARD"

0068  -W  (HP-Vectra) control buffer (HP commands) (see #P0408)
0069  R-  (HP-Vectra) SVC (keyboard request SerViCe port)
006A  -W  (HP-Vectra) Acknowledge (clear processing, done)
006C-006F	HP-HIL	(Human Interface Link = async. serial inputs 0-7)

(Table P0408)
Values for HP Vectra control buffer command code:
 00h-54h insert standard key make code into 8041 scancode buf
 55h-77h insert HP key make code into 8041 scancode buffer
 7Ah	pass through next data byte
 7Bh	set RAM Switch to 0
 7Ch	set RAM Switch to 1 (default)
 7Dh	set CRT Switch to 0
 7Eh	set CRT Switch to 1 (default)
 7Fh	reserved
 80h-D4h insert standard key break code into scancode buffer
 D5h-F7h insert HP key break code into scancode buffer
 F8h	enable AutoPoll
 F9h	disable AutoPoll
 FAh-FEh reserved
 FFh	keyboard overrun
----------P0069------------------------------
PORT 0069 - IBM 4717 Magnetic Stripe Reader - ???
SeeAlso: PORT 0066h"Magnetic Stripe"
----------P006B006F--------------------------
PORT 006B-006F - SSGA CONTROL REGISTERS

006B  ??  RAM enable/remap
006C  ??  undocumented
006D  ??  undocumented
006E  ??  undocumented
006F  ??  undocumented
----------P0070007F--------------------------
PORT 0070-007F - CMOS RAM/RTC (REAL TIME CLOCK)
Note:	the real-time clock may be either a discrete MC146814, MC146818, or
	  an emulation thereof built into the motherboard chipset
SeeAlso: PORT 00A0h"XT"

0070  -W  CMOS RAM index register port (ISA, EISA)
		 bit 7	= 1  NMI disabled from reaching CPU
			= 0  NMI enabled
		 bit 6-0     CMOS RAM index
			(64 bytes in early systems, now usually 128 bytes)
	Note:	any write to PORT 0070h should be followed by an action to
		  PORT 0071h or the RTC wil be left in an unknown state.
0071  RW  CMOS RAM data port (ISA, EISA) (see #P0409)

(Table P0409)
Values for Real-Time Clock register number (see also CMOS.LST):
 00h-0Dh clock registers
 0Eh	diagnostics status byte
 0Fh	shutdown status byte
 10h	diskette drive type for A: and B:
 11h	reserved / IBM fixed disk / setup options
 12h	fixed disk drive type for drive 0 and drive 1
 13h	reserved / AMI Extended CMOS setup (AMI Hi-Flex BIOS)
 14h	equipment byte
 15h	LSB of system base memory in Kb
 16h	MSB of system base memory in Kb
 17h	LSB of total extended memory in Kb
 18h	MSB of total extended memory in Kb
 19h	drive C extension byte
 1Ah	drive D extension byte
 1Bh-2Dh reserved
 20h-27h commonly used for first user-configurable drive type
 2Eh	CMOS MSB checksum over 10-2D
 2Fh	CMOS LSB checksum over 10-2D
 30h	LSB of extended memory found above 1Mb at POST
 31h	MSB of extended memory found above 1Mb at POST
 32h	date century in BCD
 33h	information flags
 34h-3Fh	reserved
 35h-3Ch commonly used for second user-configurable drive type
 3Dh-3Eh word to 82335 MCR memory config register at [22] (Phoenix)
 42h-4Ch AMI 1990 Hyundai super-NB368S notebook
	???
 54h-57h AMI 1990 Hyundai super-NB368S notebook
	???
 5Ch-5Dh AMI 1990 Hyundai super-NB368S notebook
	???
 60h-61h AMI 1990 Hyundai super-NB368S notebook
	???
----------P0072------------------------------
PORT 0072 - Chips&Technologies 82C100 - NMI CONTROL

!!!chips\82c100.pdf p.41
----------P00720075--------------------------
PORT 0072-0075 - AMD-645 Peripheral Bus Controller - ACCESS TO EXTENDED CMOS
SeeAlso: PORT 0070h

0072  RW  CMOS memory address, region 2 (256 bytes)
0073  RW  CMOS memory data, region 2
0074  RW  CMOS memory address, region 3 (256 bytes)
0075  RW  CMOS memory data, region 3
Note:	on the AMD-645, ports 0072h and 0073h allow access to a full 256 bytes
	  of RAM, including the standard 128 bytes available through ports
	  0070h and 0071h
----------P0073------------------------------
PORT 0073 - Intel 82378IB ("Saturn"/"Neptune" chipsets) - MBOARD CONFIGURATION
SeeAlso: PORT 0075h

0073  RW  ???
	bit 7: ???
	bit 6: disable ROM shadowing
	bit 5: ??? (related to IDE controller)
	bit 4: ???
	bit 3: ???
----------P00740076--------------------------
PORT 0074-0076 - SECONDARY CMOS (Compaq), NVRAM (IBM) ACCESS
Note:	NVRAM may be 2K, 8K, or 16K
SeeAlso: PORT 0070h-007Fh,CMOS.LST

0074  -W  secondary CMOS RAM (IBM NVRAM) index, low byte
0075  -W  secondary CMOS RAM (IBM NVRAM) index, high (in bits 2-0)
0076  RW  secondary CMOS RAM (IBM NVRAM) data byte
----------P0075------------------------------
PORT 0075 - Intel 82378IB ("Saturn"/"Neptune" chipsets) - MBOARD CONFIGURATION
SeeAlso: PORT 0073h,PORT 0078h"82378IB"

0075  R-  ???
	  bits 3-2: external bus speed
	       00  50 MHz
	       01  66 MHz
	       10  60 MHz
	       11  40 MHz
----------P0078------------------------------
PORT 0078 - HP-Vectra - HARD RESET: NMI ENABLE/DISABLE

0078  ?W  NMI enable/disable
		bit 7 = 0  disable & clear hard reset from HP-HIL controller
		      = 1  enable hard reset from HP-HIL controller chip
		bit 6-0	   reserved
----------P0078------------------------------
PORT 0078 - Intel 82378IB ("Saturn"/"Neptune" chipsets) - BIOS COUNT-DOWN TIMER
Notes:	the BIOS uses this port for certain fine timings; presumably it is
	  independent of processor speed (it appears to decrement at 1 MHz)
	the address at which this port appears may be set via the 82378's
	  PCI configuration space word at offset 0080h (see #01064), or the
	  timer may be disabled entirely
SeeAlso: PORT 0075h

0078w -W  set count-down timer
0078w R-  get current count (timer stops when it reaches 0000h)
----------P0078007F--------------------------
PORT 0078-007F - PC radio by CoZet Info Systems
Range:	The I/O address range is dipswitch selectable from:
	   038-03F and 0B0-0BF
	   078-07F and 0F0-0FF
	   138-13F and 1B0-1BF
	   178-17F and 1F0-1FF
	   238-23F and 2B0-2BF
	   278-27F and 2F0-2FF
	   338-33F and 3B0-3BF
	   378-37F and 3F0-3FF
Note:	All of these addresses show a readout of FFh in initial state.
	Once started, all of the addresses show FBh, whatever might happen.
----------P007C007D--------------------------
PORT 007C-007D - HP-Vectra - PIC 3 - PROGRAMMABLE INTERRUPT CONTROLLER (8259)
Notes:	cascaded to first controller.
	used for keyboard and input device interface.
SeeAlso: PORT 0020h-0021h,INT 68"Vectra",INT 6E"Vectra"

007C  RW  HP-Vectra  PIC 3  see at 0020	 PIC 1
007D  RW  HP-Vectra  PIC 3  see at 0021	 PIC 1
----------P007E------------------------------
PORT 007E - Chips&Technologies 82C100/110 - NMI STATUS
SeeAlso: PORT 0072h"82C100",PORT 007Fh"82C100"
!!!chips\82c100.pdf p.42
!!!chips\82c110.pdf p.39
----------P007F------------------------------
PORT 007F - Chips&Technologies 82C100/110 - POWER CONTROL AND RESET
SeeAlso: PORT 0072h"82C100",PORT 007Eh"82C100"
----------P0080------------------------------
PORT 0080 - MANUFACTURING DIAGNOSTICS PORT
Note:	sometimes used for a POST hex display

0080  -W  Manufacturing Diagnostics port
0080  R-  ???

(Table P0410)
Values for AMI BIOS diagnostics codes:
 00h	system boot completed, control passed to INT 19 bootstrap loader
 01h	register test
 02h	video initialization; NMIs disabled
 03h	power-on delay complete
 04h	pre-keyboard-test initializations complete
 05h	soft-reset/power-on setting determined
 06h	ROM enabled
 07h	ROM BIOS checksum test passed
 08h	keyboard BAT command issued
 09h	keyboard controller BAT result verified
 0Ah	keyboard controller command code issued
 0Bh	keyboard controller command byte written
 0Ch	keyboard controller pins 23/24 blocked and unblocked
 0Dh	keyboard controller NOP processing in progress
 0Eh	CMOS RAM shutdown register read/write test passed
 0Fh	CMOS RAM checksum calculation complete
 10h	CMOS RAM initialization complete
 11h	CMOS RAM status register initialized
 12h	DMA controllers 1/2 and interrupt controllers 1/2 disabled
 13h	video display disabled, port B initialized
 14h	chipset initialization, auto memory detection
 15h	8254 channel 2 test half complete
 16h	8254 channel 2 test completed
 17h	8254 channel 1 test completed
 18h	8254 channel 0 test completed
 19h	memory refresh started
 1Ah	memory refresh line is toggling
 1Bh	memory refresh test completed
 20h	base 64K memory test started
 21h	address line test passed
 22h	parity toggle complete
 23h	base 64K sequential read/write test passed
 24h	pre-interrupt-vector-initialization configuration complete
 25h	interrupt vectors initialized
 26h	8042 input port read
 27h	global data initialization complete
 28h	post-interrupt-vector-initialization initialization complete
 29h	monochrome mode set
 2Ah	color mode set
 2Bh	parity toggle on option video ROM test complete
 2Ch	initialization before video ROM control complete
 2Dh	video ROM check complete
 2Eh	!!!
 A9h	returned from E0000h adapter ROM
 AAh	final initializations after adapter ROM initializations complete
SeeAlso: #P0411,#P0412,#P0413

(Table P0411)
Values for AWARD (non-PnP) diagnostic code:
 01h	Processor Test 1
 02h	Processor Test 2
 03h	initialize chips
 04h	test memory refresh toggle
 05h	blank video, initialize keyboard
 06h	reserved
 07h	test CMOS and CMOS batter status
 08h	setup low memory
 09h	early cache initialization
 0Ah	interrupt vector initialization
 0Bh	test CMOS RAM checksum
 0Ch	initialize keyboard
 0Dh	initialize video interface
 0Eh	test video memory
 0Fh	test DMA channel 0
 10h	test DMA channel 1
 11h	test DMA page registers
 12h	reserved
 13h	reserved
 14h	test timer channel 2
 15h	test master PIC mask bits
 16h	test slave PIC mask bits
 17h	test 8259 stuck interrupt bits
 18h	test 8259 interrupt functionality
 19h	test for stuck NMI
 1Ah	display CPU clock
 1Bh-1Eh reserved
 1Fh	set EISA mode
 20h	enable Slot 0 (system board)
 21h-2Fh enable Slots 1-15
 30h	get base and extended memory size
 31h	test base and extended memory
 32h	test EISA memory
 33h-3Bh reserved
 3Ch	set allow-setup flag
 3Dh	initialize / install mouse
 3Eh	initialize cache controller
 3Fh	reserved
 41h	initialize floppy controller and drives
 42h	initialize hard disk controller and drives
 43h	detect / initialize serial and parallel ports
 44h	reserved
 45h	initialize math coprocessor
 46h-4Dh reserved
 4Eh	Manufacturing Post loop / or / display any error messages
 4Fh	ask for password, if enabled
 50h	update CMOS RAM
 51h	pre-boot enable of parity, NMI, cache
 52h	initialize option ROMs
 53h	initialize BIOS time from RTC
 60h	setup boot-sector protection
 61h	set boot CPU speed
 62h	setup NumLock
 63h	attempt to boot via INT 19h
 B0h	spurious interrupt while in protected mode
 B1h	unclaimed NMI
 BEh	chipset default initialization
 BFh	chipset initialization
 C0h	turn off chipset cache
 C1h	check on-board memory size
 C5h	early shadow-RAM enable for faster boot
 C6h	detect external cache size
 E1h-EFh setup utility pages 1-15
 FFh	system booting operating system
SeeAlso: #P0410,#P0412,#P0413

(Table P0412)
Values for AWARD (Plug-and-Play) POST code:
 01h-02h reserved
 03h	initialize EISA register (if applicable)
 04h	reserved
 05h	keyboard controller test, initialize keyboard
 06h	reserved
 07h	test CMOS and CMOS batter status
 09h	program Cyrix CPU configuration; OEM-specific cache initialization
 0Ah	initialize interrupt vectors; early power management initialization
 0Bh	check CMOS RAM; assign I/O and memory to PCI devices
 0Ch	initialize BIOS data area
 0Dh	early chipset setup; measure CPU speed; video initialization
 0Eh	display Award logo, OEM-specific sign-on messages
 0Fh	test DMA channel 0
 10h	test DMA channel 1
 11h	test DMA page registers
 12h-13h reserved
 14h	test timer channel 2
 15h	test master PIC mask bits
 16h	test slave PIC mask bits
 17h	reserved
 19h	test 8259 functionality
 1Ah-1Dh reserved
 1Eh	EISA initialization (if applicable and EISA NVRAM checksum is good)
 1Fh-29h reserved
 30h	get base and extended memory size
 31h	test base and extended memory
 32h	program on-board serial/parallel ports, floppy controller
 33h-3Bh reserved
 3Ch	set allow-setup flag
 3Dh	initialize keyboard, install PS/2 mouse if attached
 3Eh	try to turn on L2 cache
 3Fh-40h reserved
 41h	initialize floppy controller, drives
 42h	initialize hard disk controller, drives
 43h	initialize serial/parallel ports (if PnP)
 44h	reserved
 45h	initialize math coprocessor
 46h-4Dh reserved
 4Eh	display any error messages
 4Fh	ask for password, if required
 50h	update CMOS RAM
 51h	reserved
 52h	initialize expansion ROMs, PCI, PnP, shadow RAM, power management
 53h	if not PnP, initialize serial/parallel ports; set BIOS time
 54h-5Fh reserved
 60h	set boot-sector protection
 61h	turn on L2 cache; set boot speed; final chipset/PM initialization
 62h	setup daylight savings time; set NumLock, typematic
 63h	update ESCD (PnP only) if changes; boot system via INT 19h
 B0h	spurious interrupt while in protected mode
 B1h	unclaimed NMI
 BEh	chipset default initialization
 BFh	chipset initialization
 C0h	turn off chipset cache, init DMA/PIC/timer/RTC with default values
 C1h	check on-board DRAM and cache size
 C3h	test first 256K DRAM, expand compressed BIOS image into DRAM
 C5h	early shadow-RAM enable for faster boot
 FFh	system is booting operating system
SeeAlso: #P0410,#P0411,#P0413

(Table P0413)
Values for Chips&Technologies 82C100/82C235 POST code:
 01h	flags register failed
 02h	a CPU register failed
 03h	incorrect ROM checksum
 04h	DMA controller failed
 05h	system timer failed
 06h	first 64K of RAM failed address test
 07h	first 64K of RAM failed RAM test
 08h	interrupt controller failed
 09h	"Hot Interrupt" occurred
 0Ah	reserved
 0Bh	CPU still in protected mode
 0Ch	DMA page register failed
 0Dh	no RAM refresh
 0Eh	no response from keyboard controller
 0Fh	unable to enter protected mode
 10h	GDT or IDT register failed
 11h	LDT register failed
 12h	task register failed
 13h	LSL instruction failed
 14h	LAR instruction failed
 15h	VERR or VERW instruction failed
 16h	keyboard controller A20 gate failed
 17h	exception failed, or shutduwon on unexpected exception
 18h	shutdown during memory test
 19h	checksum error in copyright string
 1Ah	BMS checksum error
---POST progress codes---
 50h	initialize hardware
 51h	initialize timer
 52h	initialize DMA controller
 53h	initialize 8259
 54h	initialize chipset
 55h	reserved
 56h	first entry into protected mode
 57h	memory-chip sizing
 58h	reserved
 59h	first exit from protected mode
 5Ah	system-board memory size determination
 5Bh	shadow RAM relocation
 5Ch	configure possible EMS
 5Dh	reserved
 5Eh	re-test lowest 64K of RAM
 5Fh	test shadow RAM
 60h	test CMOS RAM
 61h	test video
 63h	test protected mode interrupts
 64h	test A20
 65h	memory address line tests
 66h	test base memory
 67h	test extended memory
 68h	test timer interrupt
 69h	test real-time clock
 6Ah	test keyboard controller
 6Bh	test 80287
 6Ch	test RS232
 6Dh	test parallel port
 6Eh	reserved
 6Fh	test floppy disk controller
 70h	test fixed disk controller
 71h	test keylock
 72h	test mouse / pointing device
 73h-8Fh reserved
 90h	setup RAM
 91h	determine CPU speed
 92h	configuration check
 93h	initialize BIOS
 94h	POD bootstrap
 95h	reset ICs
 96h	setup cache controller
SeeAlso: #P0410,#P0411,#P0412

(Table P0414)
Values for Intel SE440BX ("Seattle") motherboard POST codes:
 02h	verify real mode
 03h	disable NMI
 04h	CPU type determination
 06h	system hardware initialization
 08h	chipset initialization (initial POST values)
 09h	set IN-POST flag
 0Ah	CPU register initialization
 0Bh	enable CPU cache
 0Ch	cache initialization (initial POST values)
 0Eh	I/O component initialization
 0Fh	local-bus IDE initialization
 10h	power management initialization
 11h	load alternate rgisters with initial POST values
 12h	warm boot: restore CPU control word
 13h	PCI bus-mastering device initialization
 14h	keyboard controller initialization
 16h	checksum BIOS ROM
 17h	cache initialization (before memory autosizing)
 18h	initialize 8254 timer
 1Ah	8237 DMA controller initialization
 1Ch	programmable interrupt controller reset
 20h	DRAM refresh test
 22h	keyboard controller test
 24h	ES register set to 4G flat
 26h	A20 enabled
 28h	DRAM autosizing
 29h	POST memory manager initialization
 2Ah	512K base RAM cleared
 2Ch	RAM failure on address line xxxx
 2Eh	RAM failure on data bits xxxx of memory bus low byte
 2Fh	cache enabled before system BIOS shadowing
 30h	RAM failure on data bits xxxx of memory bus high byte
 32h	CPU bus-clock frequency test
 33h	POST dispatch manager initialization
 34h	CMOS RAM test
 35h	alternate chipset register initialization
 36h	warm start shutdown
 37h	chipset reinitialization (motherboard)
 38h	system BIOS ROM shadowing
 39h	cache reinitialization (motherboard)
 3Ah	cache autosizing
 3Ch	advanced chipset register configuration
 3Dh	load alternate registers with CMOS values
 40h	initial CPU speed set
 42h	interrupt vector initialization
 44h	BIOS interrupt initialization
 45h	POST device initialization
 46h	ROM copyright notice check
 47h	PCI option ROM manager initialization
 48h	check video configuration against CMOS RAM data
 49h	PCI bus and device initialization
 4Ah	video adapter initialization
 4Bh	display QuietBoot screen
 4Ch	vidoe BIOS ROM shadowing
 4Eh	display BIOS copyright notice
 50h	display CPU type and speed
 51h	EISA motherboard initialization
 52h	keyboard test
 54h	set key click (if enabled)
 56h	enable keyboard
 58h	test for unexpected interrupts
 59h	POST display service initialization
 5Ah	display prompt "Press F2 to enter SETUP"
 5Bh	disable CPU cache
 5Ch	RAM test (512K-640K)
 60h	extended memory test
 62h	extended memory address line test
 64h	jump to UserPatch1
 66h	advanced cache register configuration
 67h	multiprocessor APIC initialization
 68h	enable L1 and L2 caches
 69h	SMM area setup
 6Ah	display L2 cache size
 6Ch	display	shadow-area message
 6Eh	display possible UMB recovery high address
 70h	display error messages
 72h	configuration error check
 74h	real-time clock test
 76h	keyboard-error check
 7Ah	test for key lock on
 7Ch	hardware interrupt vector setup
 7Eh	coprocessor initialization (if present)
 80h	disable onboard SuperI/O ports and IRQs
 81h	late POST device initialization
 82h	detect/install external serial ports
 83h	non-MCD IDE controller configuration
 84h	detect/install external parallel ports
 85h	PC-compatible PnP ISA device initialization
 86h	onboard I/O port reinitialization
 87h	configure motherboard configurable devices
 88h	BIOS data area initialization
 89h	enable NMI
 8Ah	extended BIOS data area initialization
 8Bh	test/initialize PS/2 mouse
 8Ch	diskette controller initialization
 8Fh	determine number of ATA drives
 90h	hard-disk controller initialization
 91h	local-bus hard-disk controller initialization
 92h	jump to UserPatch2
 93h	build MPTABLE for multiprocessor boards
 94h	disable A20 (Release 5.1 and earlier)
 95h	install CD-ROM for boot
 96h	clear ES 4G segment register
 97h	multiprocessor table fixup
 98h	option ROM search
 99h	check for SMART drive
 9Ah	option ROM shadowing
 9Ch	power management setup
 9Eh	enable hardware interrupts
 9Fh	determine number of ATA and SCSI devices
 A0h	set time of day
 A2h	check key lock
 A4h	typematic rate initialization
 A8h	erase F2 prompt
 AAh	test for F2 keystroke
 ACh	enter SETUP
 AEh	clear IN-POST flag
 B0h	check for errors
 B2h	preparing to boot OS - POST complete
 B4h	short beep before booting
 B5h	terminate QuietBoot
 B6h	password check (optional)
 B8h	clear global descriptor table
 B9h	clean up all graphics
 BAh	DMI parameter initialization
 BBh	PnP option ROM initialization
 BCh	clear parity checkers
 BDh	display MultiBoot menu
 BEh	clear screen (optional)
 BFh	check virus and backup reminders
 C0h	INT 19 boot attempt
 C1h	POST Error Manager (PEM) initialization
 C2h	error logging initialization
 C3h	error display function initialization
 C4h	system error handler initialization
 E0h	chipset initialization
 E1h	bridge initialization
 E2h	processor initialization
 E3h	system timer initialization
 E4h	system I/O initialization
 E5h	check force recovery boot
 E6h	BIOS ROM checksumming
 E7h	go to BIOS
 E8h	set huge segment
 E9h	multiprocessor initialization
 EAh	OEM special code initialization
 EBh	PIC and DMA initialization
 ECh	memory type initialization
 EDh	memory size initialization
 EEh	boot block shadowing
 EFh	system memory test
 F0h	interrupt vector initialization
 F1h	real-time clock initialization
 F2h	video initialization
 F3h	beeper initialization
 F4h	initialize boot
 F5h	clear huge segment
 F6h	boot to mini-DOS
 F7h	boot to full DOS
----------P0080008F--------------------------
PORT 0080-008F - DMA PAGE REGISTERS (74612)

0080  RW  extra page register (temporary storage)
0081  RW  DMA channel 2 address byte 2
0082  RW  DMA channel 3 address byte 2
0083  RW  DMA channel 1 address byte 2
0084  RW  extra page register
0085  RW  extra page register
0086  RW  extra page register
0087  RW  DMA channel 0 address byte 2
0088  RW  extra page register
0089  RW  DMA channel 6 address byte 2
008A  RW  DMA channel 7 address byte 2
008B  RW  DMA channel 5 address byte 2
008C  RW  extra page register
008D  RW  extra page register
008E  RW  extra page register
008F  RW  DMA refresh page register
----------P0080009F--------------------------
PORT 0080-009F - Intel386sx CHIPSET 82231
Note:	includes the DMA controller functionality on PORT 0080h to PORT 008Fh
----------P0084------------------------------
PORT 0084 - Compaq POST Diagnostic
--------X-P0084------------------------------
PORT 0084 - EISA - SYNCHRONIZE BUS CYCLE
----------P00850086--------------------------
PORT 0085-0086 - Intel "Triton" chipset - ???
SeeAlso: PORT 00EBh"Triton"

0085  ?W  ???
0086  ?W  ???
----------P0090009F--------------------------
PORT 0090-009F - PS/2 - POS (PROGRAMMABLE OPTION SELECT)

0090  ??  Central arbitration control port
0090  RW  POST diagnostic code (most PS/2 with ISA bus)
0091  R-  Card selection feedback
	    bit 0 set when adapter addressed and responds, cleared on read
0092  RW  PS/2 system control port A  (port B is at PORT 0061h) (see #P0415)
0094  -W  system board enable/setup register (see #P0416)
0095  --  reserved
0096  -W  adapter enable / setup register (see #P0417)
0097  --  reserved

Bitfields for PS/2 system control port A:
Bit(s)	Description	(Table P0415)
 7-6	any bit set to 1 turns activity light on
 5	unused
 4	watchdog timout occurred
 3	=0 RTC/CMOS security lock (on password area) unlocked
	=1 CMOS locked (done by POST)
 2	unused
 1	A20 is active
 0	=0 system reset or write
	=1 pulse alternate reset pin (high-speed alternate CPU reset)
Notes:	once set, bit 3 may only be cleared by a power-on reset
	on at least the C&T 82C235, bit 0 remains set through a CPU reset to
	  allow the BIOS to determine the reset method
SeeAlso: #P0416,#P0417,MSR 00001000h

Bitfields for PS/2 system board enable/setup register:
Bit(s)	Description	(Table P0416)
 7	=1  enable functions
	=0  setup functions
 5	=1  enables VGA
	=0  setup VGA
 2	=1  enable integrated SCSI (PS/2 M77)
	=0  setup integrated SCSI
SeeAlso: #P0415,#P0417

Bitfields for PS/2 adapter enable/setup register:
Bit(s)	Description	(Table P0417)
 7	activate Channel Reset on all slots
 6-4	unused (1)
 3	=1  setup adapter specified by bits 2-0
	=0  enable registers
 2-0	adapter slot select (000 = slot 1 ... 111 = slot 8)
SeeAlso: #P0416
----------P00A000AF--------------------------
PORT 00A0-00AF - PIC 2 - PROGRAMMABLE INTERRUPT CONTROLLER (8259A)
SeeAlso: PORT 0020h-003Fh"PIC 1",INT 70"IRQ8",INT 77"IRQ15"

00A0  RW  PIC 2	 same as 0020 for PIC 1
00A1  RW  PIC 2	 same as 0021 for PIC 1 except for OCW1 (see #P0418)

Bitfields for PIC2 output control word OCW1:
Bit(s)	Description	(Table P0418)
 7	disable IRQ15 (reserved)
 6	disable IRQ14 (fixed disk interrupt)
 5	disable IRQ13 (coprocessor exception interrupt)
 4	disable IRQ12 (mouse interrupt)
 3	disable IRQ11 (reserved)
 2	disable IRQ10 (reserved)
 1	disable IRQ9  (redirect cascade)
 0	disable IRQ8  (real-time clock interrupt)
SeeAlso: #P0014
----------P00A0------------------------------
PORT 00A0 - XT - NMI MASK REGISTER
SeeAlso: PORT 0070h,INT 02

00A0  RW  NMI mask register (XT only)
	 bit 7 = 0 NMI signal disabled from reaching CPU
	       = 1 NMI signal enabled
----------P00A000AF--------------------------
PORT 00A0-00AF - Chips&Technologies 82C100/110 - NMI CONTROL
SeeAlso: PORT 0072h"82C100",PORT 007Fh"82C100"

00A0  RW  NMI mask register (XT only)
	 bit 7 = 0 NMI signal disabled from reaching CPU
	       = 1 NMI signal enabled
00Ax  RW  mirrors of PORT 00A0h
----------P00A800A9--------------------------
PORT 00A8-00A9 - Via VT82C496G "Pluto" - CONFIGURATION REGISTERS
SeeAlso: PORT 00A8h"VT82C570M"

00A8  ?W  configuration register index (see #P0419)
00A9  RW  configuration register data

(Table P0419)
Values for Via VT82C496G configuration registers:
 02h	clock throttling control (see #P0420)
 03h	I/O recovery (see #P0421)
 10h	bus speed (see #P0422)
 11h	ISA bus clock frequency control (see #P0423)
 20h	pair 0/1 row/column address (see #P0424)
 21h	pair 2/3 row/column address (see #P0425)
 22h	RAS#/CAS# pulse control (see #P0426)
 30h	C0000h-CFFFFh shadow control (see #P0427)
 31h	D0000h-DFFFFh shadow control (see #P0428)
 32h	E0000h-FFFFFh shadow control (see #P0429)
 33h	ROM decoding and memory relocation (see #P0430)
 40h	ROM cacheable control (see #P0431)
 41h	programmable non-cacheable region ???
 42h	programmable non-cacheable region ???
 43h	pair 0/1 DRAM size and configuration (see #P0432)
 44h	pair 2/3 DRAM size and configuration (see #P0433)
 50h	cache access mode (see #P0434)
 51h	cache timing/size control (see #P0435)
 52h	primary idle timer reloading control (see #P0436)
 53h	primary idle timer reload distinguish (see #P0437)
 54h	SMI triggering control (see #P0438)
 55h	SMI trigger distinguish (see #P0439)
 56h	clock frequency control (see #P0440)
 57h	peripheral timer (see #P0441)
 58h	general purpose timer (see #P0442)
 59h	timer control (see #P0443)
 5Ah	power/peripheral control (see #P0444)
 5Bh	system management control (see #P0445)
 5Ch	clock switching control (see #P0446)
 5Dh	peripheral timer control (see #P0447)
 5Eh	misc. cache control (see #P0448)
 5Fh	conserve mode/secondary idle timer control (see #P0449)
 60h	IRQ7-0 primary interrupt selection (see #P0450)
 61h	IRQ15-8 primary interrupt selection (see #P0451)
 62h	IRQ7-3 interrupt mode and global control (see #P0452)
 63h	IRQ15-9 interrupt mode (see #P0453)
 64h	(see #P0454)
 65h	peripheral timer control (see #P0455)
 68h	port 070h write shadow
 69h	port 2F8h write shadow
 6Ah	port 3F8h write shadow
 6Bh	port 372h write shadow
 6Ch	port 377h write shadow
 6Dh	port 171h write shadow
 6Eh	port 177h write shadow
 6Fh	port 376h write shadow
 71h	IDE controller/cache control (see #P0456)
 72h	non-1F0/170h port access timing (see #P0457)
 73h	drive #0 read timing for 1F0/170h access (see #P0458)
 74h	drive #0 write timing for 1F0/170h access (see #P0459)
 77h	drive #0 address setup time (see #P0460)
 78h	drive #1 read timing for 1F0/170h access (see #P0458)
 79h	drive #1 write timing for 1F0/170h access (see #P0459)
 7Ch	drive #1 address setup time (see #P0460)
SeeAlso: #P0461

Bitfields for Via VT82C496G/VT82C570M clock throttling control:
Bit(s)	Description	(Table P0420)
 4	STPCLK# throttling period (enabled by register 5Bh bit 0)
	0 = 3.35 æs * 16
	1 = 1.7 ms * 16
 3-0	duty cycle for STPCLK# (1/16 - 15/16) (enabled by register 5Bh bit 0)
SeeAlso: #P0419,#P0445

Bitfields for Via VT82C496G/VT82C570M register 03h:
Bit(s)	Description	(Table P0421)
 7-1	(VT82C496G) command delay, wait state and I/O recovery time for normal
	  ISA cycles ???
 0	decoupled DRAM refresh enable
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M register 10h:
Bit(s)	Description	(Table P0422)
 6	DMA controller runs at ISA clock speed/half ISA clock speed
SeeAlso: #P0419,#P0423

Bitfields for Via VT82C496G/VT82C570M ISA bus clock frequency control:
Bit(s)	Description	(Table P0423)
 6	flash EPROM write cycle support enable
 3-0	ISA bus clock frequency
	0xxx = CLKIN / 8
	1000 = CLKIN / 3
	1001 = CLKIN / 2
	1010 = CLKIN / 4
	1011 = CLKIN / 6
	1100 = CLKIN / 5
	1101 = CLKIN / 10
	1110 = CLKIN / 12
	1111 = OSC / 2 (asynchronous)
SeeAlso: #P0419,#P0422

Bitfields for Via VT82C496G/VT82C570M pair 0/1 row/column address:
Bit(s)	Description	(Table P0424)
 7-5	number of column address bits for pair 0
	000 = disabled
	001 = 9 bit
	010 = 10 bit
	011 = 11 bit
	100 = 12 bit
	101-111 = illegal
 4	page mode operation enable
 3-1	number of column address bits for pair 1 (same values as above)
 0	(VT82C496G) reserved
	(VT82C570M) DRAM bus width
	0 = 32 bit
	1 = 64 bit (operation width set in register 48h bits 3-0)
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M pair 2/3 row/column address:
Bit(s)	Description	(Table P0425)
 7-5	number of column address bits for pair 2
	000 = disabled
	001 = 9 bit
	010 = 10 bit
	011 = 11 bit
	100 = 12 bit
	101-111 = illegal
 4	reserved
 3-1	number of column address bits for pair 3 (same values as above)
 0	reserved
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M RAS#/CAS# pulse control:
Bit(s)	Description	(Table P0426)
 7-6	RAS# precharge time
	00-11 = (VT82C496G) 1-4 cycles
		(VT82C570M) 2-8 cycles
 5-4	RAS# pulse width
	00-11 = (VT82C496G) 2-5 cycles
		(VT82C570M) 4-10 cycles
 3-2	read cycle CAS# pulse width
	00-11 = 1-4 cycles
 1	write cycle CAS# pulse width
	0 = 1 cycle
	1 = 2 cycles
 0	RAS# to column address/column address to CAS#
	0 = 1 cycle
	1 = 2 cycles
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M C0000h-CFFFFh shadow control:
Bit(s)	Description	(Table P0427)
 7	CC000h-CFFFFh read shadow enable
 6	CC000h-CFFFFh write shadow enable
 5	C8000h-CBFFFh read shadow enable
 4	C8000h-CBFFFh write shadow enable
 3	C4000h-C7FFFh read shadow enable
 2	C4000h-C7FFFh write shadow enable
 1	C0000h-C3FFFh read shadow enable
 0	C0000h-C3FFFh write shadow enable
SeeAlso: #P0419,#P0428,#P0429

Bitfields for Via VT82C496G/VT82C570M D0000h-DFFFFh shadow control:
Bit(s)	Description	(Table P0428)
 7	DC000h-DFFFFh read shadow enable
 6	DC000h-DFFFFh write shadow enable
 5	D8000h-DBFFFh read shadow enable
 4	D8000h-DBFFFh write shadow enable
 3	D4000h-D7FFFh read shadow enable
 2	D4000h-D7FFFh write shadow enable
 1	D0000h-D3FFFh read shadow enable
 0	D0000h-D3FFFh write shadow enable
SeeAlso: #P0419,#P0427,#P0429

Bitfields for Via VT82C496G/VT82C570M E0000h-FFFFFh shadow control:
Bit(s)	Description	(Table P0429)
 7	E0000h-EFFFFh read shadow enable
 6	E0000h-EFFFFh write shadow enable
 5	F0000h-FFFFFh read shadow enable
 4	F0000h-FFFFFh write shadow enable
 3	???
 2	memory range F00000h-FFFFFFh decode as ISA cycle enable
 1	(VT82C496G) burstable DRAM cycles enable
	(VT82C570M) ???
 0	???
SeeAlso: #P0419,#P0427,#P0428,#P0430

Bitfields for Via VT82C496G/VT82C570M ROM decoding and memory relocation:
Bit(s)	Description	(Table P0430)
 7	C8000h-CFFFFh decoded as ROM cycle enable
 6	C0000h-C7FFFh decoded as ROM cycle enable
 5	E8000h-EFFFFh decoded as ROM cycle enable
 4	E0000h-E7FFFh decoded as ROM cycle enable
 3-2	memory relocation
	00 = disable
	01 = illegal
	10 = 256K relocation
	11 = 384K relocation
 1	(VT82C496G) RAS time-out
	(VT82C570M) ???
 0	???
SeeAlso: #P0419,#P0429,#P0431

Bitfields for Via VT82C496G/VT82C570M ROM cacheable control:
Bit(s)	Description	(Table P0431)
 7	C0000h-C7FFFh cacheable and write-protect enable
 6	F0000h-FFFFFh cacheable and write-protect enable
 5	E0000h-EFFFFh cacheable and write-protect enable
 4	???
 3	CAS-to-RAS refresh enable
 2	(VT82C570M) secondary cache fill for CACHE# inactive memory cycles
	  enable
 1-0	???
SeeAlso: #P0419,#P0430

Bitfields for Via VT82C496G/VT82C570M pair 0/1 DRAM size and configuration:
Bit(s)	Description	(Table P0432)
 7-5	(VT82C496G) bank-pair 0 DRAM size (x2 if double bank)
	000 = 512 KB
	001 = 1 MB
	010 = 2 MB
	011 = 4 MB
	100 = 8 MB
	101 = 16 MB
	110 = 32 MB
	111 = 64 MB
	(VT82C570M) bank-pair 0 DRAM size (x2 if double bank)
	000 = 1 MB
	001 = 2 MB
	010 = 4 MB
	011 = 8 MB
	100 = 16 MB
	101 = 32 MB
	110 = 64 MB
	111 = 128 MB
 4	number of banks in pair 0
	(0 bank if register 20h bit 7-5 = 0)
	0 = 1 bank
	1 = 2 banks
 3-1	(VT82C496G) bank-pair 1 DRAM size (x2 if double bank)
	(VT82C570M) bank-pair 1 DRAM size (x2 if double bank)
 0	number of banks in pair 1
	(0 bank if register 20h bit 3-1 = 0)
	0 = 1 bank
	1 = 2 banks
SeeAlso: #P0419,#P0433

Bitfields for Via VT82C496G/VT82C570M pair 2/3 DRAM size and configuration:
Bit(s)	Description	(Table P0433)
 7-5	(VT82C496G) bank-pair 2 DRAM size (x2 if double bank)
	000 = 512 KB
	001 = 1 MB
	010 = 2 MB
	011 = 4 MB
	100 = 8 MB
	101 = 16 MB
	110 = 32 MB
	111 = 64 MB
	(VT82C570M) bank-pair 2 DRAM size (x2 if double bank)
	000 = 1 MB
	001 = 2 MB
	010 = 4 MB
	011 = 8 MB
	100 = 16 MB
	101 = 32 MB
	110 = 64 MB
	111 = 128 MB
 4	number of banks of pair 2 (no banks if register 21h bit 7-5 = 0)
	0 = 1 bank
	1 = 2 banks
 3-1	(VT82C496G) bank-pair 3 DRAM size (x2 if double bank)
	(VT82C570M) bank-pair 3 DRAM size (x2 if double bank)
	(same values as for bits 7-5)
 0	number of banks of pair 3 (no banks if register 21h bit 3-1 = 0)
	0 = 1 bank
	1 = 2 banks
SeeAlso: #P0419,#P0432

Bitfields for Via VT82C496G/VT82C570M cache access mode:
Bit(s)	Description	(Table P0434)
 7-6	cache mode
	0x = disabled
	10 = enabled
	11 = initialization
 5	(VT82C496G) direct data SRAM access
	(VT82C570M) Cyrix CPU linear burst order enable
 4	(VT82C496G) write-back cache alter bit control (don't care for write
	  through)
	0 = combined tag/alter bit
	1 = no alter bit
 4-3	(VT82C570M) number of tag/alter bits
	  write-back (register 5Eh bit 6 = 0)
	       tag   alter   total
	  00	 8	 0	 8
	  01	 7	 1	 8
	  10	 8	 1	 9
	  11	10	 1	11
	  write-through (register 5Eh bit 6 = 1)
	       tag   alter   total
	  x0	 8	 -	 8
	  01	 7	 -     N/A
	  11	10	 -	10
 3-2	(VT82C496G) cache line size
	00 = 4 bytes
	01 = 8 bytes
	10 = 16 bytes
	11 = 4 bytes
 2	(VT82C570M) data synchronous SRAM type (if register 51h bit 4 = 0)
	0 = standard synchronous SRAM
	1 = pipelined burst synchronous SRAM
 1	(VT82C496G) burst write enable
	(VT82C570M) cache read wait state for PCI masters (PCI clock)
	0 = zero wait state (2-1-1-1)
	1 = one wait state (3-2-2-2)
 0	(VT82C496G) data streaming enable
	(VT82C570M) cache write wait state for PCI masters (PCI clock)
	0 = zero wait state (2-1-1-1)
	1 = one wait state (3-2-2-2)
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M cache timing/size control:
Bit(s)	Description	(Table P0435)
 7	(VT82C496G) read hit timing
	0 = 2-X-X-X
	1 = 3-X-X-X
	(VT82C570M) read hit timing for first cycle (CPU clock) for
	  asynchronous SRAM
	0 = 1 wait state (2-X-X-X)
	1 = 2 wait state (3-X-X-X)
 6	(VT82C496G) write hit timing
	0 = 2-X-X-X
	1 = 3-X-X-X
	(VT82C570M) write hit timing for first cycle (CPU clock) for
	  asynchronous SRAM
	0 = 1 wait state (3-X-X-X)
	1 = 2 wait state (4-X-X-X)
 5	(VT82C496G) read hit timing
	0 = X-1-1-1
	1 = X-2-2-2
	(VT82C570M) read hit timing for second-fourth burst cycle (CPU clock)
	  for asynchronous SRAM
	0 = 1 wait state (X-2-2-2)
	1 = 2 wait state (X-3-3-3)
 4	(VT82C496G) write hit timing
	0 = X-1-1-1
	1 = X-2-2-2
	(VT82C570M) data SRAM type
	0 = synchronous SRAM (type set in register 50h bit 2)
	1 = asynchronous SRAM
 3	bank of data SRAM
	0 = 1 bank
	1 = 2 banks
 2-0	cache size
	000 = no cache
	001 = (VT82C496G) 32 KB
	010 = (VT82C496G) 64 KB
	011 = 128 KB
	100 = 256 KB
	101 = 512 KB
	110 = 1 MB
	111 = (VT82C570M) 2 MB
Note:	(VT82C570M) write hit timing is always 1 wait state (X-2-2-2) for
	  asynchronous SRAM; read/write hit timing is always 3-1-1-1 for
	  synchronous SRAM
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M primary idle timer reloading control:
Bit(s)	Description	(Table P0436)
 7	reload primary idle timer on keyboard access
 6	reload primary idle timer on serial port access
 5	reload primary idle timer on parallel port access
 4	reload primary idle timer on video access
 3	reload primary idle timer on hard disk and floppy access
 2	reload primary idle timer on IO port 100h-3FFh access
 1	reload primary idle timer on external input
 0	reload primary idle timer on DRQ/LREQ (DMA/local bus master request)
SeeAlso: #P0419,#P0437,#P0438

Bitfields for Via VT82C496G/VT82C570M primary idle timer reload distinguish:
Bit(s)	Description	(Table P0437)
 7	primary idle timer reloaded by keyboard access
 6	primary idle timer reloaded by serial port access
 5	primary idle timer reloaded by parallel port access
 4	primary idle timer reloaded by video access
 3	primary idle timer reloaded by hard disk and floppy access
 2	primary idle timer reloaded by IO port 100h-3FFh access
 1	primary idle timer reloaded by external input
 0	primary idle timer reloaded by DRQ/LREQ (DMA/local bus master request)
SeeAlso: #P0419,#P0436,#P0438

Bitfields for Via VT82C496G/VT82C570M SMI triggering control:
Bit(s)	Description	(Table P0438)
 7	trigger SMI on primary idle timer time-out
 6	trigger SMI on general purpose timer time-out
 5	trigger SMI on primary activity occurrence
 4	trigger SMI on primary interrupt occurrence
 3	trigger SMI on external pin (Turbo) toggle
 2	(VT82C496G) trigger SMI on DRQ/LREQ occurrence
	(VT82C570M) trigger SMI on DRQ/PREQ occurrence
 1	trigger SMI on peripheral timer or secondary idle timer
	  time-out
	(VT82C496G) (use register 65h bits 3 and 2 to distinguish)
 0	trigger SMI on software SMI
SeeAlso: #P0419,#P0436,#P0438,#P0439

Bitfields for Via VT82C496G/VT82C570M SMI trigger distinguish:
Bit(s)	Description	(Table P0439)
 7	SMI triggered by primary idle timer time-out
 6	SMI triggered by general purpose timer time-out
 5	SMI triggered by primary activity occurrence
 4	SMI triggered by primary interrupt occurrence
 3	SMI triggered by external pin (Turbo) toggle
 2	(VT82C496G) SMI triggered by DRQ/LREQ occurrence
	(VT82C570M) SMI triggered by DRQ/PREQ occurrence
 1	SMI triggered by peripheral timer or secondary idle timer
	  time-out
	(VT82C496G) (use register 65h bits 1 and 0 to distinguish)
 0	SMI triggered by software SMI
SeeAlso: #P0419,#P0438

Bitfields for Via VT82C496G/VT82C570M clock frequency control:
Bit(s)	Description	(Table P0440)
 7-5	(VT82C496G) CPU clock frequency
	000 = CLKIN
	001 = CLKIN / 4
	010 = CLKIN / 8
	011 = CLKIN / 16
	100 = CLKIN / 32
	101 = CLKIN / 64
	110 = CLKIN / 2
	111 = 0
 3-0	CLKIN frequency
	0000 = 16 MHz
	0001 = 40 MHz
	0010 = 50 MHz
	0011 = 80 MHz
	0100 = 66 MHz
	0101 = 100 MHz
	0110 = 8 MHz
	0111 = 60 MHz
	1000 = 8 MHz
	1001 = 20 MHz
	1010 = 25 MHz
	1011 = 40 MHz
	1100 = 33 MHz
	1101 = 50 MHz
	1110 = 4 MHz
	1111 = 30 MHz
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M peripheral timer:
Bit(s)	Description	(Table P0441)
 7-0	(VT82C496G) peripheral timer (time base determined in register 5Dh
	  bits 1-0)
	(VT82C570M) peripheral timer (time base determined in register 66h
	  bits 3-2)
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M general purpose timer:
Bit(s)	Description	(Table P0442)
 7-0	general purpose timer (time base determined in register 59h bits 7-6)
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M timer control:
Bit(s)	Description	(Table P0443)
 7-6	general purpose timer (register 58h) time base
	00 = disable
	01 = 32.768 KHz
	10 = 1 sec
	11 = 1 min
 3-1	primary idle timer time-out
	000 = disable
	001 = 1 sec
	010 = 8 sec
	011 = 32 sec
	100 = 1 min
	101 = 8 min
	110 = 16 min
	111 = 32 min
 0	(VT82C496G) leakage control mode
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M power/peripheral control:
Bit(s)	Description	(Table P0444)
 7-4	general purpose output ports ???
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M system management control:
Bit(s)	Description	(Table P0445)
 7	(VT82C496G) power management mode enable
 6	(VT82C496G) SMI type
	0 = Intel 2-pin SMI (SMI#/SMIACT#)
	  (pin 112 used as SMIACT#, SM base = 30000h to 4FFFFh)
	1 = TI/AMD/Cyrix 3-pin SMI (SMI#/SMIADS#/SMIRDY#)
	  (pin 112 used as SMIADS#, SM base = 60000h to 7FFFFh)
 5	(VT82C496G) SMI target
	0 = SMI output to CPU
	1 = SMI redirected to interrupt 15 of internal 8259 interrupt
	  controller (for non-SMI CPU support)
 4	SM memory remap enable (SM base memory mapped to A0000h to BFFFFh)
 3	(VT82C496G) direct DRAM access to SMI target memory A0000h-BFFFFh
	  enable
 2	???
 1	(VT82C496G) force 3000h-4FFFFh to map to A0000h-BFFFFh
	(move SM code without causing local bus device conflict with
	  A0000h-BFFFFh)
 0	clock throttling enable
SeeAlso: #P0419

Bitfields for Via VT82C496G clock switching control:
Bit(s)	Description	(Table P0446)
 7	wait for a HALT cycle to start clock switching
 6	wait for an acknowledgment to start clock switching
 5	clock switching protocol
	0 = Intel STPCLK# protocol (pin 117 used as STPCLK# output)
	1 = TI/Cyrix SUSP#/SUSPA# protocol (pin 117 used as SUSP# input)
SeeAlso: #P0419

Bitfields for Via VT82C496G peripheral timer control:
Bit(s)	Description	(Table P0447)
 7-2	???
 1-0	peripheral timer (register 57h) time base
	00 = disable
	01 = 32.768 KHz
	10 = 1 sec
	11 = 1 min
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M misc. cache control:
Bit(s)	Description	(Table P0448)
 7	(VT82C496G) CPU internal cache
	0 = write-through
	1 = write-back
 6	external cache
	0 = write-back
	1 = write-through
 5	(VT82C496G) pin 72 usage
	0 = BLAST# (burst last input from the CPU)
	1 = CACHE# (P24T) (burst cycle indicator)
 4	(VT82C496G) snoop filtering enable
 3	???
 2	slow refresh enable
 1-0	???
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M conserve mode/secondary idle timer:
Bit(s)	Description	(Table P0449)
 7-6	(VT82C496G) conserve mode active period
	00 = 1/16 sec
	01 = 1/8 sec
	10 = 1 sec
	11 = 1 min
 5	conserve mode enable
 4	(VT82C496G) conserve mode clock select
	0 = CLKIN / 2
	1 = CLKIN / 4
 3-2	secondary idle timer time-out
	00 = 2 ms
	01 = 16 ms
	10 = 64 ms
	11 = EOI + 0.125 ms
 1	secondary events handler enable (secondary interrupt reloads secondary
	  idle timer)
 0	(VT82C496G) change clock speed on secondary interrupt to
	0 = CLKIN
	1 = CLKIN / 2
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M IRQ7-0 primary interrupt selection:
Bit(s)	Description	(Table P0450)
 7	IRQ7 is primary interrupt
 6	IRQ6 is primary interrupt
 5	IRQ5 is primary interrupt
 4	IRQ4 is primary interrupt
 3	IRQ3 is primary interrupt
 2	IRQ1 is primary interrupt
 1	IRQ0 is primary interrupt
 0	(VT82C496G) reload primary idle timer on primary interrupt
SeeAlso: #P0419,#P0451,#P0452

Bitfields for Via VT82C496G/VT82C570M IRQ15-8 primary interrupt selection:
Bit(s)	Description	(Table P0451)
 7	IRQ15 is primary interrupt
 6	IRQ14 is primary interrupt
 5	IRQ13 is primary interrupt
 4	IRQ12 is primary interrupt
 3	IRQ11 is primary interrupt
 2	IRQ10 is primary interrupt
 1	IRQ9 is primary interrupt
 0	IRQ8 is primary interrupt
SeeAlso: #P0419,#P0450,#P0453

Bitfields for Via VT82C496G IRQ7-3 interrupt mode and global control:
Bit(s)	Description	(Table P0452)
 7	IRQ7 interrupt mode (refer to note below)
 6	IRQ6 interrupt mode
 5	IRQ5 interrupt mode
 4	IRQ4 interrupt mode
 3	IRQ3 interrupt mode
 2	IRQ8 treated as
	0 = sub-secondary interrupt (CPU clock speed unchanged)
	1 = secondary interrupt
 1	IRQ0 treated as
	0 = sub-secondary interrupt (CPU clock speed unchanged)
	1 = secondary interrupt
 0	interrupt mode global control
	0 = 8259A compatible mode (all interrupt edge triggered)
	1 = extended mode (enables selection with registers 62h and 63h)
Note:	for bits 7-3, 0 = edge-triggered, 1 = level-sensitive
SeeAlso: #P0419,#P0450,#P0453

Bitfields for Via VT82C496G/VT82C570M IRQ15-9 interrupt mode:
Bit(s)	Description	(Table P0453)
 7	IRQ15 interrupt mode (refer to note below)
 6	IRQ14 interrupt mode
 5	reserved
 4	IRQ12 interrupt mode
 3	IRQ11 interrupt mode
 2	IRQ10 interrupt mode
 1	IRQ9 interrupt mode
 0	???
Note:	for bits 7-6 and 4-1, 0 = edge-triggered, 1 = level-sensitive
SeeAlso: #P0419,#P0451,#P0452

Bitfields for Via VT82C496G/VT82C570M register 64h:
Bit(s)	Description	(Table P0454)
 3-0	MA0-3 jumper setting ???
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M peripheral timer control:
Bit(s)	Description	(Table P0455)
 7	reload peripheral timer on keyboard access
 6	reload peripheral timer on serial port access
 5	reload peripheral timer on video access
 4	reload peripheral timer on hard disk and floppy access
 3	(VT82C496G) trigger SMI on peripheral timer time-out
	(VT82C570M) reload peripheral timer on parallel port access
 2	(VT82C496G) trigger SMI on secondary idle timer time-out
	(VT82C570M) reserved
 1	(VT82C496G) SMI triggered by peripheral timer time-out
	(VT82C570M) reload peripheral timer on speaker access
 0	(VT82C496G) SMI triggered by secondary idle timer time-out
	(VT82C570M) reserved
SeeAlso: #P0419

Bitfields for Via VT82C496G IDE controller/cache control:
Bit(s)	Description	(Table P0456)
 7	reserved
 6	channel and I/O port selection
	0 = primary channel (1F0h-1F7h)
	1 = secondary channel (170h-177h)
 5	write buffer enable
 4	prefetch buffer enable
 3	internal LRDY# for write cycles (0 = second T2, 1 = first T2)
 2	internal LRDY# for read cycles	(0 = second T2, 1 = first T2)
 1	read data to be presented to CPU data bus
	0 = second T2
	1 = first T2
 0	internal IDE controller enable
SeeAlso: #P0419

Bitfields for Via VT82C496G non-1F0/170h port access timing:
Bit(s)	Description	(Table P0457)
 7-4	number of CPU clocks as command active time
 3-0	number of CPU clocks as command recovery time
SeeAlso: #P0419

Bitfields for Via VT82C496G drive #0/1 read timing for 1F0/170h access:
Bit(s)	Description	(Table P0458)
 7-4	number of CPU clocks as command active time
 3-0	number of CPU clocks as command recovery time
SeeAlso: #P0419,#P0459,#P0460

Bitfields for Via VT82C496G drive #0/1 write timing for 1F0/170h access:
Bit(s)	Description	(Table P0459)
 7-4	number of CPU clocks as command active time
 3-0	number of CPU clocks as command recovery time
SeeAlso: #P0419,#P0458,#P0460

Bitfields for Via VT82C496G drive #0/1 address setup time:
Bit(s)	Description	(Table P0460)
 1-0	number of CPU clocks as address setup time
SeeAlso: #P0419,#P0458,#P0459
----------P00A800AC--------------------------
PORT 00A8-00AC - Via VT82C570M "Apollo Master" - CONFIGURATION REGISTERS
SeeAlso: PORT 00A8h"VT82C486G"

00A8  ?W  configuration register index (see #P0461)
00A9  RW  configuration register 00h-9Fh data
00AC  RW  configuration register FBh-FFh data

(Table P0461)
Values for Via VT82C570M configuration registers:
 02h	clock throttling control (see #P0420)
 03h	I/O recovery (see #P0421)
 10h	bus speed (see #P0422)
 11h	ISA bus clock frequency control (see #P0423)
 20h	pair 0/1 row/column address (see #P0424)
 21h	pair 2/3 row/column address (see #P0425)
 22h	RAS#/CAS# pulse control (see #P0426)
 30h	C0000h-CFFFFh shadow control (see #P0427)
 31h	D0000h-DFFFFh shadow control (see #P0428)
 32h	E0000h-FFFFFh shadow control (see #P0429)
 33h	ROM decoding and memory relocation (see #P0430)
 40h	ROM cacheable control (see #P0431)
 41h	programmable non-cacheable region ???
 42h	programmable non-cacheable region ???
 43h	pair 0/1 DRAM size and configuration (see #P0432)
 44h	pair 2/3 DRAM size and configuration (see #P0433)
 47h	DRAM type (see #P0462)
 48h	DRAM control (see #P0463)
 49h	cache control (see #P0464)
 50h	cache access mode (see #P0434)
 51h	cache timing/size control (see #P0435)
 52h	primary idle timer reloading control (see #P0436)
 53h	primary idle timer reload distinguish (see #P0437)
 54h	SMI triggering control (see #P0438)
 55h	SMI trigger distinguish (see #P0439)
 56h	clock frequency control (see #P0440)
 58h	general purpose timer (see #P0442)
 59h	timer control (see #P0443)
 5Ah	power/peripheral control (see #P0444)
 5Bh	system management control (see #P0445)
 5Eh	misc. cache control (see #P0448)
 5Fh	conserve mode/secondary idle timer control (see #P0449)
 60h	IRQ7-0 primary interrupt selection (see #P0450)
 61h	IRQ15-8 primary interrupt selection (see #P0451)
 63h	IRQ15-9 interrupt mode (see #P0453)
 64h	(see #P0454)
 65h	peripheral timer control (see #P0455)
 66h	(see #P0465)
 67h	peripheral timer (see #P0441)
 68h	multiple SMI triggering ???
 69h	multiple SMI triggering ???
 6Ah	multiple SMI triggering ???
 7Bh	general purpose input and output port ???
 7Ch	general purpose input and output port ???
 7Eh	general purpose output port ???
 7Fh	general purpose input and output port ???
 82h	PCI buffer control (see #P0466)
 83h	PCI data link control (see #P0467)
 84h	PCI interface timing (see #P0468)
 85h	PCI arbitration (see #P0469)
 86h	(see #P0470)
 93h	(see #P0471)
 9Ch	programmable chipselect A (see #P0472)
 9Dh	programmable chipselect A address mask (see #P0473)
 9Eh	programmable chipselect B (see #P0474)
 9Fh	programmable chipselect B address mask (see #P0475)
 FBh	plug and play DRQ routing (see #P0476)
 FCh	PCI interrupt polarity (see #P0477)
 FDh	plug and play IRQ routing (see #P0478)
 FEh	PCI IRQ routing 1 (see #P0479)
 FFh	PCI IRQ routing 2 (see #P0480)
SeeAlso: #P0419

Bitfields for Via VT82C570M DRAM type:
Bit(s)	Description	(Table P0462)
 7	Bank 3 DRAM type (used with bit 3)
	bits 7 and 3:
	00 = standard DRAM
	01 = burst EDO DRAM
	10 = EDO DRAM
	11 = illegal
 6	Bank 2 DRAM type (used with bit 2)
	bits 6 and 2: same values as for bits 7 and 3
 5	Bank 1 DRAM type (used with bit 1)
	bits 5 and 1: same values as for bits 7 and 3
 4	Bank 0 DRAM type (used with bit 0)
	bits 4 and 0: same values as for bits 7 and 3
 3	Bank 3 DRAM type (used with bit 7)
 2	Bank 2 DRAM type (used with bit 6)
 1	Bank 1 DRAM type (used with bit 5)
 0	Bank 0 DRAM type (used with bit 4)
SeeAlso: #P0461

Bitfields for Via VT82C570M register 48h:
Bit(s)	Description	(Table P0463)
 7	reserved
 6	eight CWE# pins for each byte in addition to global GWE# ???
 5-4	reserved
 3-0	DRAM operation width (if register 20h bit 0 = 1)
	0 = 64 bit operation for corresponding DRAM bank
	1 = 32 bit operation for corresponding DRAM bank
SeeAlso: #P0461

Bitfields for Via VT82C570M register 49h:
Bit(s)	Description	(Table P0464)
 5	0 = cache SRAM write enable for each bank
	1 = cache SRAM byte write enable
SeeAlso: #P0461

Bitfields for Via VT82C570M register 66h:
Bit(s)	Description	(Table P0465)
 3-2	peripheral timer (register 67h) time base
	00 = disable
	01 = 32.768 KHz
	10 = 1 sec
	11 = 1 min
SeeAlso: #P0461

Bitfields for Via VT82C570M PCI buffer control:
Bit(s)	Description	(Table P0466)
 7	CPU to PCI write buffer enable
 6	PCI to memory write buffer enable
 5	reserved
 4	PCI accessing memory prefetch buffer enable
 3	PCI accelerated decoding enable
 2	reserved
 1	on-board memory burst write enable
 0	on-board memory burst read enable
SeeAlso: #P0461

Bitfields for Via VT82C570M PCI data link control:
Bit(s)	Description	(Table P0467)
 7	data link write cycle
	0 = 1 wait state
	1 = 0 wait state
 6-4	reserved
 3	on-board memory detection point for PCI master
	0 = first address phase
	1 = first data phase
 2-1	reserved
 0	reserved (must be 0)
SeeAlso: #P0461

Bitfields for Via VT82C570M PCI interface timing:
Bit(s)	Description	(Table P0468)
 7	slave mode lock function enable
 6	retry count
	0 = 16 times
	1 = 64 times
 5	retry deadlock error reporting enable
 4	retry status occurred (write 1 to reset)
 3	CPU to PCI fast back to back enable
 2	fast FRAME# generation enable
 1-0	DEVSEL# decoding
	00 = fast
	01 = medium
	10 = slow
	11 = subtractive
SeeAlso: #P0461

Bitfields for Via VT82C570M PCI arbitration:
Bit(s)	Description	(Table P0469)
 7	0 = priority on PCI bus
	1 = fairness between CPU and PCI bus
 6	0 = REQ# based
	1 = FRAME# based
 5-4	CPU time slot in unit of
	00 = 4 PCI clocks
	01 = 8 PCI clocks
	10 = 16 PCI clocks
	11 = 32 PCI clocks
 3-0	PCI master bus time out
	0000 = disable
	0001-1111 = 1x32 - 15x32 PCI clocks
SeeAlso: #P0461

Bitfields for Via VT82C570M register 86h:
Bit(s)	Description	(Table P0470)
 7	PCI configuration mechanism #1/#2 (default #1)
SeeAlso: #P0461

Bitfields for Via VT82C570M register 93h:
Bit(s)	Description	(Table P0471)
 5	parity or system error at PCI bus signify
	0 = I/O channel check
	1 = NMI
SeeAlso: #P0461

Bitfields for Via VT82C570M programmable chipselect A:
Bit(s)	Description	(Table P0472)
 7-0	chipselect A address (high two bits in register 9Dh bits 1-0)
SeeAlso: #P0461,#P0473,#P0474

Bitfields for Via VT82C570M programmable chipselect A address mask:
Bit(s)	Description	(Table P0473)
 7-2	chipselect A address mask
 1-0	chipselect A address (low eight bits in register 9Dh)
SeeAlso: #P0461,#P0472,#P0474

Bitfields for Via VT82C570M programmable chipselect B:
Bit(s)	Description	(Table P0474)
 7-0	chipselect B address (high two bits in register 9Fh bits 1-0)
SeeAlso: #P0461,#P0472,#P0475

Bitfields for Via VT82C570M programmable chipselect B address mask:
Bit(s)	Description	(Table P0475)
 7-2	chipselect B address mask
 1-0	chipselect B address (low eight bits in register 9Eh)
SeeAlso: #P0461,#P0473,#P0474

Bitfields for Via VT82C570M plug and play DRQ routing:
Bit(s)	Description	(Table P0476)
 7-6	reserved
 5-3	PDRQ1 routing
	000-011 = DRQ0-3
	100 = reserved
	101-111 = DRQ5-7
 2-0	PDRQ0 routing
	000-011 = DRQ0-3
	100 = reserved
	101-111 = DRQ5-7
SeeAlso: #P0461

Bitfields for Via VT82C570M PCI interrupt polarity:
Bit(s)	Description	(Table P0477)
 7-4	reserved
 3	INTA# polarity (refer to note below)
 2	INTB# polarity
 1	INTC# polarity
 0	INTD# polarity
Note:	for bits 3-0, 0 = non-invert (level-sensitive), 1 = inverted (edge)
SeeAlso: #P0461

Bitfields for Via VT82C570M plug and play IRQ routing:
Bit(s)	Description	(Table P0478)
 7-4	INTD# routing (value indicates desired IRQ number; 0,2,13 are reserved)
 3-0	PIRQ0 routing (value indicates desired IRQ number; 0,2,13 are reserved)
SeeAlso: #P0461,#P0479,#P0480

Bitfields for Via VT82C570M PCI IRQ routing 1:
Bit(s)	Description	(Table P0479)
 7-4	INTA# routing (value indicates desired IRQ number; 0,2,13 are reserved)
 3-0	INTB# routing (value indicates desired IRQ number; 0,2,13 are reserved)
SeeAlso: #P0461,#P0478,#P0480

Bitfields for Via VT82C570M PCI IRQ routing 2:
Bit(s)	Description	(Table P0480)
 7-4	INTC# routing (value indicates desired IRQ number; 0,2,13 are reserved)
 3-0	PIRQ1 routing (value indicates desired IRQ number; 0,2,13 are reserved)
SeeAlso: #P0461,#P0478,#P0479
----------P00A800A9--------------------------
PORT 00A8-00A9 - Via VT82C586A - GPIO

00A8  ?W  configuration register index
00A9  RW  configuration register data
----------P00B000BF--------------------------
PORT 00B0-00BF - PC radio by CoZet Info Systems
Range:	The I/O address range is dipswitch selectable from:
	   038-03F and 0B0-0BF
	   078-07F and 0F0-0FF
	   138-13F and 1B0-1BF
	   178-17F and 1F0-1FF
	   238-23F and 2B0-2BF
	   278-27F and 2F0-2FF
	   338-33F and 3B0-3BF
	   378-37F and 3F0-3FF
Notes:	All of these addresses show a readout of FFh in initial state.
	Once started, all of the addresses show	FBh, whatever might happen.
----------P00B2------------------------------
PORT 00B2 - Intel chipsets - Advanced Power Management Control
Notes:	used to pass data between the operating system and the System
	  Management Interrupt (SMI) handler
	writes to this port can cause an SMI; reads can cause STPCLK# to be
	  asserted (putting the CPU in sleep mode)
	supported by 82420EX, 82371, and other Intel chipsets
SeeAlso: PORT 00B3h,#01079

00B2  RW  control
----------P00B3------------------------------
PORT 00B3 - Intel chipsets - Advanced Power Management Status
Notes:	used to pass data between the operating system and the System
	  Management Interrupt (SMI) handler
	supported by 82420EX, 82371, and other Intel chipsets
SeeAlso: PORT 00B2h

00B3  RW  status
----------P00C0------------------------------
PORT 00C0 - TI SN746496 programmable tone/noise generator (PCjr)
----------P00C000DF--------------------------
PORT 00C0-00DF - DMA 2 - SECOND DIRECT MEMORY ACCESS CONTROLLER (8237)

00C0  RW  DMA channel 4 memory address bytes 1 and 0 (low) (ISA, EISA)
00C2  RW  DMA channel 4 transfer count bytes 1 and 0 (low) (ISA, EISA)
00C4  RW  DMA channel 5 memory address bytes 1 and 0 (low) (ISA, EISA)
00C6  RW  DMA channel 5 transfer count bytes 1 and 0 (low) (ISA, EISA)
00C8  RW  DMA channel 6 memory address bytes 1 and 0 (low) (ISA, EISA)
00CA  RW  DMA channel 6 transfer count bytes 1 and 0 (low) (ISA, EISA)
00CC  RW  DMA channel 7 memory address byte 0 (low), then 1 (ISA, EISA)
00CE  RW  DMA channel 7 transfer count byte 0 (low), then 1 (ISA, EISA)

00D0  R-  DMA channel 4-7 status register (ISA, EISA) (see #P0481)
00D0  -W  DMA channel 4-7 command register (ISA, EISA) (see #P0482)
00D2  -W  DMA channel 4-7 write request register (ISA, EISA)
00D4  -W  DMA channel 4-7 write single mask register (ISA, EISA) (see #P0484)
00D6  -W  DMA channel 4-7 mode register (ISA, EISA) (see #P0485)
00D8  -W  DMA channel 4-7 clear byte pointer flip-flop (ISA, EISA)

00DA  R-  DMA channel 4-7 read temporary register (ISA, EISA)
00DA  -W  DMA channel 4-7 master clear (ISA, EISA)
00DC  -W  DMA channel 4-7 clear mask register (ISA, EISA)
00DE  -W  DMA channel 4-7 write mask register (ISA, EISA) (see #P0486)
Notes:	the temporary register is used as holding register in memory-to-memory
	  DMA transfers; it holds the last transferred byte
	channel 4 is used for cascading the first (8-bit) DMA controller
	base/current address registers can only address the memory in 16-bit
	  words (i.e. they contain lines A1-A16 of the address bus with line
	  A0 always equal to 0); base/current word count registers contain the
	  number of 16-bit words
	command and request registers do not exist on PS/2 DMA controller

Bitfields for DMA channel 4-7 status register:
Bit(s)	Description	(Table P0481)
 7 = 1	channel 7 request
 6 = 1	channel 6 request
 5 = 1	channel 5 request
 4 = 1	channel 4 request
 3 = 1	terminal count on channel 7
 2 = 1	terminal count on channel 6
 1 = 1	terminal count on channel 5
 0 = 1	terminal count on channel 4
SeeAlso: #P0001,#P0482

Bitfields for DMA channel 4-7 command register:
Bit(s)	Description	(Table P0482)
 7	DACK sense active high
 6	DREQ sense active high
 5	=1  extended write selection
	=0  late write selection
 4	rotating priority instead of fixed priority
 3	compressed timing
 2	=1  enable controller
	=0  enable memory-to-memory transfer
 1-0	channel number (00 = 4 to 11 = 7)
SeeAlso: #P0002,#P0481,#P0484

Bitfields for DMA channel 4-7 request register:
Bit(s)	Description	(Table P0483)
 7-3	reserved (0)
 2	=0 clear request bit
	=1 set request bit
 1-0	channel number
	00 channel 4 select
	01 channel 5 select
	10 channel 6 select
	11 channel 7 select
SeeAlso: #P0003,#P0484

Bitfields for DMA channel 4-7 write single mask register:
Bit(s)	Description	(Table P0484)
 7-3	reserved
 2	=0  clear mask bit
	=1  set mask bit
 1-0	channel select
	00 channel 4 select
	01 channel 5 select
	10 channel 6 select
	11 channel 7 select
SeeAlso: #P0004,#P0482

Bitfields for DMA channel 4-7 mode register:
Bit(s)	Description	(Table P0485)
 7-6	transfer mode
	00  demand mode
	01  single mode
	10  block mode
	11  cascade mode
 5	direction
	0  address increment select
	1  address decrement select
 4	autoinitialisation enabled
 3-2	operation
	00  verify operation
	01  write to memory
	10  read from memory
	11  reserved
 1-0	channel number
	00  channel 4 select
	01  channel 5 select
	10  channel 6 select
	11  channel 7 select
SeeAlso: #P0005,#P0484

Bitfields for DMA channel 4-7 write mask register:
Bit(s)	Description	(Table P0486)
 7-4	reserved
 3	channel 7 mask bit
 2	channel 6 mask bit
 1	channel 5 mask bit
 0	channel 4 mask bit
Note:	each mask bit is automatically set when the corresponding channel
	  reaches terminal count or an extenal EOP sigmal is received
SeeAlso: #P0484,#P0006
----------P00E000E1--------------------------
PORT 00E0-00E1 - CHIPSET FROM ACT

00E0  ?W  index for accesses to data port
00E1  R?  chip set data
----------P00E000E7--------------------------
PORT 00E0-00E7 - MICROCHANNEL

00E0  RW  split address register, memory encoding registers PS/2m80 only
	(see #P0487)
00E1  RW  memory register (see #P0488,#P0489)
00E3  RW  error trace (bits 23-16 of address on last rising edge of ERS line)
00E4  RW  error trace (bits 15-8 of address on last rising edge of ERS line)
00E5  RW  error trace (see #P0490)
00E7  RW  error trace (see #P0491)

Bitfields for Microchannel Split Address Register:
Bit(s)	Description	(Table P0487)
 7-6	unused
 5-4	2MB memory for connector 2 on Type2 motherboard
	bit 5: second MB disabled or not present
	bit 4: first MB disabled or not present
 3-0	address at which to place leftover from split in first MB, in MB
	(1-15, 0 is invalid when split is active)
SeeAlso: #P0488,#P0489

Bitfields for Microchanel Memory Register, Type1 motherboard:
Bit(s)	Description	(Table P0488)
 7-6	1 MB memory for connector 2
	10 installed
	11 not installed
 5-4	1 MB memory for connector 1
	10 installed
	11 not installed
 3-1	split memory select
		ROM   convmem	over1M
	001	ON	640K	384K
	011	ON	512K	512K
	100	shadow	640K	0K
	101	ON	640K	0K
	110	shadow	512K	0K
	111	ON	512K	0K
 0	parity checking
	=0 enable
	=1 clear parity error (write 0 to re-enable parity checking)
SeeAlso: #P0487,#P0489

Bitfields for Microchannel Memory Register, Type2 motherboard:
Bit(s)	Description	(Table P0489)
 7-6	unused
 5-4	memory connector 1
	bit 5: second MB disabled or not present
	bit 4: first MB disabled or not present
 3-1	split memory select
		ROM   convmem	over1M
	000	shadow	640K	256K
	001	ON	640K	384K
	010	shadow	512K	384K
	011	ON	512K	512K
	100	shadow	640K	0K
	101	ON	640K	0K
	110	shadow	512K	0K
	111	ON	512K	0K
 0	parity checking
	=0 enable
	=1 clear parity error (write 0 to re-enable parity checking)
SeeAlso: #P0487,#P0488

Bitfields for Microchannel Error Trace register E5h:
Bit(s)	Description	(Table P0490)
 7-2	bits 7-2 of address on last rising edge of ERS line
 1	address space (0=I/O, 1=memory)
 0	=1 bus-master arbitration cycle
SeeAlso: #P0491

Bitfields for Microchannel Error Trace register E7h:
Bit(s)	Description	(Table P0491)
 7-1	unused
 0	bus cycle type
	=0 control (instruction fetch, halt, interrupt acknowledge)
	=1 data
SeeAlso: #P0490
----------P00E000EF--------------------------
PORT 00E0-00EF - IBM PS/1 CLOCK
----------P00E1------------------------------
PORT 00E1 - STB PowerMEG - ???
Desc:	the STB PowerMEG is a memory expansion card capable of providing EMS

00E1  RW  ???
	  bit 0: ???
--------X-P00E2------------------------------
PORT 00E2 - S3 Trio64V+ - I2C PORT
Range:	PORT 00E2h or PORT 00E8h; default depends on external pin, but can
	  be reprogrammed via chip's CR6F
SeeAlso: PORT 00E8h,#M0079
--------X-P00E8------------------------------
PORT 00E8 - S3 Trio64V+ - I2C PORT
Range:	PORT 00E2h or PORT 00E8h; default depends on external pin, but can
	  be reprogrammed via chip's CR6F
SeeAlso: PORT 00E2h,#M0079
----------P00EB------------------------------
PORT 00EB - Intel "Triton" chipset - ???
SeeAlso: PORT 0085h"Triton"

00EB  ?W  ???
----------P00EB------------------------------
PORT 00EB - DUMMY PORT FOR DELAY???
Note:	on a number of machines, the BIOS appears to write a copy of any
	  data sent to numerous other ports to this port as well; it seems
	  to be a dummy port used for short delays between writes to other
	  ports (used instead of JMP $+2, which no longer delays on Pentium+)
SeeAlso: PORT 00ED"DUMMY"

00EB  ?W  ???
----------P00EC00ED--------------------------
PORT 00EC-00ED - Compaq LTE Elite
----------P00ED------------------------------
PORT 00ED - DUMMY PORT FOR DELAY???
Note:	on a number of machines, the BIOS appears to write a copy of any
	  data sent to numerous other ports to this port as well; it seems
	  to be a dummy port used for short delays between writes to other
	  ports (used instead of JMP $+2, which no longer delays on Pentium+)
SeeAlso: PORT 00EB"DUMMY"

00EDw  ?W  ???
----------P00EF------------------------------
PORT 00EF - Hyunday Super-NB386S (AMD386sx with Intel chipset)
Warning: any access to this port causes a cold reset on this machine!
----------P00F000F5--------------------------
PORT 00F0-00F5 - PCjr Disk Controller

00F0  ??  disk controller
00F2  ??  disk controller control port
00F4  ??  disk controller status register
00F5  ??  disk controller data port
----------P00F000FF--------------------------
PORT 00F0-00FF - MATH COPROCESSOR (8087..80387)

00F0  -W  math coprocessor clear busy latch (write 00h)
00F1  -W  math coprocessor reset (write 00h)
00F8  RW  opcode transfer (CPU-coprocessor communication)
00FA  RW  opcode transfer
00FC  RW  opcode transfer
----------P00F9------------------------------
PORT 00F9 - Compaq LTE Elite
----------P00FB------------------------------
PORT 00FB - Compaq LTE Elite
----------P00F900FF--------------------------
PORT 00F9-00FF - PC radio by CoZet Info Systems
Range:	The I/O address range is dipswitch selectable from:
	   038-03F and 0B0-0BF
	   078-07F and 0F0-0FF
	   138-13F and 1B0-1BF
	   178-17F and 1F0-1FF
	   238-23F and 2B0-2BF
	   278-27F and 2F0-2FF
	   338-33F and 3B0-3BF
	   378-37F and 3F0-3FF
Notes:	All of these addresses show a readout of FFh in initial state.
	Once started, all of the addresses show	FBh, whatever might happen.
----------P0100------------------------------
PORT 0100 - 3COM 3C509 Ethernet card - ID port
Note: this port is present only on the 3C509, not on any other 3COM card
SeeAlso: PORT 0110h,PORT 0120h
----------P01000107--------------------------
PORT 0100-0107 - PS/2 POS (Programmable Option Select)
Note:	the default value for PORT 0102h is stored in CMOS 31h

0100  R	  POS register 0	Low adapter ID byte
0101  R	  POS register 1	High adapter ID byte
0102  RW  POS register 2	option select data byte 1 (see #P0492)
0103  RW  POS register 3	option select data byte 2 (see #P0493)
0104  RW  POS register 4	option select data byte 3
0105  RW  POS register 5	option select data byte 4
		 bit 7	channel active (-CHCK)
		 bit 6	channel status
0106  RW  POS register 6	Low subaddress extension
0107  RW  POS register 7	High subaddress extension

Bitfields for PS/2 POS register 2, option select data byte 1:
Bit(s)	Description	(Table P0492)
 7	  0  = unidirectional LPT port
	  1  = bidirectional LPT port
 6-5	PS/2 Model 50 and higher
	 00b = default LPT port at 3BCh
	 01b = ""		   378h
	 10b = ""		   278h
	 11b = reserved
 4	enable parallel port
 3	serial port address
	=0 COM2 (02F8h, IRQ3)
	=1 COM1 (03F8h, IRQ4)
 2	enable serial port
 1	enable diskette controller
 0	(MCA) =0 override bits 1,2,4 and disable devices
 0	card enable (CDEN)
 0	=1 VGA sleep bit, disconnects output drivers from VGA (usage for VGA
	  without monitor)
---ET4000---
 7-4	reserved???
 3	video RAM wait enable
 2	ET4000: ROM BIOS wait enable
 1	ET4000: I/O wait enable
Note:	access to this port is only possible when PORT 0094h bit 7 is low.
SeeAlso: #P0493

Bitfields for Chips&Technologies 64200 "Wingine" setup register:
Bit(s)	Description	(Table P0493)
 7	enable access to extended registers (see #P0762)
Note:	on some C&T graphics chips, this register can be made read-only
	  via XR70 (see #P0762)
SeeAlso: #P0492
----------P0100010F--------------------------
PORT 0100-010F - CompaQ Tape drive adapter. alternate address at 0300
----------P0102------------------------------
PORT 0102 - Chips & Technologies 64310 - GLOBAL ENABLE REGISTER
SeeAlso: PORT 0106"Chips"

0102  RW  global enable register (see #P0494)

Bitfields for Chips & Technologies 64310 global enable register:
Bit(s)	Description	(Table P0494)
 7-1	reserved (0)
 0	VGA sleep (used if port 102h bit 1 = 0)
	0 = VGA disabled
	1 = VGA enabled
Note:	Only accessible in setup mode (port 46E8h bit 4 = 1).
SeeAlso: #P0495,#P0492
----------P0106------------------------------
PORT 0106 - Chips & Technologies 64310 - MOTHERBOARD DISABLE REGISTER
SeeAlso: PORT 0102"Chips"

0106  RW  motherboard disable register (see #P0495)

Bitfields for Chips & Technologies 64310 motherboard disable register:
Bit(s)	Description	(Table P0495)
 7-2	reserved (0)
 1	sleep control
	0 = port 102h bit 0 controls VGA sleep (default)
	1 = port 106h bit 0 controls VGA sleep
 0	VGA sleep (used if bit 1 = 1)
	0 = VGA disabled
	1 = VGA enabled
Note:	Only accessible in setup mode (port 46E8h bit 4 = 1),
	  if XR01 bit 2 = 1.
SeeAlso: #P0494
----------P0108010F--------------------------
PORT 0108-010F - IBM PS/2 - 8 digit LED info panel

010F  -W  leftmost character on display
010E  -W  second character
 ...
0108  -W  eighth character
----------P0110------------------------------
PORT 0110 - 3COM 3C509 Ethernet card - ID port (alternate address)
Note:	this port is present only on the 3C509, not on any other 3COM card
SeeAlso: PORT 0100h"3COM",PORT 0120h"3COM"
----------P0120------------------------------
PORT 0120 - 3COM 3C509 Ethernet card - ID port (alternate address)
Note:	this port is present only on the 3C509, not on any other 3COM card
SeeAlso: PORT 0100h"3COM",PORT 0110h"3COM"
----------P0130013F--------------------------
PORT 0130-013F - CompaQ SCSI adapter. alternate address at 0330
----------P01300133--------------------------
PORT 0130-0133 - Adaptec 154xB/154xC SCSI adapter
Range:	four ports at any of 0130, 0134, 0230, 0234, 0330 (default) or 0334
----------P01340137--------------------------
PORT 0134-0137 - Adaptec 154xB/154xC SCSI adapter
Range:	four ports at any of 0130, 0134, 0230, 0234, 0330 (default) or 0334
----------P0138013F--------------------------
PORT 0138-013F - PC radio by CoZet Info Systems
Range:	The I/O address range is dipswitch selectable from:
	   038-03F and 0B0-0BF
	   078-07F and 0F0-0FF
	   138-13F and 1B0-1BF
	   178-17F and 1F0-1FF
	   238-23F and 2B0-2BF
	   278-27F and 2F0-2FF
	   338-33F and 3B0-3BF
	   378-37F and 3F0-3FF
Notes:	All of these addresses show a readout of FFh in initial state.
	Once started, all of the addresses show	FBh, whatever might happen.
---------------------------------------------
Ports List, part 2 of 3
Copyright (c) 1989,1990,1991,1992,1993,1994,1995,1996,1997,1998,1999 Ralf Brown
----------P0140014F--------------------------
PORT 0140-014F - SCSI (alternate Small Computer System Interface) adapter
Note:	first adapter is at 0340-034F
----------P0140014F--------------------------
PORT 0140-014F - Xirlink/Relialogic XL-220/221 SCSI adapter
Range:	alternate address at 0150, 0160, 0170
Notes:	XL-220/221 are based on LOGIC Devices L53C80JC4 SCSI controller which
	  is compatible with Symbios Logic (formaerly NCR) 53C80
	each SCSI data pin is inverted and compared with correcponding bit
	  in the ID select register; if any matches are found while a bus free
	  condition exists and SEL is active, SCSI controller will genarate an
	  interrupt to indicate a selection or reselection
	pseudo-DMA register is provided by some on-card PLM, and decodes any
	  address in the range 01x8-01xF; it should be accessed with 16-bit
	  I/O instructions only causing 2 SCSI REQ/ACK hanshakes (8-bit I/O
	  is treated as 16-bit, and second byte is lost); delayed assertion of
	  the REQ signal or bus free condition on the SCSI bus causes the
	  pseudo-DMA register to prolong ISA I/O cycle not asserting IOCHRDY
	  signal (SCSI phase mismatch doesn't), and so may cause ISA bus to
	  hang in not ready state!
	SCSI BIOS is an 8K ROM located at C8000-CBFFF if I/O port range
	  0140-014F is selected, at CC000-CFFFF if I/O port range 0150-015F
	  is selected, at D8000-DBFFF if I/O port range 0160-016F is selected,
	  and at DC000-DFFFF if I/O port range 0170-017F is selected

0140  R-  current SCSI data bus register
0140  -W  output data register
0141  RW  initiator command register (see #P0496)
0142  RW  mode register (see #P0497)
0143  RW  target command register (see #P0498)
0144  R-  current SCSI control register (see #P0499)
0144  -W  ID select register
0145  R-  DMA status register (see #P0500)
0145  -W  start DMA send register
	  any write starts DMA send
0146  R-  input data register
	  temporarily holds data byte received from the SCSI bus in DMA mode
0146  -W  start DMA target receive register
	  any write starts target mode DMA receive
0147  R-  reset error/interrupt register
	  any read resets the interrupt request latch and the error latches
0147  -W  start DMA initiator mode receive register
	  any write starts initiator mode DMA receive
0148w RW  pseudo-DMA register

Bitfields for initiator command register:
Bit(s)	Description	(Table P0496)
 7	assert RST
 6	(read) arbitration in progress
	(write) test mode
 5	(read) lost arbitration
 4	assert ACK
 3	assert BSY
 2	assert SEL
 1	assert ATN
 0	assert data bus
SeeAlso: #P0497,#P0498,#P0499,#P0500

Bitfields for mode register:
Bit(s)	Description	(Table P0497)
 7	block mode
 6	target mode
 5	enable parity check
 4	enable parity interrupt
 3	enable end of DMA interrupt
 2	monitor BSY
 1	DMA mode
 0	arbitrate
SeeAlso: #P0496

Bitfields for target command register:
Bit(s)	Description	(Table P0498)
 7	(read) last byte sent
 6-4	reserved
 3	assert REQ
 2	assert MSG
 1	assert C/D
 0	assert I/O
SeeAlso: #P0496

Bitfields for current SCSI control register:
Bit(s)	Description	(Table P0499)
 7	RST
 6	BSY
 5	REQ
 4	MSG
 3	C/D
 2	I/O
 1	SEL
 0	parity
SeeAlso: #P0496

Bitfields for DMA status register:
Bit(s)	Description	(Table P0500)
 7	end of DMA
 6	DMA request
 5	parity error
 4	interrupt request
 3	phase match
 2	BSY error
 1	ATN
 0	ACK
SeeAlso: #P0496
----------P0140014F--------------------------
PORT 0140-014F - Future Domain TMC-16x0 SCSI adapter
Range:	alternate address at 0150, 0160, 0170
Notes:	TMC-1650/1670 have a 25-pin external connector, whereas the 1660 and
	  1680 have a SCSI-2 50-pin high-density external connector
	TMC-1670/1680 have floppy disk controller built in
	BIOS versions prior to 3.2 assigned SCSI ID 6 to SCSI adapter,
	  versions 3.2 and greater use SCSI ID 7
	the drive ordering implemented in BIOS versions 3.4 and 3.5 is the
	  opposite of the order (currently) used by the rest of the SCSI
	  industry--for example, under DOS SCSI ID 0 will be D: and SCSI ID 1
	  will be C:
	Future Domain TMC-16x0 SCSI adapter series are based upon Future Domain
	  TMC-1800/18C50/18C30 SCSI controllers
	TMC-1800/18C50/18C30 are ISA SCSI controllers, TMC-36C70 is a PCI
	  version of TMC-18C30
	TMC-1800/18C50 have 8K FIFO, TMC-18C30/36C70 have 2K FIFO
	Future Domain TMC-1650/1660/1670/1680/1610M/1610MER/1610MEX SCSI
	  adapters are based on TMC-1800/18C50/18C30
	Quantum ISA-200S/250MG SCSI adapters are based on TMC-18C50 (?)
	Future Domain TMC-3260 and Adaptec AHA-2920 PCI SCSI adapters are
	  based on TMC-36C70

0140  R-  read SCSI data register
0140  -W  write SCSI data register
0141  R-  SCSI status register (see #P0501)
0141  -W  SCSI control register (see #P0502)
0142  R-  TMC status register (see #P0503)
0142  -W  interrupt control register (see #P0504)
0143  R-  FIFO status register, TMC-18C50/18C30/36C70 chips only
0143  -W  SCSI mode control register (see #P0505)
0144  R-  interrupt condition register, TMC-18C50/18C30/36C70 only (see #P0506)
0144  -W  TMC control register (see #P0507)
0145  R-  ID code LSB register
	  27h for TMC-1800 chip
	  E9h for TMC-18C50/18C30/36C70 chips
0145  -W  memory control register, TMC-18C50/18C30/36C70 only
0146  R-  ID code MSB register
	  60h for TMC-18C50/18C30 chips
	  61h for TMC-1800 chip
0147  R-  read loopback register
0147  -W  write loopback register
0148  RW  SCSI data no ACK register
0149  R-  interrupt status register (see #P0508)
014A  R-  configuration register 1 (see #P0509)
014B  R-  configuration register 2, TMC-18C50/18C30/36C70 only (see #P0510)
014B  -W  I/O control register, TMC-18C30/36C70 only (see #P0511)
014Cw R-  read FIFO data register
014Cw -W  write FIFO data register
014Ew R-  FIFO data count register
Notes:	any value written into the write loopback register can be read back
	  from the read loopback register unchanged (this is used by the BIOS
	  to test the controller)
	reading from read SCSI data register and writing to write SCSI data
	  register causes REQ/ACK handshake to occur automatically, reading
	  and writing the SCSI data no ACK register doesn't
	SCSI FIFO may be used only for DATA IN / DATA OUT phase transfers on
	  TMC-1800; on TMC-18C50/18C30 it may also be used for COMMAND phase
	  transfers

Bitfields for SCSI status register:
Bit(s)	Description	(Table P0501)
 7	not BSY
 6	not MSG
 5	not I/O
 4	not C/D
 3	not REQ
 2	not SEL
 1	parity error???
 0	not ATN
SeeAlso: #P0502,#P0511

Bitfields for SCSI control register:
Bit(s)	Description	(Table P0502)
 7	RST
 6	SEL
 5	BSY
 4	ATN
 3	I/O
 2	C/D
 1	MSG
 0	bus enable
SeeAlso: #P0501,#P0503,#P0504

Bitfields for TMC status register:
Bit(s)	Description	(Table P0503)
 7	bus enabled
 6	parity enabled
 5	FIFO enabled
 4	=1 data are expected to flow out from FIFO to SCSI bus
	=0 data are expected to flow from SCSI bus into FIFO
 3	SCSI reset
 2	???
 1	arbitration complete
 0	interrupt request
SeeAlso: #P0502

Bitfields for interrupt control register:
Bit(s)	Description	(Table P0504)
 7	enable interrupt on REQ
 6	enable interrupt on SEL
 5	enable arbitration interrupt
 4	enable interrupt on ???
 0-3	FIFO threshold (how many 512 byte blocks in FIFO should be
	  full/empty for interrupt to be generated)
SeeAlso: #P0502

Bitfields for SCSI mode control register:
Bit(s)	Description	(Table P0505)
 7	synchronous mode
 6	fast SCSI
 5-4	reserved?
 3-0	synchronous transfer period in 25 ns units
SeeAlso: #P0502

Bitfields for interrupt condition register:
Bit(s)	Description	(Table P0506)
 7	FIFO error interrupt
 6	forced interrupt???
 5	interrupt on RST
 4	arbitration interrupt
 3	interrupt on SEL
 2	interrupt on REQ
 1	interrupt on ???
 0	???
SeeAlso: #P0502

Bitfields for TMC control register:
Bit(s)	Description	(Table P0507)
 7	enable FIFO
 6	=1 data are expected to flow out from FIFO to SCSI bus
	=0 data are expected to flow from SCSI bus into FIFO
 5	clear forced interrupt, TMC-18C50/18C30/36C70 only
 4	enable interrupt
 3	enable parity
 2	arbitrate
 1	force interrupt???
 0	clear SCSI reset flag???
SeeAlso: #P0502
Note:	on the TMC-1800 the FIFO must be enabled and bit 6 must be set
	  according to the expected data direction before a data phase will
	  occur (the TMC-1800 probably doesn't generate interrupts on REQ in
	  DATA IN / DATA OUT phases); on the TMC-18C50/18C30 it may be done
	  when the interrupt on REQ occurs and the SCSI phase is
	  DATA IN, DATA OUT or COMMAND

Bitfields for interrupt status register:
Bit(s)	Description	(Table P0508)
 7	interrupt on REQ enabled
 6	interrupt on SEL enabled
 5	arbitration interrupt enabled
 4	interrupt on ??? enabled
 3	interrupt enabled
 2	???
 1	always set???
 0	???
SeeAlso: #P0502

Bitfields for configuration register 1:
Bit(s)	Description	(Table P0509)
 7-6	BIOS address range
	00 C8000h-C9FFFh
	01 CA000h-CBFFFh
	10 CE000h-CFFFFh
	11 DE000h-DFFFFh
 5-4	I/O address range
	00 140h-14Fh
	01 150h-15Fh
	10 160h-16Fh
	11 170h-17Fh
 3-1	interrupt select
	000 IRQ3
	001 IRQ5
	010 IRQ10
	011 IRQ11
	100 IRQ12
	101 IRQ14
	110 IRQ15
	111 no IRQ
 0	reserved???
Note:	the seven on-board configuration jumpers are read through this register
SeeAlso: #P0502,#P0510

Bitfields for configuration register 2:
Bit(s)	Description	(Table P0510)
 7	32-bit mode enabled (TMC-18C30/36C70 only???)
 6-2	???
 1	RAM disabled (TMC-18C30/36C70 only???)
 0	???
Note:	256 byte on-chip RAM is mapped at offset 1F00h within the BIOS segment
SeeAlso: #P0502,#P0509

Bitfields for TMC control register:
Bit(s)	Description	(Table P0511)
 7	enable 32-bit mode
 6-0	???
SeeAlso: #P0502
--------d-P0140014F--------------------------
PORT 0140-014F - Quantum ISA-200S/250MG SCSI adapter
Range:	alternate address at 0150, 0160, 0170
Note:	Quantum ISA-200S/250MG SCSI adapters are based upon Future Domain
	  TMC-18C50 SCSI controller (???)
SeeAlso: PORT 0140h-014Fh"Future Domain TMC-16x0"
----------P01400157--------------------------
PORT 0140-0157 - RTC (alternate Real Time Clock for XT)	 (1st at 0340-0357)
--------d-P0140015F--------------------------
PORT 0140-015F -  Adaptec AHA-152x SCSI adapter
Range:	alternate address at 0340
----------P0150015F--------------------------
PORT 0150-015F - Xirlink/Relialogic XL-220/221 SCSI adapter
Range:	alternate address at 0140, 0160, 0170
----------P0150015F--------------------------
PORT 0150-015F - Future Domain TMC-16x0 SCSI adapter
Range:	alternate address at 0140, 0160, 0170
--------d-P0150015F--------------------------
PORT 0150-015F - Quantum ISA-200S/250MG SCSI adapter
Range:	alternate address at 0140, 0160, 0170
Note:	Quantum ISA-200S/250MG SCSI adapters are based upon Future Domain
	  TMC-18C50 SCSI controller (???)
SeeAlso: PORT 0140h-014Fh"Future Domain TMC-16x0"
----------P015C015D--------------------------
PORT 015C-015D - Dell Enhanced Parallel Port
SeeAlso: PORT 002Eh,PORT 026Eh,PORT 0398h

015C  -W  index for data port
015D  RW  EPP command data
----------P015F------------------------------
PORT 015F - ARTEC Handyscanner A400Z.  alternate address at 35F.
----------P0160016F--------------------------
PORT 0160-016F - Xirlink/Relialogic XL-220/221 SCSI adapter
Range:	alternate address at 0140, 0150, 0170
----------P0160016F--------------------------
PORT 0160-016F - Future Domain TMC-16x0 SCSI adapter
Range:	alternate address at 0140, 0150, 0170
--------d-P0160016F--------------------------
PORT 0160-016F - Quantum ISA-200S/250MG SCSI adapter
Range:	alternate address at 0140, 0150, 0170
Note:	Quantum ISA-200S/250MG SCSI adapters are based upon Future Domain
	  TMC-18C50 SCSI controller (???)
SeeAlso: PORT 0140h-014Fh"Future Domain TMC-16x0"
----------P0168016F--------------------------
PORT 0168-016F - 4th (Quaternary) EIDE Controller
Range:	01F0-01F7 for primary controller, 0170-0177 for secondary controller
SeeAlso: PORT 0170h-0177h,PORT 01E8h-01EFh,PORT 01F0h-01F7h
----------P01700176--------------------------
PORT 0170-0176 - OPTi "Vendetta" (82C750) CHIPSET - SECONDARY IDE CONTROLLER
Note:	to unlock access to these ports, you must perform two immediately
	  successive 16-bit INs from PORT 0171h, followed by 8-bit OUT of 03h
	  to PORT 172h
SeeAlso: PORT 01F0h"Vendetta"

0170  RW  read cycle timing register (see #P0536)
0171  RW  write cycle timing register (see #P0537)
0172  RW  internal ID register (see #P0538)
0173  RW  control register (see #P0539)
0175  RW  strap register (see #P0540)
0176  RW  miscellaneous register (see #P0541)
----------P01700177--------------------------
PORT 0170-0177 - HDC 2	(2nd Fixed Disk Controller) (ISA, EISA)
Range:	01F0-01F7 for primary controller, 0170-0177 for secondary controller
SeeAlso: PORT 0168h-016Fh,PORT 01E8h-01EFh,PORT 01F0h-01F7h
----------P0170017F--------------------------
PORT 0170-017F - Xirlink/Relialogic XL-220/221 SCSI adapter
Range:	alternate address at 0140, 0150, 0160
----------P0170017F--------------------------
PORT 0170-017F - Future Domain TMC-16x0 SCSI adapter
Range:	alternate address at 0140, 0150, 0160
--------d-P0170017F--------------------------
PORT 0170-017F - Quantum ISA-200S/250MG SCSI adapter
Range:	alternate address at 0140, 0150, 0160
Note:	Quantum ISA-200S/250MG SCSI adapters are based upon Future Domain
	  TMC-18C50 SCSI controller (???)
SeeAlso: PORT 0140h-014Fh"Future Domain TMC-16x0"
----------P01780179--------------------------
PORT 0178-0179 - Power Management
SeeAlso: PORT 0026h,#P0377

0178  -W  index selection for data port
0179  RW  power management data
----------P0178017F--------------------------
PORT 0178-017F - PC radio by CoZet Info Systems
Range:	The I/O address range is dipswitch selectable from:
	   038-03F and 0B0-0BF
	   078-07F and 0F0-0FF
	   138-13F and 1B0-1BF
	   178-17F and 1F0-1FF
	   238-23F and 2B0-2BF
	   278-27F and 2F0-2FF
	   338-33F and 3B0-3BF
	   378-37F and 3F0-3FF
Notes:	All of these addresses show a readout of FFh in initial state.
	Once started, all of the addresses show	FBh, whatever might happen.
----------P01CE01CF--------------------------
PORT 01CE-01CF - ATI Mach32 video chipset - ???

01CE  -W  index register
01CF  RW  data register
----------P01E801EF--------------------------
PORT 01E8-01EF - Headland HL21 & Acer M5105 chipsets - SYSTEM CONTROL

01ED  RW  select internal register. Data to/from 01EF
01EE  R-  ???
01EF  RW  register value
	05h  = 1000xxxx for low CPU clock speed (4MHz on Morse/Mitac)
	     = 0xxxxxxx for high CPU clock speed (16MHz on Morse/Mitac)
	10h memory size
	   bits 2-0 = size
		   (undefined,512K,640K,1024K,2560K,2048K,4096K,undef.)
	14h ???
	   bit 2: 384K RAM of first 1024K relocated to top of memory
----------P01E801EF--------------------------
PORT 01E8-01EF - 3rd (Tertiary) EIDE Controller
Range:	01F0-01F7 for primary controller, 0170-0177 for secondary controller
SeeAlso: PORT 0168h-016Fh,PORT 0170h-0177h,PORT 01F0h-01F7h
----------P01F001F7--------------------------
PORT 01F0-01F7 - HDC 1	(1st Fixed Disk Controller) (ISA, EISA)
Range:	01F0-01F7 for primary controller, 0170-0177 for secondary controller
SeeAlso: PORT 0170h-0177h,PORT 3510h-3513h

01F0  RW  data register
01F1  R-  error register (see #P0512)
01F1  -W  WPC/4	 (Write Precompensation Cylinder divided by 4)
01F2  RW  sector count
01F3  RW  sector number (CHS mode)
	  logical block address, bits 0-7 (LBA mode)
01F4  RW  cylinder low (CHS mode)
	  logical block address, bits 15-8 (LBA mode)
01F5  RW  cylinder high (CHS mode)
	  logical block address, bits 23-16 (LBA mode)
01F6  RW  drive/head (see #P0513)
01F7  R-  status register (see #P0514)
01F7  -W  command register (see #P0515)

Bitfields for Hard Disk Controller error register:
Bit(s)	Description	(Table P0512)
---diagnostic mode errors---
 7	which drive failed (0 = master, 1 = slave)
 6-3	reserved
 2-0	error code
	001	no error detected
	010	formatter device error
	011	sector buffer error
	100	ECC circuitry error
	101	controlling microprocessor error
---operation mode---
 7	bad block detected
 6	uncorrectable ECC error
 5	reserved
 4	ID found
 3	reserved
 2	command aborted prematurely
 1	track 000 not found
 0	DAM not found (always 0 for CP-3022)
SeeAlso: #P0513,#P0514

Bitfields for hard disk controller drive/head specifier:
Bit(s)	Description	(Table P0513)
 7	=1
 6	LBA mode enabled, rather than default CHS mode
 5	=1
 4	drive select (0 = drive 0, 1 = drive 1)
 3-0	head select bits (CHS mode)
	logical block address, bits 27-24 (LBA mode)
SeeAlso: #P0512,#P0514

Bitfields for hard disk controller status register:
Bit(s)	Description	(Table P0514)
 7	controller is executing a command
 6	drive is ready
 5	write fault
 4	seek complete
 3	sector buffer requires servicing
 2	disk data read successfully corrected
 1	index - set to 1 each disk revolution
 0	previous command ended in an error
SeeAlso: #P0512,#P0515

(Table P0515)
Values for hard disk controller command codes:
Command	 Spec	Type	Proto	Description			class:
 00h		opt	nondata	NOP
 08h				device reset
 1xh		opt	nondata	recalibrate			  1
 20h		req	PIOin	read sectors with retry		  1
 21h		req	PIOin	read sectors without retry	  1
 22h		req	PIOin	read long with retry		  1
 23h		req	PIOin	read long without retry		  1
 30h		req	PIOout	write sectors with retry	  2
 31h		req	PIOout	write sectors without retry	  2
 32h		req	PIOout	write long with retry		  2
 33h		req	PIOout	write long without retry	  2
 3Ch	 IDE	opt	PIOout	write verify			  3
 40h		req	nondata	read verify sectors with retry	  1
 41h		req	nondata	read verify sectors without retry 1
 50h		req	vend	format track			  2
 7xh		req	nondata	seek				  1
 8xh	 IDE	vendor	vend	vendor unique 3
 90h		req	nondata	execute drive diagnostics	  1
 91h		req	nondata	initialize drive parameters	  1
 92h		opt	PIOout	download microcode
 94h E0h IDE	opt	nondata	standby immediate		  1
 95h E1h IDE	opt	nondata	idle immediate			  1
 96h E2h IDE	opt	nondata	standby				  1
 97h E3h IDE	opt	nondata	idle				  1
 98h E5h IDE	opt	nondata	check power mode		  1
 99h E6h IDE	opt	nondata	set sleep mode			  1
 9Ah	 IDE	vendor	vend	vendor unique 1
 A0h	 ATAPI			packet command
 A1h	 ATAPI	opt	PIOin	ATAPI Identify			(see #P0524)
 B0h	 SMART	opt		Self Mon., Analysis, Rept. Tech. (see #P0527)
 C0h-C3h IDE	vendor	vend	vendor unique 2
 C4h	 IDE	opt	PIOin	read multiple			  1
 C5h	 IDE	opt	PIOout	write multiple			  3
 C6h	 IDE	opt	nondata	set multiple mode		  1
 C7h	 ATA-4			Read DMA O/Q
 C8h	 IDE	opt	DMA	read DMA with retry		  1
 C9h	 IDE	opt	DMA	read DMA without retry		  1
 CAh	 IDE	opt	DMA	write DMA with retry		  3
 CBh	 IDE	opt	DMA	write DMA w/out retry		  3
 CCh	 ATA-4			Write DMA O/Q
 DAh				get media status
 DBh	 ATA-2	opt	vend	acknowledge media chng		[Removable]
 DCh	 ATA-2	opt	vend	Boot / Post-Boot		[Removable]
 DDh	 ATA-2	opt	vend	Boot / Pre-Boot	(ATA-2)		[Removable]
 DEh	 ATA-2	opt	vend	door lock			[Removable]
 DFh	 ATA-2	opt	vend	door unlock			[Removable]
 E0h-E3h			(second half of commands 94h-96h)
 E4h	 IDE	opt	PIOin	read buffer			  1
 E5h-E6h			(second half of commands 98h-99h)
 E8h	 IDE	opt	PIOout	write buffer			  2
 E9h	 IDE	opt	PIOout	write same			  3
 EAh	 ATA-3	opt		Secure Disable			[Security Mode]
 EAh	 ATA-3	opt		Secure Lock			[Security Mode]
 EAh	 ATA-3	opt		Secure State			[Security Mode]
 EAh	 ATA-3	opt		Secure Enable WriteProt		[Security Mode]
 EBh	 ATA-3	opt		Secure Enable			[Security Mode]
 EBh	 ATA-3	opt		Secure Unlock			[Security Mode]
 ECh	 IDE	req	PIOin	identify drive			  1 (see #P0516)
 EDh	 ATA-2	opt	nondata	media eject			[Removable]
 EEh	 ATA-3	opt		identify device DMA		    (see #P0516)
 EFh	 IDE	opt	nondata	set features			  1 (see #P0535)
 F0h-F4h IDE		vend	EATA standard
 F1h				Security Set Password
 F2h				Security Unlock
 F3h				Security Erase Prepare
 F4h				Security Erase Unit
 F5h-FFh IDE	vendor	vend	vendor unique 4
 F5h				Security Freeze Lock
 F6h				Security Disable Password
SeeAlso: #P0512,#P0514

Format of IDE/ATA Identify Drive information:
Offset	Size	Description	(Table P0516)
 00h	WORD	general configuration (see #P0517)
 02h	WORD	number of logical cylinders
 04h	WORD	reserved
 06h	WORD	number of logical heads
 08h	WORD	vendor-specific (obsolete: unformatted bytes per track)
 0Ah	WORD	vendor-specific (obsolete: unformatted bytes per sector)
 0Ch	WORD	number of logical sectors
 0Eh	WORD	vendor-specific
 10h	WORD	vendor-specific
 12h	WORD	vendor-specific
 14h 10 WORDs	serial number
		no serial number if first word is 0000h
		else blank-padded ASCII serial number
 28h	WORD	vendor-specific
		[buffer type: 01h single-sector, 02h multisector,
		  03h multisector with read cache]
 2Ah	WORD	controller buffer size in 512-byte sectors
		0000h = unspecified
 2Ch	WORD	number of vendor-specific (usually ECC) bytes on
		  Read/Write Long; 0000h = unspecified
 2Eh  4	WORDs	firmware revision
		no revision number if first word is 0000h
		else blank-padded ASCII revision number
 36h 20	WORDs	model number
		no model number if first word is 0000h
		else blank-padded ASCII model string
 5Eh	WORD	read/write multiple support
		bits 7-0: maximum number of sectors per block supported
			00h if read/write multiple not supported
		bits 15-8: vendor-specified
 60h	WORD	able to do doubleword transfers if nonzero
 62h	WORD	capabilities (see #P0518)
 64h	WORD	security mode
		bit 15: security-mode feature set supported
		bits 14-8: maximum number of passwords supported
 66h	WORD	PIO data transfer cycle timing
 68h	WORD	single-word DMA data transfer cycle timing
 6Ah	WORD	field validity
		bit 0: offsets 6Ch-75h valid
		bit 1: offsets 80h-8Dh valid
 6Ch	WORD	logical cylinders in current translation mode
 6Eh	WORD	logical heads in current translation mode
 70h	WORD	logical sectors per track in current translation mode
 72h	DWORD	current capacity in sectors (excluding device-specific uses)
 76h	WORD	multiple-sector support
		bits 7-0: count for read/write multiple command
		bit 8:	multiple-sector setting is valid
 78h	DWORD	total number of user-addressable sectors (LBA mode)
		00000000h if LBA mode not supported
 7Ch	WORD	single-word DMA transfer modes
		low byte is bitmap of supported modes (bit 0 = mode 0, etc.)
		high bytes is bitmap of active mode (bit 8 = mode 0, etc.)
 7Eh	WORD	multiword DMA transfer
		low byte is bitmap of supported modes (bit 0 = mode 0, etc.)
		high byte is bitmap of active mode (bit 8 = mode 0, etc.)
 80h	WORD	supported flow control PIO transfer modes
 82h	WORD	minimum multiword DMA transfer cycle time in ns
 84h	WORD	recommended multiword DMA cycle time in ns
 86h	WORD	minimum non-flow-control PIO transfer cycle time in ns
 88h	WORD	minimum PIO transfer cycle time with IORDY in ns
 8Ah  2 WORDs	reserved for future PIO modes (0)
 8Eh  2 WORDs	reserved (0)
 92h	WORD	command queueing/overlapped operation (see #P0523)
 94h  6 WORDs	reserved (0)
 A0h	WORD	major revision number of specification to which device conforms
		01h = ATA-1, 02h = ATA-2, etc.	0000h/FFFFh = not reported
 A2h	WORD	minor revision number of specification to which device conforms
		0000h/FFFFh = not reported
 A4h	WORD	feature set support 1 (see #P0519)
		(only valid if revision reported in A0h/A2h)
 A6h	WORD	feature set support 2 (see #P0520)
		(only valid if revision reported in A0h/A2h)
 A8h	WORD	(ATA/ATAPI-4) feature set support extension (see #P0521)
 AAh	WORD	feature set enabled 1 (see #P0522)
		(only valid if revision reported in A0h/A2h)
 ACh	WORD	feature set enabled 2 (see #P0520)
		(only valid if revision reported in A0h/A2h)
 AEh	WORD	(ATA/ATAPI-4) feature set enabled extension (see #P0521)
 B0h 42 WORDs	reserved (0)
100h 32 WORDs	vendor-specific
100h	WORD	security status
140h 96 WORDs	reserved (0)
SeeAlso: #P0524,#00267

Bitfields for IDE general configuration:
Bit(s)	Description	(Table P0517)
 15	device class
	=0 ATA device
	=1 ATAPI device
 14	requires format speed tolerance gap
 13	supports track offset option
 12	supports data strobe offset
 11	disk rotational sped tolerance > 0.5%
 10-8	disk transfer rate
	001 <= 5Mbit/sec
	010 5-10 Mbit/sec
	100 > 10Mbit/sec
 7-6	drive type
	01 fixed media
	10 removable media
 5	synchronized drive motor option enabled
 4	head-switching time > 15 microseconds
 3	encoding
	=0 MFM
 2-1	sector type
	01 hard-sectored
	10 soft-sectored
 0	unused (0)
SeeAlso: #P0516

Bitfields for IDE capabilities:
Bit(s)	Description	(Table P0518)
 13	Standby Timer values used according to ATA standard
 11	IORDY supported
 10	device can disable use of IORDY
 9	LBA mode supported
 8	DMA supported
SeeAlso: #P0516

Bitfields for ATA feature set support 1:
Bit(s)	Description	(Table P0519)
 15	Identify Device DMA command is supported
 14	NOP (00h) command is supported
 13	Read Buffer command is supported
 12	Write Buffer command is supported
 11	Write Verify command is supported
 10	host protected area feature set is supported
 9	Device Reset (08h) command is supported
 8	Service interrupt is supported
 7	release interrupt is supported
 6	device supports look-ahead
 5	device supports write cache
 4	PACKET command feature set is supported
 3	power management is supported
 2	removable-media feature set is supported
 1	security feature set is supported
 0	SMART feature set is supported
Note:	values of 0000h and FFFFh indicate that this field is not supported
SeeAlso: #P0516,#P0520,#P0521

Bitfields for ATA feature set support/enabled 2:
Bit(s)	Description	(Table P0520)
 15	must be 0 if this field is supported
 14	must be 1 if this field is supported
 13-2	reserved
 1	Read DMA O/Q (C7h) and Write DMA O/Q (CCh) commands supported/enabled
 0	Download Microcode (92h) command is supported/enabled
SeeAlso: #P0516,#P0522,#P0519,#P0521

Bitfields for ATA feature set support extension:
Bit(s)	Description	(Table P0521)
 15	must be 0 if this field is supported
 14	must be 1 if this field is supported
 13-0	reserved
SeeAlso: #P0516,#P0519,#P0520

Bitfields for ATA feature set enabled 1:
Bit(s)	Description	(Table P0522)
 15	Identify Device DMA command is supported
 14	NOP (00h) command is supported
 13	Read Buffer command is supported
 12	Write Buffer command is supported
 11	Write Verify command is supported
 10	host protected area feature set is supported
 9	Device Reset (08h) command is supported
 8	Service interrupt is enabled
 7	release interrupt is enabled
 6	look-ahead is enabled
 5	write cache is enabled
 4	PACKET command feature set is enabled
 3	power management is enabled
 2	removable-media feature set is enabled
 1	security feature set is enabled
 0	SMART feature set is enabled
SeeAlso: #P0516,#P0520

Bitfields for ATA/ATAPI-4 command queueing/overlapped operation support:
Bit(s)	Description	(Table P0523)
 15	reserved
 14	device supports command queueing
 13	device supports overlapped operation
 12-5	reserved
 4-0	maximum depth of queued commands supported (0 if bit 14 clear)
SeeAlso: #P0516

Format of ATAPI Identify Information:
Offset	Size	Description	(Table P0524)
 00h	WORD	general configuration (see #P0525)
 02h  9 WORDs	???
 14h 10 WORDs	serial number
		no serial number if first word is 0000h
		else blank-padded ASCII serial number
 28h  3 WORDs	vendor-specific
 2Eh  4	WORDs	firmware revision
		no revision number if first word is 0000h
		else blank-padded ASCII revision number
 36h 20	WORDs	model number
		no model number if first word is 0000h
		else blank-padded ASCII model string
 5Eh	WORD	vendor-specific
 60h	WORD	reserved (0)
 62h	WORD	capabilities (see #P0518)
 64h	WORD	security mode???
 66h	WORD	PIO data transfer cycle timing
 68h	WORD	single-word DMA data transfer cycle timing
 6Ah	WORD	field validity
		bit 0: offsets 6Ch-73h valid
		bit 1: offsets 80h-8Dh valid
 6Ch	WORD	??? logical cylinders in current translation mode
 6Eh	WORD	??? logical heads in current translation mode
 70h	WORD	??? logical sectors per track in current translation mode
 72h  2	WORDs	??? current capacity in sectors
 76h	WORD	??? multiple-sector count for read/write multiple command
 78h  2	WORDs	??? total number of user-addressable sectors (LBA mode)
 7Ch	WORD	single-word DMA transfer modes
		low byte is bitmap of supported modes (bit 0 = mode 0, etc.)
		high bytes is bitmap of active mode (bit 8 = mode 0, etc.)
 7Eh	WORD	multiword DMA transfer
		low byte is bitmap of supported modes (bit 0 = mode 0, etc.)
		high bytes is bitmap of active mode (bit 8 = mode 0, etc.)
 80h	WORD	supported flow control PIO transfer modes
 82h	WORD	minimum multiword DMA transfer cycle time
 84h	WORD	recommended multiword DMA cycle time
 86h	WORD	minimum non-flow-control PIO transfer cycle time
 88h	WORD	minimum PIO transfer cycle time with IORDY
 8Ah  2 WORDs	reserved for future PIO modes (0)
 8Eh	WORD	typical time for release when processing overlapped CMD in
		  microseconds
 90h	WORD	???
 92h	WORD	major ATAPI version number
 94h	WORD	minor ATAPI version number
 96h 54 WORDs	reserved (0)
100h 32 WORDs	vendor-specific
140h 96 WORDs	reserved (0)
SeeAlso: #P0516

Bitfields for ATAPI General Configuration:
Bit(s)	Description	(Table P0525)
 15-14	device type
	0x not ATAPI
	10 ATAPI
	11 reserved
 13	reserved
 12	device present (non-ATAPI)
 12-8	ATAPI device type (see #P0526)
 7	device is removable
 6-5	CMD DMA Request type
	00 microprocessor DRQ
	01 interrupt DRQ
	10 accelerated DRQ
	11 reserved
 4-2	reserved
 1-0	CMD packet size (00 = 12 bytes, 01 = 16 bytes)
SeeAlso: #P0524

(Table P0526)
Values for ATAPI device type:
 00h	direct-access device (i.e. disk drive)
 01h	sequential-access device (i.e. tape drive)
 02h	printer
 03h	processor
 04h	write-once device
 05h	CD-ROM
 06h	scanner
 07h	optical memory
 08h	medium changer
 09h	communications device
 0Ah	reserved for ACS IT8
 0Bh	reserved for ACS IT8
 0Ch	array controller device (i.e. RAID)
 0Dh-1Eh reserved
 1Fh	unknown type or no device
SeeAlso: #P0525

(Table P0527)
Values for Self-Monitoring, Analysis, Reporting Technology (SMART) subcommand:
 D0h	Read Attribute Values (optional) (see #P0529)
	results returned in 512-byte sector read from controller
 D1h	Read Attribute Thresholds (optional) (see #P0528)
	results returned in 512-byte sector read from controller
 D2h	Disable Attribute Autosave (optional)
	sector-count register set to 0000h
 D2h	Enable Attribute Autosave
	sector-count register set to 00F1h
 D3h	Save Attribute Values (optional)
 D4h	execute off-line tests immediately (optional)
 D5h-D6h reserved
 D7h	vendor-specific
 D8h	Enable SMART Operations
 D9h	Disable SMART Operations
 DAh	Return SMART Status
	if any threshold(s) exceeded, CylinderLow set to F4h and CylinderHigh
	  set to 2Ch
 DBh	Enable/Disable Automatic Off-Line Data Collection
	sector-count register set to 0000h to disable, 00F8h to enable
 DCh-DFh reserved
 E0h-EFh vendor-specific
Note:	to access SMART commands, the Cylinder Low register must be set to
	  004Fh and the Cylinder High register must be set to 00C2h before
	  invoking the SMART command with the SMART command number in the
	  Features register
SeeAlso: #P0515

Format of S.M.A.R.T. attribute thresholds sector:
Offset	Size	Description	(Table P0528)
 00h	WORD	data structure revision number (0005h for SMART Revision 2.0)
 02h 12 BYTEs	attribute threshold data 1 (see #P0531)
 ...
14Eh 12 BYTEs	attribute threshold data 30 (see #P0531)
16Ah 18 BYTEs	reserved (0)
17Ch 131 BYTEs	vendor-specific
1FFh	BYTE	checksum (two's complement of eight-bit sum of first 511 bytes)
Note:	if the drive provides fewer than 30 attributes, all remaining attribute
	  records are filled with NUL (00h) bytes
SeeAlso: #P0527,#P0529

Format of S.M.A.R.T. attribute values sector:
Offset	Size	Description	(Table P0529)
 00h	WORD
 02h 12 BYTEs	attribute value data 1 (see #P0532)
 ...
14Eh 12 BYTEs	attribute value data 30 (see #P0532)
16Ah	BYTE	off-line data collection status (see #P0533)
16Bh	BYTE	vendor-specific
16Ch	WORD	time to complete off-line data collection, in seconds
		0001h-FFFFh
16Eh	BYTE	vendor-sepcific
16Fh	BYTE	off-line data collection capability (see #P0534)
170h	WORD	S.M.A.R.T. capabilities (see #P0530)
172h 16 BYTEs	reserved (0)
182h 125 BYTEs	vendor-specific
1FFh	BYTE	checksum (two's complement of eight-bit sum of first 511 bytes)
Note:	if the drive provides fewer than 30 attributes, all remaining attribute
	  records are filled with NUL (00h) bytes
SeeAlso: #P0527,#P0528

Bitfields for S.M.A.R.T capabilities:
Bit(s)	Description	(Table P0530)
 0	attributes saved on going into power-saving mode
 1	Enable/Disable Attribute Autosave subcommands are supported
 2-15	reserved
SeeAlso: #P0529

Format of S.M.A.R.T. attribute threshold:
Offset	Size	Description	(Table P0531)
 00h	BYTE	attribute ID (01h-FFh)
 01h	BYTE	attribute threshold
		00h always passing
		01h minimum threshold value
		FDh maximum threshold value
		FEh invalid (do not use)
		FFh always failing (for testing)
 02h 10 BYTEs	reserved (0)
Note:	the attribute ID and actual threshold values are vendor-specific
SeeAlso: #P0528,#P0532

Format of S.M.A.R.T attribute value:
Offset	Size	Description	(Table P0532)
 00h	BYTE	attribute ID (01h-FFh)
 01h	WORD	status flags
		bit 0: pre-failure/advisory
			=0 value < threshold indicates usage/age exceeding
				  design life
			=1 value < threshold indicates pre-failure condition
		bit 1: on-line data collection
		bits 2-5 vendor-specific
		bits 6-15 reserved
 03h	BYTE	attribute value (01h-FDh)
		initial value prior to data collection is 64h
 04h  8 BYTEs	vendor-specific
SeeAlso: #P0529,#P0531

(Table P0533)
Values for S.M.A.R.T. off-line data collection status:
 00h	off-line collection never started
 01h	reserved
 02h	off-line data collection completed successfully
 03h	reserved
 04h	off-line data collection suspended by command from host
 05h	off-line data collection aborted by command from host
 06h	off-line data collection aborted due to fatal error
 07h-3Fh reserved
 40h-7Fh vendor-specific
 80h	off-line collection never started (auto-offline feature enabled)
 81h	reserved
 82h	off-line data collection completed successfully (auto-offline feature
	  enabled)
 83h	reserved
 84h	off-line data collection suspended by command from host (auto-offline
	  feature enabled)
 85h	off-line data collection aborted by command from host (auto-offline
	  feature enabled)
 86h	off-line data collection aborted due to fatal error (auto-offline
	  feature enabled)
 87h-BFh reserved
 C0h-FFh vendor-specific
SeeAlso: #P0529,#P0534

Bitfields for S.M.A.R.T. off-line data collection capabilities:
Bit(s)	Description	(Table P0534)
 0	Execute Off-Line Immediate (D4h) subcommand is implemented
 1	Enable/Disable Automatic Off-Line subcommand is implemented
 2	abort/resume on interrupting command
	=0 off-line resumes automatically after an interrupting command
	=1 off-line collection is aborted by an interrupting command
 3-7	reserved
SeeAlso: #P0527

(Table P0535)
Values for Feature Code:
 01h	[opt] 8-bit instead of 16-bit data transfers
 02h	[opt] enable write cache
 03h	      set transfer mode as specified by Sector Count register
 04h	[opt] enable all automatic defect reassignment
 22h	[opt] Write Same, user-specified area
 33h	[opt] disable retries
 44h	      specify length of ECC bytes used by Read Long and Write Long
 54h	[opt] set cache segments (value in Sector Count register)
 55h	      disable look-ahead
 66h	      disable reverting to power-on defaults
 77h	[opt] disable ECC
 81h	[opt] 16-bit instead of 8-bit data transfers
 82h	[opt] disable write cache
 84h	[opt] disable all automatic defect reassignment
 88h	[opt] enable ECC
 99h	[opt] enable retries
 9Ah	[opt] set device maximum average current
 AAh	      enable look-ahead
 ABh	[opt] set maximum prefecth (value in Sector Count register)
 BBh	      use four bytes of ECC on Read Long and Write Long (for compat.)
 CCh	      enable reverting to power-on defaults
 DDh	[opt] Write Same, entire disk
SeeAlso: #00266
----------P01F001F6--------------------------
PORT 01F0-01F6 - OPTi "Vendetta" (82C750) CHIPSET - PRIMARY IDE CONTROLLER
Note:	to unlock access to these ports, you must perform two immediately
	  successive 16-bit INs from PORT 01F1h, followed by 8-bit OUT of 03h
	  to PORT 1F2h
SeeAlso: PORT 0170h"Vendetta",PORT 01F0h"HDC 1"

01F0  RW  read cycle timing register (see #P0536)
01F1  RW  write cycle timing register (see #P0537)
01F2  RW  internal ID register (see #P0538)
01F3  RW  control register (see #P0539)
01F5  RW  strap register (see #P0540)
01F6  RW  miscellaneous register (see #P0541)

Bitfields for OPTi "Vendetta" IDE controller read cycle timing register:
Bit(s)	Description	(Table P0536)
 7-4	DRD# pulse width - 1 LCLKs on 16-bit IDE data register read
 3-0	recovery time between DRD# and DA2-0/DCSx# - 2 LCLKs after 16-bit IDE
	  data register read
Notes:	if register 1F6h/176h bit 0 = 0, controls drive selected by
	  register 1F3h/173h bits 3-2
	if register 1F6h/176h bit 0 = 1, controls drive not selected by
	  register 1F3h/173h bits 3-2, if register 1F3h/173h bit 7 = 1
SeeAlso: #P0537,#P0538,#P0539

Bitfields for OPTi "Vendetta" IDE controller write cycle timing register:
Bit(s)	Description	(Table P0537)
 7-4	DWR# pulse width - 1 LCLKs on 16-bit IDE data register write
 3-0	recovery time between DWR# and DA2-0/DCSx# - 2 LCLKs after 16-bit IDE
	  data register write
Notes:	if register 1F6h/176h bit 0 = 0, controls drive selected by
	  register 1F3h/173h bits 3-2
	if register 1F6h/176h bit 0 = 1, controls drive not selected by
	  register 1F3h/173h bits 3-2, if register 1F3h/173h bit 7 = 1
SeeAlso: #P0536,#P0539

Bitfields for OPTi "Vendetta" IDE controller internal ID register:
Bit(s)	Description	(Table P0538)
 7	controller register access disable (write-only)
 6	controller register access disable until power-down or reset
	  (write-only)
 5-2	reserved (read-only)
 1-0	reserved (11, otherwise all controller register writes blocked)
SeeAlso: #P0540

Bitfields for OPTi "Vendetta" IDE controller control register:
Bit(s)	Description	(Table P0539)
 7	enable 1F0h-1F1h/170h-171h and 1F6h/176h bits 5-1 cycle timing
	  set for drive not selected by 1F3h/173h bits 3-2
 6-5	reserved (read-only)
 4	(primary IDE controller) minimum read wait states
	0 = 2 wait states
	1 = 1 wait states
	(secondary IDE controller) reserved
 3	enable 1F0h-1F1h/170h-171h cycle timing set for drive 1
 2	enable 1F0h-1F1h/170h-171h cycle timing set for drive 0
 1	reserved
 0	reserved (1) (read-only)
SeeAlso: #P0540,#P0541

Bitfields for OPTi "Vendetta" IDE controller strap register:
Bit(s)	Description	(Table P0540)
 7	reserved (1) (read-only)
 6-5	revision number (read-only)
	11 = chip revision in PCI configuration register 08h (see #00878)
	  (see #00931)
 4	(primary IDE controller) DINTR state (read-only)
	(secondary IDE controller) SDINTR state (read-only)
 3-2	(primary IDE controller only) IDE device cycle time (read-only)
	value determined by PCI config register 40h bits 1-0 (see #00931)
 1	reserved (1) (read-only)
 0	(primary IDE controller only) PCI CLK
	0 = 33 MHz
	1 = 25 MHz
SeeAlso: #P0539,#P0541,#P0538

Bitfields for OPTi "Vendetta" IDE controller miscellaneous register:
Bit(s)	Description	(Table P0541)
 7	reserved
 6	read prefetch enable
 5-4	address setup time between DRD#/DWR# active and
	  DA2-0/DCS3#/DCS1# - 1 LCLKs
 3-1	minimum number of LCLKs between DRDY# high and DRD#/DRW# inactive - 2
 0	cycle timing register switch (1F0h/170h and 1F1h/171h)
SeeAlso: #P0539,#P0540
----------P01F8------------------------------
PORT 01F8 - ???

01F8  RW  ???
		bit 0: A20 gate control (set = A20 enabled, clear = disabled)
----------P01F901FF--------------------------
PORT 01F9-01FF - PC radio by CoZet Info Systems
Range:	The I/O address range is dipswitch selectable from:
	   038-03F and 0B0-0BF
	   078-07F and 0F0-0FF
	   138-13F and 1B0-1BF
	   178-17F and 1F0-1FF
	   238-23F and 2B0-2BF
	   278-27F and 2F0-2FF
	   338-33F and 3B0-3BF
	   378-37F and 3F0-3FF
Notes:	All of these addresses show a readout of FFh in initial state.
	Once started, all of the addresses show	FBh, whatever might happen.
--------d-P0200------------------------------
PORT 0200 - Digidesign 'Session 8' HARD-DISK RECORDING SYSTEM
SeeAlso: PORT 0300h"Digidesign"
----------P0200020F--------------------------
PORT 0200-020F - Game port reserved I/O address space
0200-0207 - Game port, eight identical addresses on some boards

0201  R-  read joystick position and status (see #P0542)
0201  -W  fire joystick's four one-shots
0201  RW  gameport on mc-soundmachine, mc 03-04/1992: Adlib-compatible,
		Covox 'voice master' & 'speech thing' compatible soundcard.
		(enabled if bit1=1 in PORT 038Fh. Because it is disabled on
		power-on, it cannot be found by BIOS) (see PORT 0388h-038Fh)

Bitfields for joystick position and status:
Bit(s)	Description	(Table P0542)
 7	status B joystick button 2 / D paddle button
 6	status B joystick button 1 / C paddle button
 5	status A joystick button 2 / B paddle button
 4	status A joystick button 1 / A paddle button
 3	B joystick Y coordinate	   / D paddle coordinate
 2	B joystick X coordinate	   / C paddle coordinate
 1	A joystick Y coordinate	   / B paddle coordinate
 0	A joystick X coordinate	   / A paddle coordinate
----------P020002FF--------------------------
PORT 0200-02FF - Sunshine uPW48, programmer for EPROM version CPU's 8748/8749
Range:	4 bit DIP switch installable in the range 20x-2Fx

0200-0203	adresses of the 8255 on the uPW48
0208-020B	adresses of ??? on the uPW48 (all showing zeros)
----------P02080209--------------------------
PORT 0208-0209 - Intel 82C212B "Neat" chipset - EMS emulation control
Range:	may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, 02E8
----------P0208020A--------------------------
PORT 0208-020A - Chips&Technologies 82C235 "SCAT" chipset - EMS PAGE REGISTERS
Range:	PORT 0208h or PORT 0218h, depending on configuration register 4Fh
	  (see #P0067)
SeeAlso: PORT 0022h"82C235"

0208  RW  EMS page register
0209  RW  EMS page register
020A  RW  EMS page register
----------P020C020F--------------------------
PORT 020C-020F - AIMS LAB PC Radio
Range:	configurable to PORT 020Ch or PORT 030Ch
Notes:	writing a value with bit 3 set to one of these ports turns on the
	  radio; writing a value with bit 3 clear turns it off
	PORT 020Eh bits 1 indicates status of some kind
----------P02100217--------------------------
PORT 0210-0217 - Expansion unit (XT)

0210  -W  latch expansion bus data
0210  R-  verify expansion bus data
0211  -W  clear wait, test latch
0211  R-  High byte data address
0212  R-  Low byte data address
0213  -W  0=enable,  1=disable expansion unit
0214  -W  latch data  (receiver card port)
0214  R-  read data   (receiver card port)
0215  R-  High byte of address, then Low byte	(receiver card port)
----------P02100211--------------------------
PORT 0210-0211 - Game Blaster
Range:	PORT 02x0h-02x1h, x=1,2,...

0210  -W  register index
0211  ?W  register data
----------P02180219--------------------------
PORT 0218-0219 - Intel 82C212B "Neat" chipset - EMS emulation control
Range:	base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P0218021A--------------------------
PORT 0218-021A - Chips&Technologies 82C235 "SCAT" chipset - EMS PAGE REGISTERS
Range:	PORT 0208h or PORT 0218h, depending on configuration register 4Fh
	  (see #P0067)
SeeAlso: PORT 0022h"82C235"

0218  RW  EMS page register
0219  RW  EMS page register
021A  RW  EMS page register
----------P02200223--------------------------
PORT 0220-0223 - Sound Blaster / Adlib port (Stereo)
SeeAlso: PORT 0388h-0389h

0220  R-  Left speaker -- Status port
0220  -W  Left speaker -- Address port
0221  -W  Left speaker -- Data port
0222  R-  Right speaker -- Status port
0222  -W  Right speaker -- Address port
0223  -W  Right speaker -- Data port
----------P02200227--------------------------
PORT 0220-0227 - Soundblaster PRO and SSB 16 ASP
----------P02200228--------------------------
PORT 0220-0228 - C&T 82C570 CHIPSlink '3270' Protocol Controller
!!!chips\82c570.pdf p.7
----------P0220022F--------------------------
PORT 0220-022F - Soundblaster PRO 2.0
----------P0220022F--------------------------
PORT 0220-022F - Soundblaster PRO 4.0
Note:	the FM music is accessible on 0388/0389 for compatibility.

0220  R-  left FM status port
0220  -W  left FM music register address port (index)
0221  RW  left FM music data port
0222  R-  right FM status port
0222  -W  right FM music register address port (index)
0223  RW  right FM music data port
0224  -W  mixer register address port (index) (see #P0543)
0225  RW  mixer data port
0226  -W  DSP reset
0228  R-  FM music status port
0228  -W  FM music register address port (index)
0229  -W  FM music data port
022A  R-  DSP read data (voice I/O and Midi)
022C  -W  DSP write data / write command
022C  R-  DSP write buffer status (bit 7)
022E  R-  DSP data available status (bit 7)

(Table P0543)
Values for SB Mixer register index:
 Index	Description		PORT 0225h data
 00h	reset			00h = zero all mixer controls
 04h	voice select		high nybble = left, low nybble = right
 0Ah	microphone gain		bits 2-0 = gain
 22h	master gain		high nybble = left, low nybble = right
 26h	MIDI gain		high nybble = left, low nybble = right
 28h	CD gain			high nybble = left, low nybble = right
 2Eh	Line In			high nybble = left, low nybble = right
 30h	Master Left		bits 7-3 = volume
 31h	Master Right		bits 7-3 = volume
 32h	Voice Left		bits 7-3 = volume
 33h	Voice Right		bits 7-3 = volume
 34h	MIDI Left		bits 7-3 = volume
 35h	MIDI Right		bits 7-3 = volume
 36h	CD Left			bits 7-3 = volume
 37h	CD Right		bits 7-3 = volume
 38h	LineIn Left		bits 7-3 = volume
 39h	LineIn Right		bits 7-3 = volume
 3Ah	Microphone		bits 7-3 = gain
 3Bh	PC speaker		bits 7-3 = volume
 3Ch	Sound Output		highest set bit is enabled source (see #P0544)
 3Dh	Sound Source (left)	highest set bit is enabled source (see #P0544)
 3Eh	Sound Source (right)	highest set bit is enabled source (see #P0544)
 40h	In gain			bits 7-6 = gain
				   (00 = x1, 01 = x2, 10 = x4, 11 = x8)
 41h	Out gain (left)		bits 7-6 = gain (as for In)
 42h	Out gain (right)	bits 7-6 = gain (as for In)
 43h	Automatic Gain Control	bit 0 = enable
 44h	Treble (left)		bits 7-3 = volume
 45h	Treble (right)		bits 7-3 = volume
 46h	Bass (left)		bits 7-3 = volume
 47h	Bass (right)		bits 7-3 = volume

Bitfields for SB Mixer sound source:
Bit(s)	Description	(Table P0544)
 7	PC speaker???
 6	MIDI left
 5	MIDI right
 4	LineIn left
 3	LineIn right
 2	CD left
 1	CD right
 0	microphone		
Note:	bits 7-5 are ignored for Sound Output register
SeeAlso: #P0543
----------P022B------------------------------
PORT 022B - GI1904 Scanner Interface Adapter
Range:	PORT 026Bh, PORT 02ABh (default), PORT 02EBh, PORT 032Bh, PORT 036Bh
Range:	PORT 03ABh, PORT 03EBh
----------P022C------------------------------
PORT 022C - GS-IF Scanner Interface adapter
Range:	PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
	  PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:	many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
	  others use this interface
----------P022F------------------------------
PORT 022F - mc-soundmachine, mc 03-04/1992 - SPEECH I/O
Note:	An Adlib-compatible Covox 'voice master' & 'speech thing' compatible
	  soundcard
SeeAlso: PORT 0378h"Covox",PORT 0388h-038Fh"soundmachine"

022F  RW  Covox compatible speech I/O  (via internal A/D converter,
		each read access starts a new conversion cycle)
		register enabled if bit7=1 in PORT 038Fh
----------P02300233--------------------------
PORT 0230-0233 - Adaptec 154xB/154xC SCSI adapter.
Range:	four ports at any of 0130, 0134, 0230, 0234, 0330 (default) or 0334
----------P02340237--------------------------
PORT 0234-0237 - Adaptec 154xB/154xC SCSI adapter.
Range:	four ports at any of 0130, 0134, 0230, 0234, 0330 (default) or 0334
----------P0238023F--------------------------
PORT 0238-023F - COM port addresses on UniRAM card by German magazine c't
		selectable from 238, 2E8, 2F8, 338, 3E0, 3E8, 3F8
----------P0238023B--------------------------
PORT 0238-023B - Bus Mouse Port (secondary address)
InstallCheck: read the ID Port twice; if installed, the first byte
	  returned will be DEh, and the second will vary by card
	  (revision number???)
Note:	secondary address for bus mice from MS and Logitech, and the ATI
	  video adapter mouse
SeeAlso: PORT 023Ch"Mouse"

0238  ?W  Command port
0239  ?W  Data port
023A  R?  ID Port 
----------P023C023F--------------------------
PORT 023C-023F - Bus Mouse Port (primary address)
InstallCheck: read the ID Port twice; if installed, the first byte
	  returned will be DEh, and the second will vary by card
	  (revision number???)
Note:	primary address for bus mice from MS and Logitech, the ATI video
	  adapter mouse, and the Commodore PC30III bus mouse
SeeAlso: PORT 0238h"Mouse"

023C  ?W  Command port
023D  ?W  Data port
023E  R?  ID Port 
----------P0240024F--------------------------
PORT 0240-024F - Gravis Ultra Sound by Advanced Gravis
Range:	The I/O address range is dipswitch selectable from:
	   0200-020F and 0300-030F
	   0210-021F and 0310-031F
	   0220-022F and 0320-032F
	   0230-023F and 0330-033F
	   0240-024F and 0340-034F
	   0250-025F and 0350-035F
	   0260-026F and 0360-036F
	   0270-027F and 0370-037F
SeeAlso: PORT 0340h-034Fh,PORT 0746h

0240  -W  Mix Control register (see #P0545)
0241  R-  Read Data
0241  -W  Trigger Timer
0246  R-  IRQ Status Register (see #P0546)
0248  RW  Timer Control Reg
	  Same as ADLIB Board (see PORT 0200h)
0249  -W  Timer Data (see #P0547)
024B  -W  IRQ Control Register (0240 bit 6 = 1) (see #P0548)
024B  -W  DMA Control Register (0240 bit 6 = 0) (see #P0549)
024F  RW  Register Controls (rev 3.4+)

Bitfields for Gravis Ultra Sound mix control register:
Bit(s)	Description	(Table P0545)
 6	   Control Register Select (see 024B)
 5	   Enable MIDI Loopback
 4	   Combine GF1 IRQ with MIDI IRQ
 3	   Enable Latches
 2	   Enable MIC IN
 1	   Disable LINE OUT
 0	   Disable LINE IN
SeeAlso: #P0546

Bitfields for Gravis Ultra Sound IRQ status register:
Bit(s)	Description	(Table P0546)
 7	   DMA TC IRQ
 6	   Volume Ramp IRQ
 5	   WaveTable IRQ
 3	   Timer 2 IRQ
 2	   Timer 1 IRQ
 1	   MIDI Receive IRQ
 0	   MIDI Transmit IRQ
SeeAlso: #P0545,#P0548,#P0549

Bitfields for Gravis Ultra Sound timer data:
Bit(s)	Description	(Table P0547)
 7	   Reset Timr IRQ
 6	   Mask Timer 1
 5	   Mask Timer 2
 1	   Timer 2 Start
 0	   Timer 1 Start
SeeAlso: #P0546,#P0548

Bitfields for Gravis Ultra Sound IRQ control register:
Bit(s)	Description	(Table P0548)
 6	Combine Both IRQ
 5-3	MIDI IRQ Selector
	000  No IRQ
	001  IRQ 2
	010  IRQ 5
	011  IRQ 3
	100  IRQ 7
	101  IRQ 11
	110  IRQ 12
	111  IRQ 15
 2-0	GF1 IRQ Selector
	000  No IRQ
	001  IRQ 2
	010  IRQ 5
	011  IRQ 3
	100  IRQ 7
	101  IRQ 11
	110  IRQ 12
	111  IRQ 15
SeeAlso: #P0546,#P0549

Bitfields for Gravis Ultra Sound DMA Control Register:
Bit(s)	Description	(Table P0549)
 6	Combine Both DMA
 5-3	DMA Select Register 2
	000  No DMA
	001  DMA 1
	010  DMA 3
	011  DMA 5
	100  DMA 6
	101  DMA 7
 2-0	DMA Select Register 1
	000  No DMA
	001  DMA 1
	010  DMA 3
	011  DMA 5
	100  DMA 6
	101  DMA 7
SeeAlso: #P0546,#P0548,#P0591
----------P02400257--------------------------
PORT 0240-0257 - RTC (alternate Real Time Clock for XT)	 (1st at 0340-0357)
		(used by TIMER.COM v1.2 which is the 'standard' timer program)
----------P02580259--------------------------
PORT 0258-0259 - Intel 82C212B "Neat" chipset - EMS emulation control
Range:	base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P02580259--------------------------
PORT 0258-0259 - AT RAMBANK Memory Expansion Board - EXT MEMORY AND EMS-SUPPORT
Range:	base address may be set to 0218h, 0228h, 0238h, 0258h, 0268h, 0298h,
	  or 02A8h
----------P0258025F--------------------------
PORT 0258-025F - Intel Above Board
----------P02600268--------------------------
PORT 0260-0268	-  LPT port address on the UniRAM card by German magazine c't
		selectable from 260, 2E0, 2E8, 2F0, 3E0, 3E8.
----------P02680269--------------------------
PORT 0268-0269 - Intel 82C212B "Neat" chipset - EMS emulation control
Range:	base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P026B------------------------------
PORT 026B - GI1904 Scanner Interface Adapter
Range:	PORT 022Bh, PORT 02ABh (default), PORT 02EBh, PORT 032Bh, PORT 036Bh
Range:	PORT 03ABh, PORT 03EBh
----------P026C------------------------------
PORT 026C - GS-IF Scanner Interface adapter
Range:	PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
	  PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:	many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
	  others use this interface
----------P026E026F--------------------------
PORT 026E-026F - Dell Enhanced Parallel Port
SeeAlso: PORT 002Eh,PORT 015Ch,PORT 0398h

026E  -W  index for data port
026F  RW  EPP command data
----------P026E026F--------------------------
PORT 026E-026F - Intel 82091AA Advanced Integrated Peripheral
Range:	PORT 0022h (X-Bus), PORT 0024h (X-Bus), PORT 026Eh (ISA), or
	  PORT 0398h (ISA)
SeeAlso: PORT 0022h"82091AA",PORT 0024h"82091AA",PORT 0398h"82091AA"

026E  ?W  configuration register index
026F  RW  configuration register data
----------P0278------------------------------
PORT 0278 - Covox 'Speech Thing' COMPATIBLES
SeeAlso: PORT 022Fh"Covox",PORT 0388h-038Fh"soundmachine"

0278  -W  speech data output via printer data port
		(with mc-soundmachine, enabled if bit5=1 in 38F)
----------P0278027A--------------------------
PORT 0278-027A - PARALLEL PRINTER PORT (usually LPT1, sometimes LPT2)
Range:	usually PORT 03BCh, PORT 0278h, or PORT 0378h
SeeAlso: PORT 0278h"EPP",MEM 0040h:0008h,INT 17/AH=00h

0278  -W  data port
0279  R-  status port (see #P0658 at PORT 03BCh)
027A  RW  control port (see #P0659 at PORT 03BCh)
----------P0278027F--------------------------
PORT 0278-027F - Intel 82360SL/82091AA - EPP-mode PARALLEL PORT
Range:	PORT 0278h or PORT 0378h
SeeAlso: PORT 0278h"LPT1",PORT 0678h"ECP"

0278-027A	as for standard parallel port
027B  RW  address strobe
027C  RW  data strobe 0
027D  RW  data strobe 1
027E  RW  data strobe 2
027F  RW  data strobe 3
----------P0279------------------------------
PORT 0279 - Plug-and-Play - CONFIGURATION REGISTER
SeeAlso: PORT 0A79h

0279  -W  index into Plug-and-Play register set for Read Data Port and
	  Write Data Port I/O (see #P0550,#P0551)

(Table P0550)
Values for Plug-and-Play Card-Level Registers:
 00h	set Read Port address
	bits 9-2 of Read Data port address (bits 15-10 are always 0, bits 1-0
	  are always 11); valid Read Port addresses are 0203h-03FFh
 01h	serial isolation
 02h	configuration control
 03h	Wake command
	(specifies which card is accessed through configuration registers)
 04h	resource data
 05h	status
 06h	Card Select Number (CSN)
 07h	logical device number
	(selects which logical device on card is accessed at locations 30h-FFh)
	(see #P0551)
 08h-1Fh reserved
 20h-2Fh vendor-specific
Note:	there is one set of these registers per installed card
SeeAlso: #P0551

(Table P0551)
Values for Plug-and-Play Logical Device Registers:
 30h	activate
	bit 0: device is active on ISA bus
	bits 7-1: reserved (0)
 31h	I/O range check
	bit 0: I/O Read Pattern select (if bit 1 set, then I/O reads return
		55h if this bit is set, AAh if this bit is clear)
	bit 1: I/O Range Check Enable: if set, all reads from device I/O
		  registers return 55h or AAh, depending on bit 0
	bits 7-2: reserved (0)
 32h-37h reserved
 38h-3Fh vendor-specific
 40h-44h 24-bit ISA memory descriptor 0
 45h-47h reserved
 48h-4Ch 24-bit ISA memory descriptor 1
 4Dh-4Fh reserved
 50h-54h 24-bit ISA memory descriptor 2
 55h-57h reserved
 58h-5Ch 24-bit ISA memory descriptor 3
 5Dh-5Fh reserved
 60h-6Fh I/O configuration registers 0-7
 70h-71h IRQ channel select 0
 72h-73h IRQ channel select 1
 74h-75h DMA configuration registers 0-1
 76h-7Eh 32-bit memory range configuration register 0
 7Fh	 reserved
 80h-88h 32-bit memory range configuration register 1
 89h-8Fh reserved
 90h-98h 32-bit memory range configuration register 2
 99h-9Fh reserved
 A0h-A8h 32-bit memory range configuration register 3
 A9h-EFh reserved for logical device configuration
 F0h-FEh vendor-specific
 FFh	reserved
Note:	there is one set of these registers per logical device
SeeAlso: #P0550
----------P0280------------------------------
PORT 0280 - LCD display on Wyse 2108 PC
----------P02800288--------------------------
PORT 0280-0288	- non-standard COM port addresses (V20-XT by German magazine c't)
		selectable from 0280, 0288, 0290, 0298, 6A0, 6A8
--------s-P02800283--------------------------
PORT 0280-0283 - Pro Audio Spectrum 16 (PAS16)
Range:	PORT 0280h, PORT 0284h, PORT 0288h, PORT 028Ch, PORT 384h,
	  PORT 0388h (default), or PORT 038Ch
----------P0288028F--------------------------
PORT 0288-028F	- non-standard COM port addresses (V20-XT by German magazine c't)
0280-0288	selectable from 0280, 0288, 0290, 0298, 06A0, 06A8
0290-0298
0298-029F
--------s-P02840287--------------------------
PORT 0284-0287 - Pro Audio Spectrum 16 (PAS16)
Range:	PORT 0280h, PORT 0284h, PORT 0288h, PORT 028Ch, PORT 384h,
	  PORT 0388h (default), or PORT 038Ch
--------s-P0288028F--------------------------
PORT 0288-028F - Pro Audio Spectrum 16 (PAS16)
Range:	PORT 0280h, PORT 0284h, PORT 0288h, PORT 028Ch, PORT 384h,
	  PORT 0388h (default), or PORT 038Ch
--------s-P028C028F--------------------------
PORT 028C-028F - Pro Audio Spectrum 16 (PAS16)
Range:	PORT 0280h, PORT 0284h, PORT 0288h, PORT 028Ch, PORT 384h,
	  PORT 0388h (default), or PORT 038Ch
----------P02A002A7--------------------------
PORT 02A0-02A7 - Sunshine EW-901BN, EW-904BN
		EPROM writer card (release 1986) for EPROMs up to 27512
02A0-02A3	adresses of the 8255 on the EW-90xBN
----------P02A202A3--------------------------
PORT 02A2-02A3 - MSM58321RS clock
----------P02A802A9--------------------------
PORT 02A8-02A9 - Intel 82C212B "Neat" chipset - EMS emulation control
Range:	base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P02AB------------------------------
PORT 02AB - GI1904 Scanner Interface Adapter (default)
Range:	PORT 022Bh, PORT 026Bh, PORT 02EBh, PORT 032Bh, PORT 036Bh
Range:	PORT 03ABh, PORT 03EBh
Note:	the GI1904 is used by many SPI 400/800dpi gray/halftone/color handy
	  scanners by Marstek, Mustek, Conrad, V”lkner and others
----------P02AC------------------------------
PORT 02AC - GS-IF Scanner Interface adapter
Range:	PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
	  PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:	many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
	  others use this interface
----------P02B002BF--------------------------
PORT 02B0-02BF - Trantor SCSI adapter
----------P02B002DF--------------------------
PORT 02B0-02DF - alternate EGA,	primary EGA at 03C0
----------P02B802B9--------------------------
PORT 02B8-02B9 - Intel 82C212B "Neat" chipset - EMS emulation control
Range: base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P02C002Cx--------------------------
PORT 02C0-02Cx - AST-clock
----------P02C002DF--------------------------
PORT 02C0-02DF - XT-Real Time Clock 2 (default jumpered address)
----------P02C002CF--------------------------
PORT 02C0-02CF - EGA (2nd adapter)
SeeAlso: PORT 03C0h
--------V-P02C602C9--------------------------
PORT 02C6-02C9 - VGA/MCGA - DAC REGISTERS (alternate address)
Range:	PORT 03C6h or PORT 02C6h (alternate)
SeeAlso: PORT 03C6h
----------P02D002DA--------------------------
PORT 02D0-02DA - C&T 82C570 CHIPSlink '3270' Protocol Controller
!!!chips\82c570.pdf p.12
----------P02E002E8--------------------------
PORT 02E0-02E8 - LPT port address on the UniRAM card by German magazine c't
Range:	base address selectable from 0260, 02E0, 02E8, 02F0, 03E0, and 03E8.
----------P02E002EF--------------------------
PORT 02E0-02EF - GPIB (General Purpose Interface Bus, IEEE 488 interface)
		(GAB 0 on XT)
02E1  ??  GPIB (adapter 0)
02E2
02E3
----------P02E002EF--------------------------
PORT 02E0-02EF - data aquisition	 (AT)

02E2  ??  data aquisition (adapter 0)
02E3  ??  data aquisition (adapter 0)
----------P02E8------------------------------
PORT 02E8 - S3 86C928 video controller (ELSA Winner 1000)
----------P02E802E9--------------------------
PORT 02E8-02E9 - Intel 82C212B "Neat" chipset - EMS emulation control
Range:	base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
----------P02E802EF--------------------------
PORT 02E8-02EF - serial port, same as 02F8, 03E8 and 03F8 (COM4)
----------P02E802EF--------------------------
PORT 02E8-02EF - 8514/A and compatible (e.g. ATI Graphics Ultra)

02E8  R-  display status
02E8  -W  horizontal total
02EA  RW  Lookup: DAC mask
02EB  -W  Lookup: DAC read index
02EC  -W  Lookup: DAC write index
02ED  RW  Lookup: DAC data
----------P02EA------------------------------
PORT 02EA - S3 86C928 video controller (ELSA Winner 1000)
----------P02EB------------------------------
PORT 02EB - GI1904 Scanner Interface Adapter
Range:	PORT 022Bh, PORT 026Bh, PORT 02ABh (default), PORT 032Bh, PORT 036Bh,
	  PORT 03ABh, PORT 03EBh
----------P02EC------------------------------
PORT 02EC - GS-IF Scanner Interface adapter
Range:	PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
	  PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:	many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
	  others use this interface
----------P02F002F8--------------------------
PORT 02F0-02F8 - LPT port address on the UniRAM card by German magazine c't
		selectable from 260, 2E0, 2E8, 2F0, 3E0, 3E8.
----------P02F802FF--------------------------
PORT 02F8-02FF - serial port, same as 02E8, 03E8 and 03F8 (COM2)

02F8  -W  transmitter holding register
02F8  R-  receiver buffer register
02F8  RW  divisor latch, low byte	when DLAB=1
02F9  RW  divisor latch, high byte	when DLAB=1
02F9  RW  interrupt enable register when DLAB=0
02FA  R-  interrupt identification register
02FB  RW  line control register
02FC  RW  modem control register
02FD  R-  line status register
02FF  RW  scratch register
----------P0300------------------------------
PORT 0300 - Award POST Diagnostic
SeeAlso: PORT 0080h
--------d-P0300------------------------------
PORT 0300 - Digidesign 'Session 8' HARD-DISK RECORDING SYSTEM
SeeAlso: PORT 0200h"Digidesign"
--------s-P03000301--------------------------
PORT 0300-0301 - MPU-401 MIDI UART
Range:	alternate address at PORT 0330h, occasionally at PORT 0310h or
	  PORT 0320h
----------P03000301--------------------------
PORT 0300-0301 - Soundblaster 16 ASP MPU-Midi EMULATION
----------P0300????--------------------------
PORT 0300-???? - HP IEC/HP-IB adapter (e.g. for use with tape streamer HP9142)
----------P03000303--------------------------
PORT 0300-0303 - Panasonic 52x CD-ROM SCSI Miniport
Range:	PORT 0300h-0303h,PORT 0320h-0323h,PORT 0340h-0343h,PORT 0360h-0363h,
	  and PORT 0380h-0383h
----------P0300030F--------------------------
PORT 0300-030F - Philips CD-ROM player CM50
----------P0300030F--------------------------
PORT 0300-030F - CompaQ Tape drive adapter. alternate address at 0100
--------N-P0300031F--------------------------
PORT 0300-031F - 3com Ethernet adapters (default address)
--------N-P0300031F--------------------------
PORT 0300-031F - NE2000 compatible Ethernet adapters
Range:	may be placed at 0300h, 0320h, 0340h, or 0360h
SeeAlso: PORT 0300h"PCnet"
--------N-P0300031F--------------------------
PORT 0300-031F - AMD PCnet - NE2100-compatible Ethernet adapters
Range:	may be placed at 0300h, 0320h, 0340h, or 0360h, with the card's ROM
	  appearing at segment C800h, CC00h, D000h, or D400h, respectively
Note:	for the PCnet-FAST chip, the I/O address may be read from the PCI
	  configuration space at offset 10h (see #00878 at INT 1A/AX=B10Ah)
SeeAlso: PORT 0300h"NE2000",#00878

0300-030F  R-  address PROM (used to store Ethernet address, etc.)
0310w RW  Register Data Port (RDP) (see #P0552,#P0553)
0312w ?W  Register Access Port (RAP) (selects register index for RDP and IDP)
	  (see #P0570)
0314w ?W  Reset
0316w RW  ISA Bus Data Port (IDP)
0318w	  reserved for vendor-specific use
031A-031F      reserved

(Table P0552)
Values for AMD PCnet-ISA Register Data Port index:
 00h	"CSR0" status and control flags (see #P0554)
 01h	"CSR1" low half of IADR (appears at PORT 0316h)
 02h	"CSR2" high half of IADR (appears at PORT 0317h)
 03h	"CSR3" interrupt masks (see #P0555)
 04h	"CSR4" interrupt masks and status bits (see #P0556)
 08h-0Bh logical address filter
 0Ch-0Eh physical address register
 0Fh	"CSR15" mode (see #P0560)
 4Ch	"CSR76" receive descriptor ring length
 4Eh	"CSR78" transmit descriptor ring length
 50h	"CSR80" FIFO threshold / DMA burst control (see #P0564)
 52h	"CSR82" DMA bus timer
 58h	"CSR88" chip ID
 70h	"CSR112" number of missed packets
 72h	"CSR114" number of receive collisions
 7Ch	"CSR124" BMU test register
		bit 4: accept runt packets
SeeAlso: #P0570,#P0553

(Table P0553)
Values for AMD PCnet-SCSI/PCnet-FAST Register Data Port index:
 00h	"CSR0" status and control flags (see #P0554)
 01h	"CSR1" low half of IADR (appears at PORT 0316h)
 02h	"CSR2" high half of IADR (appears at PORT 0317h)
 03h	"CSR3" interrupt masks (see #P0555)
 04h	"CSR4" interrupt masks and status bits (see #P0556)
 05h	"CSR5" (PCnet-FAST) extended control and interrupt 1 (see #P0557)
 06h	"CSR6" receive/transmit descriptor table lengths (see #P0558)
 07h	"CSR7" (PCnet-FAST) extended control and interrupt 2 (see #P0559)
 08h-0Bh logical address filter
 0Ch-0Eh physical address register
 0Fh	"CSR15" mode (see #P0560)
 10h	"CSR16"	alias of CSR1
 11h	"CSR17"	alias of CSR2
 12h	"CSR18" low half of current receive buffer address
 13h	"CSR19" high half of current receive buffer address
 14h	"CSR20" low half of current transmit buffer address
 15h	"CSR21" high half of current transmit buffer address
 16h	"CSR22" low half of next receive buffer address
 17h	"CSR23" high half of next receive buffer address
 18h	"CSR24" low half of receive-ring base address
 19h	"CSR25" high half of receive-ring base address
 1Ah	"CSR26" low half of next receive descriptor address
 1Bh	"CSR27" high half of next receive descriptor address
 1Ch	"CSR28" low half of current receive descriptor address
 1Dh	"CSR29" high half of current receive descriptor address
 1Eh	"CSR30" low half of transmit ring base address
 1Fh	"CSR31" high half of transmit ring base address
 20h	"CSR32" low half of next transmit descriptor address
 21h	"CSR33" high half of next transmit descriptor address
 22h	"CSR34" low half of current transmit descriptor address
 23h	"CSR35" high half of current transmit descriptor address
 24h	"CSR36" low half of next next receive descriptor address
 25h	"CSR37" high half of next next receive descriptor address
 26h	"CSR38" low half of next next transmit descriptor address
 27h	"CSR39" high half of next next transmit descriptor address
 28h	"CSR40" current receive byte count (see #P0561)
 29h	"CSR41" current receive status
 2Ah	"CSR42" current transmit byte count (see #P0562)
 2Bh	"CSR43" current transmit status
 2Ch	"CSR44" next receive byte count (bits 11-0; bits 15-12=0)
 2Dh	"CSR45" next receive status
 2Eh	"CSR46" transmit poll time counter
 2Fh	"CSR47" transmit polling interval
 30h	"CSR48" receive poll time counter
 31h	"CSR49" receive polling interval
 32h-39h reserved
 3Ah	"CSR58" software style (see #P0563)
 3Bh	reserved
 3Ch	"CSR60" previous transmit descriptor address (low)
 3Dh	"CSR61" previous transmit descriptor address (high)
 3Eh	"CSR62" previous transmit byte count (bits 11-0; bits 15-12=0)
 3Fh	"CSR63" previous transmit status
 40h	"CSR64" next transmit buffer address (low)
 41h	"CSR65" next transmit buffer address (high)
 42h	"CSR66" next transmit byte count (bits 11-0; bits 15-12=0)
 43h	"CSR67" next transmit status
 44h-47h reserved
 48h	"CSR72" receive ring counter
 49h	reserved
 4Ah	"CSR74" transmit ring counter
 4Bh	reserved
 4Ch	"CSR76" receive descriptor ring length
 4Dh	reserved
 4Eh	"CSR78" transmit descriptor ring length
 4Fh	reserved
 50h	"CSR80" FIFO threshold / DMA burst control (see #P0564)
 51h	reserved
 52h	"CSR82" (PCnet-SCSI) DMA bus timer
		(PCnet-FAST) transmit descriptor address (low)
 53h	reserved
 54h	"CSR84" DMA address register (low)
 55h	"CSR85" DMA address register (high)
 56h	"CSR86" buffer byte counter (bits 11-0; bits 15-12=0)
 57h	reserved
 58h	"CSR88" chip ID (low 16 bits) (see #P0565)
 59h	"CSR89" chip ID (high 16 bits) (see #P0565)
 5Ah	"CSR90" (PCnet-SCSI)
 5Bh	reserved
 5Ch	"CSR92" ring length conversion
 5Dh	reserved
 5Eh	"CSR94" (PCnet-SCSI)
 5Fh-63h reserved
 64h	"CSR100" bus timeout
 65h-6Fh reserved
 70h	"CSR112" number of missed packets
 71h	reserved
 72h	"CSR114" number of receive collisions
 73h-79h reserved
 7Ah	"CSR122" advanced feature control (see #P0566)
 7Bh	reserved
 7Ch	"CSR124" BMU test register (see #P0567)
 7Dh	"CSR125" (PCnet-FAST) MAC Enhanced Configuration Control (see #P0568)
 7Eh-7Fh reserved
SeeAlso: #P0552,#P0594

Bitfields for AMD PCnet CSR0 status and control flags:
Bit(s)	Description	(Table P0554)
 15	"ERR"	error; set if BABL, CERR, MISS, or MESS set
 14	"BABL"	network babbling control
 13	"CERR"	collision error
 12	"MISS"	missed frame
 11	"MERR"	memory error
 10	"RINT"	receive interrupt
 9	"TINT"	transmit interrupt
 8	"IDON"	initialization done
 7	"INTR"	interrupt flag
 6	"IENA"	interrupt enable
 5	"RXON"	recieve ON
 4	"TXON"	transmit ON
 3	"TDMD"	transmit demand
 2	"STOP"	stop -- disable all external activity
 1	"STRT"	start -- enable extrnal activity
 0	"INIT"	begin initialization procedure
SeeAlso: #P0552,#P0555

Bitfields for AMD PCnet CSR3 interrupt masks:
Bit(s)	Description	(Table P0555)
 15	reserved
 14	"BABLM"	disable babble interrupt
 13	reserved
 12	"MISSM" disable missed-frame interrupt
 11	"MERM"	disable memory-error interrupt
 10	"RINTM"	disable receive interrupt
 9	"TINTM" disable transmit interrupt
 8	"IDONM" disable initialization-done interrupt
 7-5	reserved
 4	"DXMT2PD" disable Transmit Two Part Deferral
 3	"EMBA"	enable modified back-off algorithm
 2-0	reserved
Note:	other bits are reserved
SeeAlso: #P0552,#P0554,#P0556

Bitfields for AMD PCnet CSR4 interrupt masks and status bits:
Bit(s)	Description	(Table P0556)
 15	"ENTST"	   enable Test Mode / CSR124 access
 14	"DMAPLUS"  disable CSR80 burst transaction counter
 13	"TIMER"	   enable Bus Timer register
 12	"DPOLL"	   disable transmit polling
 11	"APADXMT"  Auto-Pad Transmit
 10	"ASTRPRCV" enable automatic pad stripping
 9	"MFCO"	   missed frame counter has overflowed
 8	"MFCOM"	   disable interrupt on MFCO
 7	"UINTCMD"  (PCnet-FAST) user interrupt command
 6	"UINT"	   (PCnet-FAST) user interrupt pending
			write 1 to clear
 5	"RCVCCO"   receive collision counter has overflowed
 4	"RCVCCOM"  disable interrupt on RCVCCO
 3	"TXSTRT"   Transmit Start
 2	"TXSTRTM"  disable interrupt on TXSTRT
 1	"JAB"	   Jabber error
 0	"JABM"	   disable interrupt on JAB
SeeAlso: #P0552,#P0555,#P0553

Bitfields for AMD PCnet-FAST CSR5 extended control and interrupt 1:
Bit(s)	Description	(Table P0557)
 31-16	reserved
 15	"TOKINTD"  disable Transmit OK interrupt
 14	"LTINTEN"  enable Last Transmit interrupt
 13-12	reserved
 11	"SINT"	   System Interrupt (write 1 to clear)
 10	"SINTE"	   enable System Interrupt
 9	"SLPINT"   Sleep Interrupt (write 1 to clear)
 8	"SLPINTE"  enable Sleep Interrupt
 7	"EXDINT"   Excessive Deferral Interrupt (write 1 to clear)
 6	"EXDINTE"  enable Excessive Deferral Interrupt
 5	"MPPLBA"   Magic Packet Physical Logical Broadcast Accept
 4	"MPINT"	   Magic Packet Interrupt (write 1 to clear)
 3	"MPINTE"   enable Magic Packet Interrupt
 2	"MPEN"	   enable Magic Packet mode
 1	"MPMODE"   Magic Packet mode active
 0	"SPND"	   Suspend
SeeAlso: #P0553,#P0556,#P0559

Bitfields for AMD PCnet CSR6 Descriptor Table Length register:
Bit(s)	Description	(Table P0558)
 15-12	transmit encoded ring length
 11-8	receive encoded ring length
 7-0	reserved
SeeAlso: #P0553,#P0557

Bitfields for AMD PCnet CSR7 Extended Control and Interrupt 2:
Bit(s)	Description	(Table P0559)
 15	"FASTSPNDE"  enable Fast Suspend
 14	"RXFRTG"     Receive Frame Tag
 13	"RDMD"	     Receive Demand
 12	"RXDPOL"     disable receive polling
 11	"STINT"	     Software Timer Interrupt (write 1 to clear)
 10	"STINTE"     enable Software Timer Interrupt
 9	"MREINT"     MII Management Read Error Interrupt (write 1 to clear)
 8	"MREINTE"    enable MII Management Read Error Interrupt
 7	"MAPINT"     MII Management Auto-Poll Interrupt (write 1 to clear)
 6	"MAPINTE"    enable MII Management Auto-Poll Interrupt
 5	"MCCINT"     MII Management Command Complete Interrupt (write 1 to clr)
 4	"MCCINTE"    enable MII Management Command Complete Interrupt
 3	"MCCIINT"    MII Management Command Complete Internal Interrupt
			(write 1 to clear)
 2	"MCCIINTE"   enable MII Manamagement Command Complete Internal Int.
 1	"MIIPDTINT"  MII PHY Detect Transition Interrupt (write 1 to clear)
 0	"MIIPDTINTE" enable MII PHY Detect Transition Interrupt
SeeAlso: #P0553,#P0557

Bitfields for AMD PCnet CSR15 mode flags:
Bit(s)	Description	(Table P0560)
 15	"PROM"	   promiscuous mode
 14	"DRCVBC"   disable Receive Broadcast
 13	"DRCVPA"   disable Receive Physical Address
 12	"DLNKTST"  disable Link Status
 11	"DAPC"	   disable Automatic Polarity Correction
 10	"MENDECL"  MENDEC loopback mode
 9	"LRT/TSEL" Low Receive Threshold
 8-7	"PORTSEL"  Port Select
		00  AUI
		01  10Base-T
		10  GPSI
		11  reserved
 6	"INTL"	   internal loopback
 5	"DRTY"	   disable retry
 4	"FCOLL"	   force collision
 3	"DXMTFCS"  disable Transmit CRC
 2	"LOOP"	   enable Loopback
 1	"DTX"	   disable transmitter
 0	"DRX"	   disable receiver
SeeAlso: #P0552,#P0556,#P0564

Bitfields for AMD PCnet CSR40 Current Receive Byte Count register:
Bit(s)	Description	(Table P0561)
 15-12	reserved (0)
 11-0	current receive byte count (copy of BCNT field of current receive
	  descriptor's RMD1)
SeeAlso: #P0553,#P0562

Bitfields for AMD PCnet CSR42 Current Transmit Byte Count register:
Bit(s)	Description	(Table P0562)
 15-12	reserved (0)
 11-0	current transmit byte count (copy of BCNT field of current receive
	  descriptor's TMD1)
SeeAlso: #P0553,#P0561

Bitfields for AMD PCnet CSR58 Software Style register:
Bit(s)	Description	(Table P0563)
 15-11	reserved (undefined)
 10	"APERREN"	enabled advanced parity error handling
 9	"CSRPCNET"	PCnet-ISA compatibility (read-only)
 8	"SSIZE32"	32-bit software structures for data blocks
 7-0	"SWSTYLE"	software style
		00h LANCE/PCnet-ISA (16-bit software structures)
		01h reserved
		02h PCnet-PCI (32-bit software)
		03h PCnet-PCI (32-bit software)
SeeAlso: #P0553

Bitfields for AMD PCnet CSR80 FIFO threshold and DMA burst control:
Bit(s)	Description	(Table P0564)
 15-14	reserved
 13-12	receive FIFO high-water mark; request DMA when N byte available
	00 = 16 bytes
	01 = 32 bytes
	10 = 64 bytes
 11-10	transmit starting point; start transmission after N bytes written
	00 = 4 bytes
	01 = 16 bytes
	10 = 64 bytes
	11 = 112 bytes
 9-8	transmit FIFO low-water mark; start DMA when room for N bytes
	00 = 8 bytes
	01 = 16 bytes
	10 = 32 bytes
 7-0	DMA burst register
SeeAlso: #P0552,#P0560

Bitfields for AMD PCnet Chip ID register (read-only):
Bit(s)	Description	(Table P0565)
 31-28	hardware version
 27-12	part number
	2623h = Am79C971
 11-1	manufacturer ID (0001h = AMD)
 0	reserved (1)
SeeAlso: #P0553

Bitfields for AMD PCnet CSR122 Advanced Feature Control register:
Bit(s)	Description	(Table P0566)
 15-1	reserved
 0	"RCVALGN"	DWORD-align received packets
SeeAlso: #P0553,#P0567

Bitfields for AMD PCnet CSR124 Test Register 1:
Bit(s)	Description	(Table P0567)
 15-5	reserved
 4	(PCnet-SCSI) accept runt packets
 3	(PCnet-FAST) accept runt packets
 2-0	reserved
SeeAlso: #P0553,#P0566

Bitfields for AMD PCnet-FAST CSR125 MAC Enhanced Configuration Control reg:
Bit(s)	Description	(Table P0568)
 15-8	inter-packet gap (reducing from default 96 can disrupt network)
 7-0	inter-frame spacing, part 1
SeeAlso: #P0553

(Table P0569)
Values for AMD PCnet-ISA ISA Bus Configuration Register index:
 00h	"MSRDA" width of DMA read signal
 01h	"MSWRA" width of DMA write signal
 02h	"MC"	ISA bus configuration (see #P0572)
 05h	"LED1"	LED1 signal control (see #P0573)
 06h	"LED2"	LED2 signal control (see #P0573)
 07h	"LED3"	LED3 signal control (see #P0573)
SeeAlso: #P0552,#P0594,#P0570

(Table P0570)
Values for AMD PCnet-SCSI Bus Configuration Register index:
 00h	"MSRDA" width of DMA read signal (reserved)
 01h	"MSWRA" width of DMA write signal (reserved)
 02h	"MC"	miscellaneous configuration (see #P0572)
 03h	reserved
 04h	"LINKST" link status
 05h	"LED1"	LED1 signal control (see #P0573) -- receive status
 06h	"LED2"	LED2 signal control (see #P0573)
 07h	"LED3"	LED3 signal control (see #P0573) -- transmit status
 08h-0Fh reserved
 10h	"IOBASEL"
 11h	"IOBASEU"
 12h	"BSBC"	burst size and bus control
 13h	"EECAS" EEPROM Control and Status
 14h	"SWS"	software style
 15h	"INTCON" reserved
SeeAlso: #P0553,#P0569,#P0571

(Table P0571)
Values for AMD PCnet-FAST Bus Configuration Register index:
 00h	"MSRDA"		width of DMA read signal (reserved)
 01h	"MSWRA"		width of DMA write signal (reserved)
 02h	"MC"		miscellaneous configuration (see #P0572)
 03h	reserved	!!!p.154
 04h	"LED0"	LED0 status
 05h	"LED1"	LED1 signal control (see #P0573) -- receive status
 06h	"LED2"	LED2 signal control (see #P0573)
 07h	"LED3"	LED3 signal control (see #P0573) -- transmit status
 08h	reserved
 09h	"FDC"		full-duplex control
 0Ah-0Fh reserved
 10h	"IOBASEL"	I/O base select (lo) -- reserved
 11h	"IOBASEU"	I/O base select (hi) -- reserved
 12h	"BSBC"		burst size and bus control
 13h	"EECAS"		EEPROM Control and Status
 14h	"SWS"		software style
 15h	"INTCON"	reserved
 16h	"PCILAT"	PCI-bus latency
 17h	"PCISID"	PCI subsystem ID
 18h	"PCISVID"	PCI subsystem vendor ID
 19h	"SRAMSIZ"	SRAM size
 1Ah	"SRAMB"		SRAM boundary
 1Bh	"SRAMIC"	SRAM interface control
 1Ch	"EBADDRL"	expansion bus address (low)
 1Dh	"EBADDRU"	expansion bus address (high)
 1Eh	"EBD"		expansion bus data port
 1Fh	"STVAL"		software timer value
 20h	"MIICAS"	MII control and status
 21h	"MIIADDR"	MII address
 22h	"MIIMDR"	MII management data
 23h	"PCIVID"	PCI vendor ID
SeeAlso: #P0553,#P0569,#P0570

Bitfields for AMD PCnet ISA bus configuration:
Bit(s)	Description	(Table P0572)
 3	EADISEL
 2	AWAKE
 1	ASEL
 0	XMAUSEL
SeeAlso: #P0570,#P0573

Bitfields for AMD PCnet LEDn signal control:
Bit(s)	Description	(Table P0573)
 15	LEDOUT
 14-8	reserved
 7	PSE
 6-5	reserved
 4	XMTE
 3	RVPE
 2	RCVE
 1	JABE
 0	COLE
SeeAlso: #P0570
----------P0300031F--------------------------
PORT 0300-031F - prototype cards
		Periscope hardware debugger
----------P030C030F--------------------------
PORT 030C-030F - AIMS LAB PC Radio
Range:	configurable to PORT 020Ch or PORT 030Ch
Notes:	writing a value with bit 3 set to one of these ports turns on the
	  radio; writing a value with bit 3 clear turns it off
	PORT 020Eh bits 1 indicates status of some kind
--------s-P03100311--------------------------
PORT 0310-0311 - MPU-401 MIDI UART
Range:	alternate address at PORT 0300h or PORT 0330h, occasionally at
	  PORT 0320h
----------P0310031F--------------------------
PORT 0310-031F - Philips CD-ROM player CM50
--------s-P03200321--------------------------
PORT 0320-0321 - MPU-401 MIDI UART
Range:	alternate address at PORT 0300h or PORT 0330h, occasionally at
	  PORT 0310h
----------P03200323--------------------------
PORT 0320-0323 - XT HDC 1   (Hard Disk Controller)
SeeAlso: PORT 01F0h-01F7h

0320  RW  data register
0321  -W  reset controller
0321  R-  read controller hardware status (see #P0574)
0322  R-  read DIPswitch setting on XT controller card
0322  -W  generate controller-select pulse
0323  -W  write pattern to DMA and INT mask register

Bitfields for XT hard disk controller hardware status:
Bit(s)	Description	(Table P0574)
 7-6	always 0
 5	logical unit number
 4-2	always 0
 1	error occurred
 0	always 0
----------P03240327--------------------------
PORT 0324-0327 - XT HDC 2   (Hard Disk Controller)
----------P0328032B--------------------------
PORT 0328-032B - XT HDC 3   (Hard Disk Controller)
----------P032B------------------------------
PORT 032B - GI1904 Scanner Interface Adapter
Range:	PORT 022Bh, PORT 026Bh, PORT 02ABh (default), PORT 02EBh, PORT 036Bh,
	  PORT 03ABh, PORT 03EBh
----------P032C------------------------------
PORT 032C - GS-IF Scanner Interface adapter
Range:	PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
	  PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:	many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
	  others use this interface
----------P032C032F--------------------------
PORT 032C-032F - XT HDC 4   (Hard Disk Controller)
----------P032C032F--------------------------
PORT 032C-032F - AMD InterWave
----------P03300331--------------------------
PORT 0330-0331 - MPU-401 MIDI UART
Range:	alternate address at PORT 0300h, occasionally at PORT 0310h or
	  PORT 0320h

0330  RW  data register
0331  R-  status register (see #P0575)
0331  -W  command register (see #P0576)
Note:	MPU-401 genarates an interrupt when MIDI code is ready; by reading
	  MIDI code from the data register this interrupt is cleared

Bitfields for MPU-401 status register:
Bit(s)	Description	(Table P0575)
 7	input ready
	=1 no data is available for reading
	=0 data is available for reading
 6	output ready
	=1 not ready to receive command/data byte
	=0 ready to receive command/data byte
 5-0	reserved
Note:	pending input seems to block the output
SeeAlso: #P0576

(Table P0576)
Values for MPU-401 commands (data go to/from PORT 0330h):
Command	Description		 Results  Parameter
 01h	send MIDI stop		   ACK	      -
 02h	send MIDI start		   ACK	      -
 03h	send MIDI continue	   ACK	      -
 15h	stop all (recording,	   ACK	      -
	  playback and MIDI)
 34h	return timing bytes	   ACK	      -
	  in stop mode
 35h	enable mode messages	   ACK	      -
	  to PC
 38h	enable system common	   ACK	      -
	  messages to PC
 39h	enable real time	   ACK	      -
	  messages to PC
 3Ch	use CLS sync		   ACK	      -
 3Dh	use SMPTE sync		   ACK	      -
 3Fh	enter UART mode		   ACK	      -
 80h	use MIDI sync		   ACK	      -
 81h	use FSK sync		   ACK	      -
 82h	use MIDI sync		   ACK	      -
 83h	enable metronome	   ACK	      -
 84h	disable metronome	   ACK	      -
 87h	enable pitch and	   ACK	      -
	  controller
 8Ah	disable data in stopped	   ACK	      -
	  mode
 8Bh	enable data in stop mode   ACK	      -
 8Ch	disable measure end	   ACK	      -
	  messages to host
 91h	enable ext MIDI control	   ACK	      -
 94h	disable clock to host	   ACK	      -
 95h	enable clock to host	   ACK	      -
 97h	enable system exclusive	   ACK	      -
	  messages to PC
 ACh	get MIDI version	 ACK,VER      -
 ADh	get revision		 ACK,REV      -
 Cxh	set timebase to x*24	   ACK	      -
	  ppqn (x>1)
 D0h	???			   ACK	      -
 DFh	???			   ACK	      -
 E0h	set tempo		   ACK	     BPS
 E4h	set clocks per click	   ACK	     CPC
 E6h	set beats per measure	   ACK	     BPM
 E7h	send all clocks to host	   ACK	    1 byte
					  (04h is sent)
 FFh	reset			   ACK	      -
Notes:	after receiving a command byte MPU-401 must reply with command
	  acknowledge byte FEh in data register
	command parameters are sent, and response bytes are received through
	  the data register
	no commands (except reset) can be issued in UART mode, and MPU-401
	  must be reset to leave UART mode
	Key:
		ACK	command acknowledge byte (FEh)
		VER	MIDI version number
			bits 7-4: major version
			bits 0-3: minor version
		REV	revision number
		BPS	beats per second (8..250)
		CPC	clocks per click
		BPM	beats per measure
SeeAlso: #P0576
----------P03300333--------------------------
PORT 0330-0333 - Adaptec 154xB/154xC SCSI adapter (default address)
Range:	four ports at any of 0130, 0134, 0230, 0234, 0330 (default) or 0334
Notes:	Adaptec AHA-154x adapters use ISA bus-mastering mechanism, and so
	  require the DMA channel to be programmed to the cascaded mode
	the original AHA-1540 only supported asynchronous SCSI data transfers,
	  and did not support scatter/gather operation
	AHA-154xA+ supports the target mode implementing the SCSI-2 processor
	  device model; it executes INQUIRY, TEST UNIT READY, and REQUEST SENSE
	  commands received from the initiators without CPU intervention; the
	  CPU is required to provide information only for the SEND/RECEIVE
	  commands; other commands are treated by the host adapter as invalid
	AHA-154xCF supports Fast SCSI data transfer
	BusLogic BT-545S and DTC 3290 seem to be "almost" compatible with
	  the Adaptec AHA-154x

0330  R-  status register (see #P0577)
0330  -W  control register (see #P0578)
0331  R-  data in register
0331  -W  command / data out register (see #P0580)
0332  R-  interrupt status register (see #P0579)

Bitfields for AHA-154x status register:
Bit(s)	Description	(Table P0577)
 7	self-test in progress (STST)
 6	diagnostic failure (DIAGF)
 5	mailbox initialization required (INIT)
 4	adapter idle (IDLE)
 3	command register full (CDF)
 2	data register full (DF)
 1	reserved
 0	invalid command (INVDCMD)
Notes:	bit 0 is only valid from the time the host adapter command complete
	  interrupt is set (bit 2 in the interrupt flag register) until it is
	  reset
	the data in register should only be read if bit 2 is set; reading the
	  data in register resets this bit
	command / data out register should only be written if bit 3 is zero;
	  the host adapter usually clears this bit within 100 mcs after CPU
	  writes to the command / data out register
	bit 4 indicates that the host adapter has no outstanding adapter or
	  SCSI commands
	bit 5 indicates that the mailbox initialization command (01h) required
	bit 7 is asserted after a power-on or hard reset (bit 7 in the control
	  register); when diagnostics is complete, this bit is reset and bit 5
	  or bit 6 is set to indicate seccessful or unsuccessful completion;
	  if the bit remain set, then initialization/diagnostic could not be
	  completed
	if bit 6 is set indication failed diagnostics, only the hard reset
	  (bit 7 in the control register) will clear it
SeeAlso: #P0578,#P0579,#P0580

Bitfields for AHA-154x control register:
Bit(s)	Description	(Table P0578)
 7	hardware reset (HRST)
 6	software reset (SRST)
 5	interrupt reset (IRST)
 4	SCSI bus reset (SCRST)
 0-3	reserved
Notes:	setting bit 4 causes the host adapter to assert the RST signal on the
	  SCSI bus for 25 microseconds (reset hold time); the reset is
	  managed as a SCSI soft reset, and will allow partially completed
	  operations to continue; use bit 7 to force a SCSI hard reset
	setting bit 5 clears all bits in the interrupt flag register and resets
	  the interrupt
	setting bit 6 clears all ongoing SCSI and host adapter commands
	setting bit 7 forces the host adapter into a state identical to a
	  normal power on state: diagnostic functions are executed and all
	  status for ongoing SCSI operations is lost, a reset condition is
	  generated on the SCSI bus; while the reset is being processed, bit 7
	  on the status register is set
	when soft/hard reset is complete, bits 4 and 5 of the status register
	  are set
SeeAlso: #P0577

Bitfields for AHA-154x interrupt status register:
Bit(s)	Description	(Table P0579)
 7	any interrupt (ANYINTR)
 4-6	reserved
 3	SCSI reset detected (SCRD)
 2	host adapter command complete (HACC)
 1	mailbox out available (MBOA)
 0	mailbox in full (MBIF)
Notes:	bit 0 indicates that an entry has been placed by the host adapter in
	  the mailbox in; this interrupt should be reset as soon as possible
	bit 1 indicates that an outbound mailbox entry is now available for use
	bit 2 indicates that an adapter command has been completed; bit 0 of
	  the status register will indicate success or failure; during the
	  parameter transfers to/from the host adapter, this bit should be
	  examined to verify that the command has not been ended abnormally
	bit 3 indicates that a SCSI reset has been received on the SCSI bus;
	  CPU can convert the SCSI soft reset to the SCSI hard reset by setting
	  bit 6 of the control register upon the detection of the SCSI reset
	  interrupt; it is not set for the CPU-initiated SCSI reset (via bit
	  4 of the control register)
	if the host adapter command complete and SCSI reset detected interrupts
	  are present, the mailbox in full and mailbox out available interrupts
	  are not presented until the former are cleared
	if bit 7 of this register or bit 2 of the status register is set, host
	  adapter command complete and SCSI reset detected interrupts will not
	  be presented until the interrupts already present are cleared
SeeAlso: #P0577,#P0581

(Table P0580)
Values for AHA-154x host adapter commands:
Command	Description		   Parameters		Results
 00h	no operation		   -			-
 01h	mailbox initialization	   MBC,MBA0..MBA2	-
 02h	start SCSI command	   -			-
 03h	start PC/AT BIOS command   BFN,TRG,CH,CLHH,	-
				   HL,SN,SC,BA0..BA2
 04h	adapter inquiry		   -			BID,SOID,FWR0,FWR1
 05h	enable mailbox out	   E/D			-
	  interrupt
 06h	set selection time-out	   E/D,TO0,TO1		-
 07h	set bus on time		   BON			-
 08h	set bus off time	   BOFF			-
 09h	set AT bus transfer speed  ATBS			-
 0Ah	return installed devices   -			TC0..TC7
 0Bh	return configuration data  -			DAP,IC,SID
 0Ch	enable target mode	   E/D,LUM		-
	  (not AHA-1540/W1542A)
 0Dh	return setup data	   DIL			SPS,ATBS,BON,BOFF,
							MBC,MBA0..MBA2,
							STA0..STA7,DS
 1Ah	write adapter channel 2	   BA0..BA2		-
	  buffer
 1Bh	read  adapter channel 2	   BA0..BA2		-
	  buffer
 1Ch	write adapter FIFO buffer  BA0..BA2		-
 1Dh	read  adapter FIFO buffer  BA0..BA2		-
 1Fh	echo command data	   EV			EV
 20h	run adapter diagnostics	   -			-
 21h	set adapter options	   ESG,DS		-
 22h	program EEPROM		   35 bytes		-
	  (AHA-1542C)
 23h	return EEPROM data	   ???,NED,EA		EEPROM data bytes
	  (AHA-1542C)
 24h	set shadow RAM parameters  1 byte		-
	  (AHA-1542C?)
 25h	BIOS mailbox initializa-   MBC,MBA0..MBA2	-
	  tion (since AHA-1540B
	  rev. 1.4?)
 26h	set BIOS bank 1		   -			-
	  (AHA-1542C?)
 27h	set BIOS bank 2		   -			-
	  (AHA-1542C?)
 28h	return extended BIOS	   -			F,MBLT
	  information (since
	  AHA-1540B rev. 1.4?)
 29h	enable mailbox interface   MBU,MBLT		-
	  (since AHA-1540B
	  rev. 1.4?)
 41h	AMI inquiry (AMI-4448)	   SL			C0..C3,M0..M5,
							S0..S5,V0..V5
 82h	start BIOS SCSI command	   -			-
	  (since AHA-1540B
	  rev. 1.4?)
 8Dh	exteded setup information  DIL?			?
	  (since AHA-1540B
	  rev. 1.4?)
Note:	MBC	   mailboxes count (>0)
	MBA0..MBA2 MSB..LSB of the physical address of the mailbox area
		     (see #P0581)
	BFN	   BIOS function number
	TRG	   bits 7-5: target ID
		   bits 4-0: reserved
	CH	   bits 7-4: reserved
		   bits 3-0: bits 9-6 of cylinder number
	CLHH	   bits 7-2: bits 5-0 of cylinder number
		   bits 1-0: bits 5-4 of head number
	HL	   bits 7-4: reserved
		   bits 3-0: bits 3-0 of head number
	SN	   sector number - 1
	SC	   sector count
	BA0..BA2   MSB..LSB of the physical address of the data buffer
	BID	   board ID
		   00h AHA-1540 (16-head BIOS)
		   20h BusLogic BT-545S
		   30h AHA-1540 (64-head BIOS)
		   31h AHA-1540
		   41h AHA-154xA/154xB (64-head BIOS)
		   42h AHA-1640 (64-head BIOS)
		   43h AHA-1542C
		   44h AHA-1542CF
		   45h AHA-1542CF (BIOS v2.01)
	SOID	   special options ID
		   30h ???
		   41h standard model
	FWR0,FWR1  firmware revision (alphanumeric)
	E/D	   enable/diable parameter
		   00h disable
		   01h enable
	TO0,TO1	   MSB, LSB of the time-out value (in ms)
		   default 250 ms
	BON	   bus on time (in mcs)
		   time the adapter stays on the AT bus when transferring data
		     2..15 mcs, default 11 mcs
	BOFF	   bus off time (in mcs)
		   time the adapter stays off the AT bus when transferring data
		     1..64 mcs, default 4 mcs
	ATBS	   AT bus transfer speed
		   00h,AAh 5.0	MB/s
		   01h,99h 6.7	Mb/s
		   02h	   8.0	Mb/s
		   03h,88h 10.0 Mb/s
		   04h	   5.7	Mb/s
		   BBh	   4.0	Mb/s?
		   CCh	   3.3	Mb/s?
		   DDh	   2.9	Mb/s?
		   EEh	   2.5	Mb/s?
		   FFh	   2.2	Mb/s?
	TC0..TC7   target 0..7 configuration
		   bit M in byte N is set if SCSI ID N LUN M is installed
	DAO	   DRQ arbitration priority
		   bit 7: channel 7
		   bit 6: channel 6
		   bit 5: channel 5
		   bits 4-1: reserved (0)
		   bit 0: channel 0
	IRQ	   interrupt channel
		   bit 7: reserved (0)
		   bit 6: IRQ15
		   bit 5: IRQ14
		   bit 4: reserved (0)
		   bit 3: IRQ12
		   bit 2: IRQ11
		   bit 1: IRQ10
		   bit 0: IRQ9
	SID	   SCSI ID
		   bits 7-3: reserved (0)
		   bits 2-0: binary value of SCSI ID
	LUM	   logical unit mask
		   bit N is set if LUN N is to respond in target mode
	DIL	   data in length
		   number of bytes to return (0 means 256 bytes)
	SPS	   SDT and parity status
		   bits 7-2: reserved (0)
		   bit 1: SCSI parity check enabled
		   bit 0: synchronous negotiation initiated
	STA0..STA7 synchronous transfer agreements for target ID 0..7
		   bit 7: synchronous transfer negotiated
		   bits 6-4: value defining synchronous transfer period
			     period in ns can be calculated as 200+50*value
		   bits 3-0: negotiated offset value
	DS	   (AHA-154xB+?) disconnect status
		   bit N is set if target ID N is unable to disconnect?
	EV	   echo value (it is be echoed back)
	ESG	   01h: enable scatter/gather
	NED	   number of EEPROM data bytes to return
	EA	   EEPROM address to read data from
	F	   flags
		   bit 3: extended BIOS translation (255 heads / 63 sectors)
	MBLT	   mailbox lock type
		   01h translation  lock (for extended BIOS)
		   02h dynamic scan lock
	MBU	   00h: mailbox unlock
	SL	   string length
	C0..C3	   ASCIZ company string ("AMI")
	M0..M5	   ASCIZ model string
	S0..S5	   ASCIZ series string ("48")
	V0..V5	   ASCIZ version string ("1.00")
Notes:	all commands except 02h, 05h, 82h should only be issued if the host
	  adapter is idle (bit 4 in the status register set)
	command 02h can be issued even if the command / data out register is
	  full (bit 3 in the status register may be set)
	command 02h causes host adapter to scan both its SCSI and BIOS mailbox
	  areas; command 82h causes host adapter to scan only BIOS mailbox area
	all commands except 02h and 05h cause host adapter command complete
	  interrupt (bit 2 in the interrupt flag register) after completetion;
	  command 05h will still generate the interrupt if its parameter was
	  invalid
	return installed devices command (0Ah) results in the host adapter
	  issuing the TEST UNIT READY command to each target/LUN combination
	return setup data command (0Dh) returns the number of bytes requested
	  with DIL parameter
	BusLogic BT-545S gets the adapter inquiry command (04h) wrong returning
	  only one byte instead of four; DTC 3290 gets this command wrong too
	AMI inquiry command (41h) returns the number of bytes requested
	  with SL parameter
SeeAlso: #P0577,#P0579

Format of AHA-154x mailbox array:
Offset	Size	Description	(Table P0581)
 00h  N*4 BYTEs	array of N "out" mailboxes (MBO) (see #P0582)
 N*4  N*4 BYTEs	array of N "in" mailboxes (MBI) (see #P0584)
Notes:	the MBO entries are scanned by the host adapter in a round-robin
	  fashion, i.e. the host adapter first looks into an MBO which follows
	  the one least recently used (and wraps around if it was the last one)
	the MBI entries are filled in a round-robin fashion, so the CPU should
	  check the next MBI entry after the last one that was found when a new
	  mailbox in full (bit 0 in the interrupt flag register) interrupt; CPU
	  should also check the next MBI entries to determine if more than one
	  MBI is ready
	MBI entries are absent in case of BIOS mailboxes; in this case MBI
	  status code is returned in the command linking ID field of the
	  command control block (CCB)
	target mode CCB may be posted to the host adapter in anticipation of
	  the SCSI command reception, with the direction bits indicating the
	  expected transfer directiin (i.e. SEND or RECEIVE command); if a SCSI
	  command is received by the host adapter before the CCB is prepared,
	  it requests a CCB from the host through the MBI
SeeAlso: #P0577,#P0579,#P0583,#P0585,#P0587

Format of AHA-154x mailbox-out (MBO) entry:
Offset	Size	Description	(Table P0582)
 00h	BYTE	mailbox command/status code (see #P0583,#P0585)
 01h  3 BYTEs	address of the command control block (CCB) (see #P0586)
		physical address in big-endian format
SeeAlso: #P0577,#P0581,#P0584

(Table P0583)
Values for mailbox out command codes:
 00h	mailbox/CCB is free
 01h	start CCB
 02h	abort CCB
SeeAlso: #P0577,#P0581,#P0585

Format of mailbox-in (MBI) entry:
Offset	Size	Description	(Table P0584)
 00h	BYTE	MBI status code (see #0584)
---MBI status code 10h---
 01h	BYTE	initiator and LUN
		bits 7-5: SCSI initiator ID
		bit 4: RECEIVE command received
		bit 3: SEND command received
		bits 2-0: LUN
 02h	WORD	data length
		2 high bytes of the data length in SCSI SEND/RECEIVE command
		in big-endian format
---other MBI status codes---
 01h  3 BYTEs	CCB pointer
		physical address in big-endian format
SeeAlso: #P0582,#P0577,#P0581,#P0587

(Table P0585)
Values for mailbox in status codes:
 00h	command in progress
 01h	CCB completed
 02h	CCB aborted
 03h	CCB abort failed
 04h	CCB completed with error
SeeAlso: #P0584,#P0581,#P0583

Format of AHA-154x command control block (CCB):
Offset	Size	Description	(Table P0586)
 00h	BYTE	CCB operation code (see #P0587)
---operation code 00h---
 01h	BYTE	address and control (see #P0601)
 02h	BYTE	SCSI command length
 03h	BYTE	request sense allocation length
		00h request 14 bytes of sense data
		01h disable auto-sense
		02h-07h reserved
		08h-FFh sense data length
 04h  3 BYTEs	data length
		in big-endian format
 07h  3 BYTEs	data pointer
		physical address in big-endian format
 0Ah  3 BYTEs	link pointer (link to the next CCB for the linked commands)
		physical address in big-endian format
 0Dh	BYTE	command linking ID (for the linked commands)
		(return) MBI status code if this CCB is in a BIOS mailbox
		  (see #P0585)
 0Eh	BYTE	(return) host adapter status (HASTAT) (see #P0589)
 0Fh	BYTE	(return) target device status (TARSTAT)
		SCSI status byte
 10h  2 BYTEs	reserved
 12h  N BYTEs	SCSI command descriptor block (CDB)
 12h+N M BYTEs	allocated for sense data
		(return) sense data (if requested)
---operation code 01h---
 01h	BYTE	address and control
		bits 7-5: initiator ID
		bits 4-3: transfer direction
			  01 SEND command
			  10 RECEIVE command
			  00,11 illegal combination
		bits 2-0: LUN
 02h	BYTE	SCSI command length
 03h	BYTE	request sense allocation length
 04h  3 BYTEs	data length
 07h  3 BYTEs	data pointer
 0Ah  4 BYTEs	reserved
 0Eh	BYTE	(return) host adapter status (see #P0589)
 0Fh	BYTE	(return) target device status
 10h  2 BYTEs	reserved
 12h  N BYTEs	(return) SCSI CDB
 12h+N M BYTEs	allocated for sense data
		(return) sense data (to be sent to the initiator)
---operation code 02h---
 01h	BYTE	address and control (see #P0601)
 02h	BYTE	SCSI command length
 03h	BYTE	request sense allocation length
 04h  3 BYTEs	data segment list length (in bytes)
		in big-endian format
 07h  3 BYTEs	data segment list pointer
		physical address in big-endian format
 0Ah  3 BYTEs	link pointer
 0Dh	BYTE	command linking ID
		(return) MBI status code if this CCB is in a BIOS mailbox
		  (see #P0585)
 0Eh	BYTE	(return) host adapter status (see #P0589)
 0Fh	BYTE	(return) target device status
 10h  2 BYTEs	reserved
 12h  N BYTEs	SCSI CDB
 12h+N M BYTEs	allocated for sense data
		(return) sense data (if requested)
---operation code 03h---
 01h	BYTE	address and control (see #P0601)
 02h	BYTE	SCSI command length
 03h	BYTE	request sense allocation length
 04h  3 BYTEs	data length
		(return) residual length
 07h  3 BYTEs	data pointer
 0Ah  3 BYTEs	link pointer
 0Dh	BYTE	command linking ID
		(return) MBI status code if this CCB is in a BIOS mailbox
		  (see #P0585)
 0Eh	BYTE	(return) host adapter status (see #P0589)
 0Fh	BYTE	(return) target device status
 10h  2 BYTEs	reserved
 12h  N BYTEs	SCSI CDB
 12h+N M BYTEs	allocated for sense data
		(return) sense data (if requested)
---operation code 04h---
 01h	BYTE	address and control (see #P0601)
 02h	BYTE	SCSI command length
 03h	BYTE	request sense allocation length
 04h  3 BYTEs	data segment list length (in bytes)
		(return) residual length
 07h  3 BYTEs	data segment list pointer
 0Ah  3 BYTEs	link pointer
 0Dh	BYTE	command linking ID
		(return) MBI status code if this CCB is in a BIOS mailbox
		  (see #P0583)
 0Eh	BYTE	(return) host adapter status (see #P0589)
 0Fh	BYTE	(return) target device status
 10h  2 BYTEs	reserved
 12h  N BYTEs	SCSI CDB
 12h+N M BYTEs	allocated for sense data
		(return) sense data (if requested)
---operation code 81h---
 01h	BYTE	address and control
		bits 7-5: target ID
		bits 4-0: reserved
Note:	if a SCSI command completes with the BUSY status, the host adapter
	  periodically restarts it until it completes with other status
	if a SCSI command completes with the CHECK CONDITION status, the host
	  adapter automatically issues a REQUEST SENSE command with the data
	  length specified by request sense allocation length field; the actual
	  bytes returned are placed in the area allocated for sense data; but
	  if the request sense allocation length was 01h, no REQUEST SENSE
	  command is issued
	if the host adapter completes a SCSI command with the CHECK CONDITION
	  status while it is operating in the target mode, the same sense data
	  that will later be received by the initiator is also placed in the
	  area allocated for sense data
	command linking is not supported in target mode
	for a target mode CCB target device status field is used to indicate
	  to the host what status the host adapter returned to the initiator;
	  SCSI CDB field is used to return the CDB from the initiator
SeeAlso: #P0577,#P0582,#P0584

(Table P0587)
Values for CCB type:
 00h	initiator CCB
 01h	target CCB (not on AHA-1540/W1542A)
 02h	initiator CCB with scatter/gather (see #P0590) (not on AHA-1540)
 03h	initiator CCB with residual length (AHA-154xB or higher)
 04h	initiator CCB with scatter/gather and residual length (see #P0590)
	(AHA-154xB or higher)
 81h	bus device reset CCB
Note:	residual length is returned in the data length field of CCB
	initiator CCB with scatter/gather cannot have a zero data length or
	  contain more than 16 entries
SeeAlso: #P0577,#P0586

Bitfields for the initiator mode address and control CCB field:
Bit(s)	Description	(Table P0601)
 7-5	target ID
 4-3	transfer direction
	00 determined by the SCSI command
	01 inbound data	 transfer, length is checked
	10 outbound data transfer, length is checked
	11 no data transfer (suppress inbound data transfer)
 2-0	LUN
SeeAlso: #P0586,#P0589

(Table P0589)
Values for host adapter status:
 00h	command complete
 0Ah	linked command complete (linked CCBs only)
 0Bh	linked command complete with flag (linked CCBs only)
 11h	selection time out
 12h	data overrun/underrun
 13h	unexpected bus free
 14h	target bus phase sequence failure
 15h	invalid mailbox out command
 16h	invalid CCB operation code
 17h	linked CCB does not have the same LUN
 18h	(not AHA-1540/W1542A) invalid target direction received from host
	  (target mode)
 19h	(not AHA-1540/W1542A) duplicate CCB received (target mode)
 1Ah	invalid CCB or segment list parameter
Notes:	in the initiator mode, if the target attempted to transfer more data
	  than was allocated by the data length field or the sum of the data
	  segment length fields, and the length checking was enabled via bits
	  4-3 of the address and control field, the CCB will be returned with a
	  host status of 12h; if the length checking was not enabled, command
	  will be completed without error
	in the target mode, if the transfer length specified by the SEND/
	  RECEIVE command is not equal to that specified in the target mode CCB
	  the host adapter will notify the CPU, setting the incorrect length
	  indication bit (ILI), bit 5 of byte 2 in the area allocated for sense
	  data; also, bytes 3..6 in this area will contain the residue of the
	  length requested in the SSCI command and the data length in the CCB
	  (MSB first); if it is negative the GOOD status will be returned to
	  the initiator, else the CHECK CONDITION status will be returned (with
	  subsequent REQUEST SENSE returning ILI in byte 2 and residue in bytes
	  3..6 of the sense data); the CCB will be returned with a host status
	  of 12h in both cases
	  will be completed without error
	in case of target bus sequence failure host adapter will generate a
	  SCSI reset condition setting bit 3 in the interrupt flag register and
	  generating an interrupt
	in target mode one CCB may be presented for each unique combination of
	  LUN, Initiator, and direction; if a second CCB to the same LUN and
	  initiator with the same direction bit is sent to the host adapter,
	  the CCB will be returned with a host status of 19h
	if a segment list with a zero length segment or invalid segment list
	  boundaries was received or a CCB parameter was invalid, the CCB will
	  be returned with a host status of 1Ah
SeeAlso: #P0577,#P0586,#P0601

Format of AHA-154x scatter/gather segment:
Offset	Size	Description	(Table P0590)
 00h  3 BYTEs	data length
		in big-endian format
 03h  3 BYTEs	data pointer
		physical address in big-endian format
Note:	if the segment ends at odd/even bondary, the next segment must begin
	  on the same boundary
SeeAlso: #P0577
----------P0330033F--------------------------
PORT 0330-033F - CompaQ SCSI adapter. alternate address at 0130
--------d-P0330033F--------------------------
PORT 0330-033F - Philips CD-ROM player CM50
--------d-P03340337--------------------------
PORT 0334-0337 - Adaptec 154xB/154xC SCSI adapter.
Range:	four ports at any of 0130, 0134, 0230, 0234, 0330 (default) or 0334
--------s-P0338------------------------------
PORT 0338 - AdLib soundblaster card
--------S-P0338033F--------------------------
PORT 0338-033F - COM port addresses on UniRAM card by German magazine c't
Range:	selectable from 0238, 02E8, 02F8, 0338, 03E0, 03E8, 03F8
----------P0340034F--------------------------
PORT 0340-034F - Philips CD-ROM player CM50
----------P0340034F--------------------------
PORT 0340-034F - SCSI (1st Small Computer System Interface) adapter
Range:	alternate address at 0140-014F
--------s-P0340------------------------------
PORT 0340 - Crystal Semiconductor CDB4922 evaluation board
Desc:	the CDB4922 is an evaluation board for the CS4922 MPEG audio
	  decoder (see I2C xxh"CS4922")
--------s-P0340034F--------------------------
PORT 0340-034F - Gravis Ultra Sound by Advanced Gravis
Range: The I/O address range is dipswitch selectable from:
	   0200-020F and 0300-030F
	   0210-021F and 0310-031F
	   0220-022F and 0320-032F
	   0230-023F and 0330-033F
	   0240-024F and 0340-034F
	   0250-025F and 0350-035F
	   0260-026F and 0360-036F
	   0270-027F and 0370-037F
Note:	the AMD InterWave chip provides a superset of the UltraSound's
	  functionality, including these ports
SeeAlso: PORT 0240h-024Fh,PORT 0746h

0340  -W  MIDI Control (see #P0591)
0340  R-  MIDI Status (see #P0592)
0341  -W  MIDI Transmit Data
0341  R-  MIDI Receive Data
0342  RW  GF1 Page Register / Voice Select
0343  RW  GF1/Global Register Select (see #P0593)
0344  RW  GF1/Global Data Low Byte (16 bits)
0345  RW  GF1/Global Data High Byte (8 bits)
0346  -W  Mixer Data Port
0347  RW  GF1 DRAM
		 Direct Read Write at Loction pointed with regs 43 and 44

Bitfields for Gravis Ultra Sound MIDI control register:
Bit(s)	Description	(Table P0591)
 7	   Receive IRQ (1 = enabled)
 5-6   Xmit IRQ
 0-1   Master Reset (1 = enabled)
SeeAlso: #P0546,#P0548,#P0592

Bitfields for Gravis Ultra Sound MIDI status register:
Bit(s)	Description	(Table P0592)
 7	Interrupt pending
 5	Overrun Error
 4	Framing Error
 1	Transmit Register Empty
 0	Receive Register Empty
SeeAlso: #P0591,#P0593

(Table P0593)
Values for Gravis Ultra Sound GF1/Global Registers:
---Voice specific registers---
 00h  w	    Voice Control (see #P0595)
 01h  w	    Frequency Control
	     bit 15-10	 Integer Portion
	     bit 9-1	 Fractional Portion
 02h  w	    Start Address HIGH
	     bit 12-0	 Address Lines 19-7
 03h  w	    Start Address LOW
	     bit 15-9	 Address Lines 6-0
	     bit 8-5	 Fractional Part of Start Address
 04h  w	    End Address HIGH
	     bit 12-0	 Address Lines 19-7
 05h  w	    End Address LOW
	     bit 15-9	 Address Lines 6-0
	     bit 8-5	 Fractional Part of End Address
 06h  w	    Volume Ramp Rate
	     bit 5-0	 Amount added
	     bit 7-6	 Rate
 07h  w	    Volume Ramp Start
	     bit 7-4	 Exponent
	     bit 3-0	 Mantissa
 08h  w	    Volume Ramp End
	     bit 7-4	 Exponent
	     bit 3-0	 Mantissa
 09h  w	    Current Volume
	     bit 15-12	 Exponent
	     bit 11-4	 Mantissa
 0Ah  w	    Current Address HIGH
	     bit 12-0	 Address Lines 19-7
 0Bh  w	    Current Address LOW
	     bit 15-9	 Address Lines 6-0
	     bit 8-0	 Fractional Position
 0Ch  w	    Pan Position
	     bit 3-0	 Pan Postion
 0Dh  w	    Volume Control (see #P0596)
 0Eh  w	    Active Voices
	     bit 5-0	 #Voices -1  (allowed 13 - 31)
 0Fh  w	    IRQ Source Register (see #P0597)
---NOT voice specific---
 41h  r/w   DRAM DMA Control (see #P0598)
 42h  w	    DMA Start Address
	     bits 15-0	 DMA Address Lines 19-4
 43h  w	    DRAM I/O Address LOW
 44h  w	    DRAM I/O Address HIGH
	     bits 0-3	 Upper 4 Address Lines
 45h  r/w   Timer Control
	     bit 3	 Enable Timer 2
	     bit 2	 Enable Timer 1
 46h  w	    Timer 1 Count (granularity of 80 micro sec)
 47h  w	    Timer 2 Count (granulatity of 320 micro sec)
 48h  w	    Sampling Frequency
	     rate = 9878400 / (16 * (FREQ + 2))
 49h  r/w   Sampling Control (see #P0599)
 4Bh  w	    Joystick Trim DAC
 4Ch  r/w   RESET
	     bit 2	 GF1 Master IRQ Enable
	     bit 1	 DAC Enable
	     bit 0	 Master Reset
---Voice specific registers---
 80h  r	    Voice Control (see 00h)
 81h  r	    Frequency Control (see 01h)
 82h  r	    Start Address HIGH (see 02h)
 83h  r	    Start Address LOW (see 03h)
 84h  r	    End Address HIGH (see 04h)
 85h  r	    End Address LOW (see 05h)
 86h  r	    Volume Ramp Rate (see 06h)
 87h  r	    Volume Ramp Start (see 07h)
 88h  r	    Volume Ramp End (see 08h)
 89h  r	    Current Volume (see 09h)
 8Ah  r	    Current Address HIGH (see 0Ah)
 8Bh  r	    Current Address LOW (see 0Bh)
 8Ch  r	    Pan Position (see 0Ch)
 8Dh  r	    Volume Control (see 0Dh)
 8Eh  r	    Active Voices (see 0Eh)
 8Fh  r	    IRQ Status (see 0Fh)
SeeAlso: #P0592,#P0594

(Table P0594)
Values for InterWave synthesizer registers:
---voice-specific registers---
 10h  w	    synthesizer	 upper address
 11h  w	    synthesizer effects address high (16 bits)
 12h  w	    synthesizer effects address low (16 bits)
 13h  w	    synthesizer left offset (16 bits)
 14h  w	    synthesizer effects output accumulator select
 15h  w	    synthesizer mode select
 16h  w	    synthesizer effects volume (16 bits)
 17h  w	    synthesizer frequency LFO
 18h  w	    synthesizer volume LFO
---NOT voice-specific---
 19h  w	    synthesizer global mode
 1Ah  w	    synthesizer LFO base address (16 bits)
---voice-specific registers---
 1Bh  w	    synthesizer right offset (16 bits)
 1Ch  w	    synthesizer left offset (16 bits)
 1Dh  w	    synthesizer effect volume final (16 bits)
---NOT voice-specific---
 41h  r/w   local memory control: DMA control
 42h  r/w   local memory control: DMA start address bits 19-4 (16 bits)
 43h  w	    local memory control: I/O address low (16 bits)
 44h  w	    local memory control: I/O address high (16 bits)
 45h  r/w   AdLib/SoundBlaster control
 46h  r/w   AdLib timer 1
 47h  r/w   AdLib timer 2
 49h  r/w   ADC sample control
 4Bh  r/w   joystick trim
 4Ch  w	    GUS reset
 50h  r/w   local memory control: DMA start address bits 23-20/3-0 (16 bits)
 51h  r/w   local memory control: 16-bit access
 52h  r/w   local memory control: configuration
 53h  r/w   local memory control: control
 54h  r/w   local memory control: record FIFO base address bits 23-8 (16-bit)
 55h  r/w   local memory control: playback FIFO base address bits 23-8 (16-bit)
 56h  r/w   local memory control: FIFO size (16-bit)
 57h  r/w   local memory control: DMA interleave control (16-bit)
 58h  r/w   local memory control: DMA interleaev base address bits 23-8
 59h  r/w   compatibility control
 5Ah  r/w   decode control
 5Bh  r/w   version number
 5Ch  r/w   MPU-401 emulation control A
 5Dh  r/w   MPU-401 emulation control B
 5Eh  w	    MIDI receive FIFO access
 5Fh  -	    reserved
 60h  r/w   emulation IRQ
---voice-specific registers---
 90h  r	    synthesizer	 upper address
 91h  r	    synthesizer effects address high (16 bits)
 92h  r	    synthesizer effects address low (16 bits)
 93h  r	    synthesizer left offset (16 bits)
 94h  r	    synthesizer effects output accumulator select
 95h  r	    synthesizer mode select
 96h  r	    synthesizer effects volume (16 bits)
 97h  r	    synthesizer frequency LFO
 98h  r	    synthesizer volume LFO
---NOT voice-specific---
 99h  r	    synthesizer global mode
 9Ah  r	    synthesizer LFO base address (16 bits)
---voice-specific registers---
 9Bh  r	    synthesizer right offset (16 bits)
 9Ch  r	    synthesizer left offset (16 bits)
 9Dh  r	    synthesizer effect volume final (16 bits)
---NOT voice-specific---
 9Fh  r	    synthesizer voices IRQ
Note:	these registers are *in*addition* to the Gravis UltraSound registers
SeeAlso: #P0593

Bitfields for Gravis Ultra Sound voice control global register:
Bit(s)	Description	(Table P0595)
 7	 IRQ pending
 6	 Direction
 5	 Enable WAVE IRQ
 4	 Enable bi-directional Looping
 3	 Enable Looping
 2	 Size data (8/16 bits)
 1	 Stop Voice
 0	 Voice Stopped
SeeAlso: #P0593,#P0596

Bitfields for Gravis Ultra Sound volume control global register:
Bit(s)	Description	(Table P0596)
 7	 IRQ Pending
 6	 Direction
 5	 Enable Volume Ramp IRQ
 4	 Enable bi-directional Looping
 3	 Enable Looping
 2	 Rollover Condition
 1	 Stop Ramp
 0	 Ramp Stopped
SeeAlso: #P0593,#P0595

Bitfields for Gravis Ultra Sound IRQ source register:
Bit(s)	Description	(Table P0597)
 7	 WaveTable IRQ pending
 6	 Volume Ramp IRQ pending
 4-0	 Voice Number
SeeAlso: #P0593,#P0595,#P0598

Bitfields for Gravis Ultra Sound DRAM DMA control register:
Bit(s)	Description	(Table P0598)
 7	 Invert MSB
 6	 Data Size (8/16 bits)
 5	 DMA Pending
 3-4	 DMA Rate Divider
 2	 DMA Channel Width (8/16 bits)
 1	 DMA Direction (1 = read)
 0	 DMA Enable
SeeAlso: #P0593,#P0597

Bitfields for Gravis Ultra Sound sampling control register:
Bit(s)	Description	(Table P0599)
 7	 Invert MSB
 6	 DMA IRQ pending
 5	 DMA IRQ enable
 2	 DMA width (8/16 bits)
 1	 Mode (mone/stereo)
 0	 Start Sampling
SeeAlso: #P0593
----------P03400357--------------------------
PORT 0340-0357 - RTC (1st Real Time Clock for XT)
		(used by TIMER.COM v1.2 which is the 'standard' timer program)
Range:	alternate at 0240-0257
SeeAlso:  PORT 0240h-0257h

0340  RW  0.001 seconds		0-99
0341  RW  0.1 and 0.01 seconds	0-99
0342  RW  seconds		0-59
0343  RW  minutes		0-59
0343  RW  hours			0-23
0345  RW  day of week		1-7
0346  RW  day of month		1-31
0347  RW  month			1-12
0348  RW  RAM (upper nybble only)
0349  RW  year			0-99
034A  RW  RAM last month storage
034B  RW  RAM year storage (-80)
034C  RW  RAM reserved
034D  RW  RAM not used
034E  RW  RAM not used
034F  RW  RAM not used
0350  R-  interrupt status register
0351  -W  interrupt control register
0352  -W  counter reset
0353  -W  RAM reset
0354  R-  status bit
0355  -W  GO command
0356  ??  standby interrupt
0357  ??  test mode
--------d-P0340035F--------------------------
PORT 0340-035F -  Adaptec AHA-152x SCSI adapter
Range:	alternate address at 0140
Note:	Adaptec AHA-152x SCSI adapter series are based upon Adaptec
	  AIC-6260/6360/6370 SCSI controllers
SeeAlso: PORT xxxxh"Adaptec AIC-78xx"

+000  RW  SCSI sequence control register (SCSISEQ) (see #P0600)
+001  RW  SCSI transfer control register 0 (SXFRCTL0) (see #P0601)
+002  RW  SCSI transfer control register 1 (SXFRCTL1) (see #P0602)
+003  R-  SCSI control signal read  register (SCSISIGI) (see #P0603)
+003  -W  SCSI control signal write register (SCSISIGO) (see #P0604)
+004  RW  SCSI rate control register (SCSIRATE) (see #P0605)
+005  RW  SCSI ID register (SCSIID) (see #P0606)
+006  RW  SCSI latched data register (SCSIDAT)
	  read/write causes -ACK to pulse
+007  R?  SCSI data bus register (SCSIBUS)
+008  RW  SCSI transfer count register (STCNT) (3 bytes long)
+00B  R-  SCSI status register 0 (SSTAT0) (see #P0607)
+00B  -W  clear SCSI interrupt register 0 (CLRSINT0) (see #P0608)
+00C  R-  SCSI status register 1 (SSTAT1) (see #P0609)
+00C  -W  clear SCSI interrupt register 1 (CLRSINT1) (see #P0610)
+00D  R-  SCSI status register 2 (SSTAT2) (see #P0611)
+00E  R-  SCSI status register 3 (SSTAT3) (see #P0612)
+00E  ?W  SCSI test control register (SCSITEST) (see #P0613)
+00F  R-  SCSI status register 4 (SSTAT4) (see #P0614)
+00F  -W  clear SCSI interrupt register 4 (CLRSINT4) (see #P0615)
+010  RW  SCSI interrupt mode register 0 (SIMODE0) (see #P0616)
+011  RW  SCSI interrupt mode register 1 (SIMODE1) (see #P0617)
+012  RW  DMA control register 0 (DMACNTRL0) (see #P0618)
+013  RW  DMA control register 1 (DMACNTRL1) (see #P0619)
+014  RW  DMA status register (DMASTAT) (see #P0620)
+015  RW  FIFO status register (FIFOSTAT)
+016w RW  data port register (DATAPORT)
+018  RW  burst control register (BRSTCNTRL) (see #P0621)
+01A  RW  port A register (PORTA) (see #P0622)
+01B  RW  port B register (PORTB) (see #P0623)
+01C  RW  revision register (REV)
+01D  RW  stack register (STACK)
+01E  RW  test register (TEST) (see #P0624)
+01F  R?  (AIC-6360+) ID register (ID)
	  32-byte ID string can be read here
Notes:	the SCSI latched data register is used to transfer data on the SCSI bus
	  during automatic or manual PIO mode
	the SCSI data bus register reflects the state of SCSI data bus lines
	  directly

Bitfields for SCSI sequence control register (SCSISEQ):
Bit(s)	Description	(Table P0600)
 7	enable target mode (TEMODEO)
 6	enable selection out (ENSELO)
 5	enable selection in  (ENSELI)
 4	enable reselection in (ENRESELI)
 3	"ENAUTOATNO"
 2	"ENAUTOATNI"
 1	enable auto -ATN on parity error (ENAUTOATNP)
 0	SCSI reset out (SCSIRSTO)
Note:	each bit when set starts a specific SCSI sequence on the bus
SeeAlso: #P0602,#P0607,#P0608,#P0616

Bitfields for SCSI transfer control register 0 (SXFRCTL0):
Bit(s)	Description	(Table P0601)
 7	SCSI FIFO enable (SCSIEN)
 6	DMA  FIFO enable (DMAEN)
 5	channel enable (CHEN)
 4	clear SCSI transfer counter (CLRSTCNT)
 3	SCSI PIO enable (SPIOEN)
 2	SCAM enable (SCAMEN)
 1	clear channel (CLRCH)
 0	reserved
SeeAlso: #P0602,#P0607,#P0611,#P0618,#P0620

Bitfields for SCSI transfer control register 1 (SXFRCTL1):
Bit(s)	Description	(Table P0602)
 7	bit bucket (BITBUCKET)
 6	SCSI counter wrap enable (SWRAPEN)
 5	enable SCSI parity check (ENSPCHK)
 4-3	selection time-out select (STIMESEL)
	00 256 ms
	01 128 ms
	10 64  ms
	11 32  ms
 2	enable selection timer (ENSTIMER)
 1	byte align (BYTEALIGN)
 0	reserved
SeeAlso: #P0600,#P0601

Bitfields for SCSI control signal read register (SCSISIGI):
Bit(s)	Description	(Table P0603)
 7	-C/D input (CDI)
 6	-I/O input (IOI)
 5	-MSG input (MSGI)
 4	-ATN input (ATNI)
 3	-SEL input (SELI)
 2	-BSY input (BSYI)
 1	-REQ input (REQI)
 0	-ACK input (ACKI)
Note:	this register reflects the actual state of the SCSI bus control lines
SeeAlso: #P0604

Bitfields for SCSI control signal write register (SCSISIGO):
Bit(s)	Description	(Table P0604)
 7	-C/D output (CDO)
 6	-I/O output (IOO)
 5	-MSG output (MSGO)
 4	-ATN output (ATNO)
 3	-SEL output (SELO)
 2	-BSY output (BSYO)
 1	-REQ output (REQO)
 0	-ACK output (ACKO)
Notes:	writing to this register modifies the control signals on the bus; only
	  those signals that are allowed in the current mode (initiator/target)
	  are asserted
	bits 7-5 in initiator mode represent the expected SCSI bus phase and
	  can be used to trigger phase mismatch and phase change interrupts
SeeAlso: #P0603

Bitfields for SCSI rate control register (SCSIRATE):
Bit(s)	Description	(Table P0605)
 7	reserved
 6-4	synchronous transfer rate (SXFR)
	rate = 100 + SXFR * 25 (ns)
 3-0	synchronous offset (SOFS)
Note:	contents of this register determine the synchronous SCSI data transfer
	  rate and the maximum synchronous -REQ/-ACK offset; an offset of 0 in
	  the bits 3-0 disables synchronous data transfers, any offset value
	  greater than 0 enables snchronous transfers
SeeAlso: #P0611

Bitfields for SCSI ID register (SCSIID):
Bit(s)	Description	(Table P0606)
 7	reserved
 6-4	our ID (OID)
 3	reserved
 2-0	target ID (TID)
Note:	this register contains the SCSI ID of the board and the current target
	  on the selected channel
SeeAlso: #P0982

Bitfields for SCSI status register 0 (SSTAT0):
Bit(s)	Description	(Table P0607)
 7	target mode (TARGET)
 6	selection out done (SELDO)
 5	selection in  done (SELDI)
 4	selection in progress (SELINGO)
 3	SCSI counter wrap (SWRAP)
 2	SCSI PIO done  (SDONE)
 1	SCSI PIO ready (SPIORDY)
 0	DMA done (DMADONE)
Note:	bits 1-0 and 6-4 are self-clearing
	bit 2 is set when the SCSI transfer count register decrements to 0
SeeAlso: #P0600,#P0601,#P0608,#P0616

Bitfields for clear SCSI interrupt register 0 (CLRSINT0):
Bit(s)	Description	(Table P0608)
 7	set SCSI PIO done? (SETSDONE)
 6	clear selection out done (CLRSELDO)
 5	clear selection in  done (CLRSELDI)
 4	clear selection in progress (CLRSELINGO)
 3	clear SCSI counter wrap (CLRSWRAP)
 2	clear SCSI PIO done (CLRSDONE)
 1	clear SCSI PIO ready (CLRSPIORDY)
 0	reserved
Note:	writing 1 to a bit clears the associated SCSI interrupt; writing 1 to
	  the bits 3-2 also clears the asscoiated bits in SSTAT0
SeeAlso: #P0600,#P0601,#P0607,#P0616

Bitfields for SCSI status register 1 (SSTAT1):
Bit(s)	Description	(Table P0609)
 7	selection time-out (SELTO)
 6	(target) "ATNTARG"
 5	SCSI reset in (SCSIRSTI)
 4	phase mismatch (PHASEMIS)
 3	bus free (BUSFREE)
 2	SCSI parity error (SCSIPERR)
 1	phase changed (PHASECHG)
 0	-REQ asserted (REQINIT)
Notes:	bit 0 can be cleared by setting bit 0 in the clear SCSI interrupt 1
	  register (CLRSINT1), and by asserting -ACK as well
	bit 4 is self-clearing
SeeAlso: #P0602,#P0603,#P0604,#P0610,#P0617

Bitfields for clear SCSI interrupt register 1 (CLRSINT1):
Bit(s)	Description	(Table P0610)
 7	clear selection time-out (CLRSELTIMEO)
 6	clear -ATN output (CLRATNO)
 5	clear SCSI reset in (CLRSCSIRSTI)
 4	reserved
 3	clear bus free (CLRBUSFREE)
 2	clear SCSI parity error (CLRSCSIPERR)
 1	clear phase changed (CLRPHASECHG)
 0	clear -REQ asserted (CLRREQINIT)
Note:	writing 1 to a bit clears the associated SCSI interrupt; writing 1 to
	  the bits 3-0, 5, and 7 also clears the associated bits in SSTAT1
SeeAlso: #P0603,#P0604,#P0609,#P0617

Bitfields for SCSI status register 2 (SSTAT2):
Bit(s)	Description	(Table P0611)
 7-6	reserved
 5	"SOFFSET"
 4	SCSI FIFO empty (SEMPTY)
 3	SCSI FIFO full	(SFULL)
 2-0	SCSI FIFO count (SFCNT)
Note:	the SCSI FIFO is 8 bytes long; bit 3 is set when all the 8 bytes are
	  full (bits 2-0 are clear)
SeeAlso: #P0601,#P0605,#P0614,#P0615

Bitfields for SCSI status register 3 (SSTAT3):
Bit(s)	Description	(Table P0612)
 7-4	"SCSICNT"
 3-0	"OFFCNT"
SeeAlso: #P0605,#P0611

Bitfields for SCSI test control register (SCSITEST):
Bit(s)	Description	(Table P0613)
 7-4	reserved
 3	"SCTESTU"
 2	"SCTESTD"
 1	reserved
 0	"STCTEST"
SeeAlso: #P0624

Bitfields for SCSI status register 4 (SSTAT4):
Bit(s)	Description	(Table P0614)
 7-3	reserved
 2	"SYNCERR"
 1	FIFO write error? (FWERR)
 0	FIFO read  error? (FRERR)
SeeAlso: #P0611,#P0615

Bitfields for clear SCSI interrupt register 4 (CLRSINT4):
Bit(s)	Description	(Table P0615)
 7-3	reserved
 2	"CLRSYNCERR"
 1	clear FIFO write error? (CLRFWERR)
 0	clear FIFO read	 error? (CLRFRERR)
SeeAlso: #P0611,#P0614

Bitfields for SCSI interrupt mode register 0 (SIMODE0):
Bit(s)	Description	(Table P0616)
 7	reserved
 6	enable selection out done (ENSELDO)
 5	enable selection in  done (ENSELDI)
 4	enable selection in progress (ENSELINGO)
 3	enable SCSI counter wrap (ENSWRAP)
 2	enable SCSI PIO done  (ENSDONE)
 1	enable SCSI PIO ready (ENSPIORDY)
 0	enable DMA done (ENDMADONE)
Note:	setting any bit will enable the corresponding function to interrupt
	  via the IRQ pin
SeeAlso: #P0607,#P0608,#P0617,#P0618

Bitfields for SCSI interrupt mode register 1 (SIMODE1):
Bit(s)	Description	(Table P0617)
 7	enable selection time-out (ENSELTIMO)
 6	(target) "ENATNTARG"
 5	enable SCSI reset (ENSCSIRST)
 4	enable phase mismatch (ENPHASEMIS)
 3	enable bus free (ENBUSFREE)
 2	enable SCSI parity error (ENSCSIPERR)
 1	enable phase changed (ENPHASECHG)
 0	enable -REQ asserted (ENREQINIT)
Note:	setting a bit enables the corresponding function to interrupt via the
	  IRQ pin
SeeAlso: #P0609,#P0610,#P0616

Bitfields for DMA control register 0 (DMACNTRL0):
Bit(s)	Description	(Table P0618)
 7	enable DMA (ENDMA)
 6	=0 16-bit mode
	=1 8-bit mode (8BIT)
 5	=0 PIO mode
	=1 DMA mode
 4	double word PIO (DWORDPIO)
 3	=0 read
	=1 write
 2	interrupt enable (INTEN)
 1	reset FIFO (RSTFIFO)
 0	software interrupt (SWINT)
Note:	write to this register takes the controller from the power down mode
SeeAlso: #P0601

Bitfields for DMA control register 1 (DMACNTRL1):
Bit(s)	Description	(Table P0619)
 7	power down (PWRDWN)
 6	"ENSTK32"
 5	reserved
 4-0	stack pointer? (STK)

Bitfields for DMA status register (DMASTAT):
Bit(s)	Description	(Table P0620)
 7	"ATDONE"
 6	word ready (WORDRDY)
 5	interrupt status (INTSTAT)
 4	DMA FIFO full  (DFIFOFULL)
 3	DMA FIFO empty (DFIFOEMP)
 2	(AIC-6360+?) DMA FIFO half-full? (DFIFOHF)
 1	(AIC-6360+?) double word ready (DWORDRDY)
 0	reserved
SeeAlso: #P0601,#P0618

Bitfields for burst control register (BRSTCNTRL):
Bit(s)	Description	(Table P0621)
 7-4	bus on	time (BON)
 3-0	bus off time (BOFF)
Note:	the bus on/off times are in microseconds
SeeAlso: #P0624

Bitfields for port A register (PORTA):
Bit(s)	Description	(Table P0622)
 7	transfer mode
	=0 PIO
	=1 DMA
 6	boot enabled (BOOT)
 5-4	message classes (MSGCLASSES)
	00 #4
	01 #0, #1, #2, #3, #4
	10 #0, #3, #4
	11 #0, #4
 3	initial synchronous negotiation enabled (SYNCNEG)
 2	target disconnect enabled (TARDISC)
 1-0	reserved
SeeAlso: #P0623

Bitfields for port B register (PORTB):
Bit(s)	Description	(Table P0623)
 7	SCSI parity enabled (PARITY)
 6-5	DMA channel (DMACHAN)
	00 DMA channel 0
	01 DMA channel 5
	10 DMA channel 6
	11 DMA channel 7
 4-3	"IRQ"
	00,11 IRQ12
	01 IRQ10
	10 IRQ11
 2-0	SCSI ID
SeeAlso: #P0622

Bitfields for test register (TEST):
Bit(s)	Description	(Table P0624)
 7	reserved
 6	bus off timer test (BOFFTMR)
 5	bus on	timer test (BONTMR)
 4	SCSI transfer count register high   byte test (STCNTH)
 3	SCSI transfer count register middle byte test (STCNTM)
 2	SCSI transfer count register low    byte test (STCNTL)
 1	SCSI block test (SCSIBLK)
 0	DMA  block test (DMABLK)
SeeAlso: #P0613,#P0621
----------P03480357--------------------------
PORT 0348-0357 - DCA 3278
----------P034C034F--------------------------
PORT 034C-034F - Gravis UltraMax by Advanced Gravis
Range:	The I/O address range is dipswitch selectable from:
	   0200-020F and 0300-030F
	   0210-021F and 0310-031F
	   0220-022F and 0320-032F
	   0230-023F and 0330-033F
	   0240-024F and 0340-034F
	   0250-025F and 0350-035F
	   0260-026F and 0360-036F
	   0270-027F and 0370-037F
----------P035A035B--------------------------
PORT 035A-035B - Adaptec AH1520 jumper settings

035A  R	  I/O channel setup (see #P0625)
035B  R	  transfer mode setup (see #P0626)

Bitfields for Adaptec AH1520 channel setup jumper settings:
Bit(s)	Description	(Table P0625)
 7	SCSI parity disabled
 6-5	DMA channel (00 = channel 0, 01 = 5, 10 = 6, 11 = 7)
 4-3	IRQ number (00 = IRQ9, 01 = IRQ10, 10 = IRQ11, 11 = IRQ12)
 2-0	SCSI ID
SeeAlso: #P0626

Bitfields for Adaptec AH1520 transfer mode setup jumper settings:
Bit(s)	Description	(Table P0626)
 7	DMA transfer mode (clear for PIO)
 6	boot enabled
 5-4	boot type
	00 ???
	01 boot from floppy
	10 print configured options
	11 boot from hard disk
 3	enable sync negotiation
 2	enable target disconnection
 1-0	unused???
SeeAlso: #P0625
----------P035F------------------------------
PORT 035F - ARTEC Handyscanner A400Z.  alternate address at 15F.
----------P03600367--------------------------
PORT 0360-0367 - PC network (XT only)
----------P0360036F--------------------------
PORT 0360-036F - PC network (AT)
----------P0360036F--------------------------
PORT 0360-036F - National Semiconductor DP8390(1)C/NS3249C network chipset
Note:	cards based on this IEEE 802.3 networking chipset can use any range
	  of 16 consecutive addresses, and provide a total of four pages of
	  sixteen registers (see #P0627,#P0628,#P0629,#P0759)

(Table P0627)
Values for NS DP8390C/NS3249C network chipset Page 0 registers:
Number	Read Register				Write Register
 00h	Command reg. (see #P0631)	CR	Command reg.		CR
 01h	current local DMA address 0	CLDA0	page start reg.		PSTART
 02h	current local DMA address 1	CLDA1	page stop reg.		PSTOP
 03h	boundary pointer		BNRY	boundary pointer	BNRY
 04h	transmit status reg.		TSR	Tx page start address	TPSR
 05h	number of collisions reg.	NCR	Tx byte count reg.0	TBCR0
 06h	FIFO					Tx byte count reg.1	TBCR1
 07h	interrupt status reg.		ISR	interrupt status reg.	ISR
 08h	current remote DMA address 0	CRDA0	remote start addr.reg.0 RSAR0
 09h	current remote DMA address 1	CRDA1	remote start addr.reg.1 RSAR1
 0Ah	reserved				remote byte count reg.0 RBCR0
 0Bh	reserved				remote byte count reg.1 RBCR1
 0Ch	receive status reg.		RSR	Rx configuration reg.	RCR
 0Dh	tally counter 0 (frame errors)	CNTR0	Tx configuration reg.	TCR
 0Eh	tally counter 1 (CRC errors)	CNTR1	data configuration reg. DCR
 0Fh	tally counter 2 (missed pkt)	CNTR2	interrupt mask reg.	IMR
SeeAlso: #P0628,#P0629,#P0630

(Table P0628)
Values for NS DP8390C/NS3249C network chipset Page 1 registers:
Number	Read/Write
 00h	Command			CR (see #P0631)
 01h	physical address reg.0	PAR0
 02h	physical address reg.1	PAR1
 03h	physical address reg.2	PAR2
 04h	physical address reg.3	PAR3
 05h	physical address reg.4	PAR4
 06h	physical address reg.5	PAR5
 07h	current page reg.	CURR
 08h	multicast address reg.0 MAR0
 09h	multicast address reg.1 MAR1
 0Ah	multicast address reg.2 MAR2
 0Bh	multicast address reg.3 MAR3
 0Ch	multicast address reg.4 MAR4
 0Dh	multicast address reg.5 MAR5
 0Eh	multicast address reg.6 MAR6
 0Fh	multicast address reg.7 MAR7
SeeAlso: #P0627,#P0629,#P0630

(Table P0629)
Values for NS DP8390C/NS3249C network chipset Page 2 registers:
Number	Read Register				Write Register
 00h	Command				CR	Command			 CR
 01h	page start reg.			PSTART	current local DMA addr.0 CLDA0
 02h	page stop reg.			BPSTOP	current local DMA addr.1 CLDA1
 03h	remote next packet pointer		remote next packet pointer
 04h	Tx page start address		TPSR	reserved
 05h	local next packet pointer		local next packet pointer
 06h	address counter (upper)			address counter (upper)
 07h	address counter (lower)			address counter (lower)
 08h	reserved				reserved
 09h	reserved				reserved
 0Ah	reserved				reserved
 0Bh	reserved				reserved
 0Ch	Rx configuration reg.		RCR	reserved
 0Dh	Tx configuration reg.		TCR	reserved
 0Eh	data configuration reg.		DCR	reserved
 0Fh	interrupt mask reg.		IMR	reserved
Note:	this is a diagnostics page, and should never be modfied under normal
	  operation.
SeeAlso: #P0627,#P0628,#P0630

(Table P0630)
Values for NS DP8390C/NS3249C network chipset Page 3 registers:
Number	Read Register				Write Register
 00h	Command CR (see #P0631)			Command CR
Note:	Test Page - should never be modified!
SeeAlso: #P0627,#P0628,#P0629

Bitfields for NS DP8390C/NS3249C network chipset command register (00h):
Bit(s)	Description	(Table P0631)
 0	software reset command (1=offline, 0=online)
 1	do not activate NIC after reset command
 2	start transmision of a packet
 3-5	remote DMA command
	000 not allowed
	001 remote read
	010 remote write
	011 send packet
	1xx abort/complete rmote DMA
 6-7	page select
	00 register page 0
	01 register page 1
	10 register page 2
	11 register page 3
SeeAlso: #P0630
----------P036B------------------------------
PORT 036B - GI1904 Scanner Interface Adapter
Range:	PORT 022Bh, PORT 026Bh, PORT 02ABh (default), PORT 02EBh, PORT 032Bh,
	  PORT 03ABh, PORT 03EBh
----------P036C------------------------------
PORT 036C - GS-IF Scanner Interface adapter
Range:	PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
	  PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:	many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
	  others use this interface
----------P03700377--------------------------
PORT 0370-0377 - FDC 2	(2nd Floppy Disk Controller)	first FDC at 03F0
Note:	floppy disk controller is usually an 8272, 8272A, NEC765 (or
	  compatible), or an 82072 or 82077AA for perpendicular recording at
	  2.88M
SeeAlso: PORT 03F0h-03F7h

0370  R-  diskette Extra High Density controller board jumpers (AT)
0370  R-  diskette controller status A (PS/2, PS/2 model 30)
0371  R-  diskette controller status B (PS/2, PS/2 model 30)
0372  -W  diskette controller DOR (Digital Output Register)
0374  R-  diskette controller main status register
0374  -W  diskette controller datarate select register
0375  RW  diskette controller command/data register
0376  RW  (2nd FIXED disk controller status/data register)
0377  RW  (2nd FIXED disk controller drive address register)
0377  R-  diskette controller DIR (Digital Input Register)
0377  -W  select register for diskette data transfer rate
----------P0378------------------------------
PORT 0378 - Covox 'Speech Thing' COMPATIBLE SPEECH OUTPUT
SeeAlso: PORT 022Fh"mc-soundmachine",PORT 0388h-038Fh"soundmachine"

0378  -W  speech output via printer port
	  (with mc-soundmachine, enabled if bit4=1 in 38F)
----------P0378037A--------------------------
PORT 0378-037A - PARALLEL PRINTER PORT (usually LPT2, sometimes LPT3)
Range:	usually PORT 03BCh, PORT 0278h, or PORT 0378h
SeeAlso: MEM 0040h:000Ah,INT 17/AH=00h

0378  -W  data port
0379  R-  status port (see #P0658 at PORT 03BCh)
037A  RW  control port (see #P0659 at PORT 03BCh)

037B  ??  bit 7: shadow RAM on/off (UniRAM adapter,according to c't 7/90)
----------P0378037F--------------------------
PORT 0378-037F - Intel 82360SL/82091AA - EPP-mode PARALLEL PORT
Range:	PORT 0278h or PORT 0378h
SeeAlso: PORT 0278h"LPT1",PORT 0778h"ECP"

0378-037A	as for standard parallel port
037B  RW  address strobe
037C  RW  data strobe 0
037D  RW  data strobe 1
037E  RW  data strobe 2
037F  RW  data strobe 3
----------P037C037F--------------------------
PORT 037C-037F - C&T F87000 Multi-Mode Peripheral Chip - OUTPUT PORTS

037C  -W  outputs driven to keyboard outputs COL7-COL0
037C  R-  inputs driven by keyboard pins ROW7-ROW0
037D  -W  outputs driven to keyboard outputs COL15-COL8
037E  -W  outputs driven to pins P2[7-1]; bit 0 enables UART clock when low
037F  -W  external output port
----------P0380038F--------------------------
PORT 0380-038F - 2nd BSC (Binary Synchronous Communication) adapter
SeeAlso:  PORT 03A0h"BSC"
----------P0380038C--------------------------
PORT 0380-038C - 2nd SDLC (Synchronous Data Link Control) adapter
Notes:	Initialization of the SDLC adapter is performed in a typical
	  sequence like this: Setup 8255 port A-C configuration by writing
	  98h to 383h, followed by initializing 8255 port C by writing 0Dh
	  to 382h. Reset 8273 internal registers by pulsing 8255 port B4.
	  After this the 8253 has to be programmed to the desired values
	  (counter 0 in mode 3). Now the 8273 is ready to be configured for
	  the operating mode that defines the communication environment in
	  which it will be used.
	Note on 8273: Each 8273 protocol controllers internal register is
	  programmed by individual set/reset commands (via 388h) in
	  conjunction with a parameter (via 389h) that give an OR/AND mask
	  to the internal register value.
	  Although the 8273 is a full duplex device, there is only one
	  command register. Thus, the command register must be used for
	  only one command sequence at a time and the transmitter and
	  receiver may never be simultaneously in a command phase.
	  The system software starts the command phase by writing a command
	  byte into the command register. If further information is required
	  by the 8273 prior to execution of the command, the system software
	  must write the list of parameters into the parameter register.
SeeAlso: PORT 03A0h"SDLC"

0380  R-   on adapter 8255(A5) port A: internal/external sensing (see #P0632)
0381  -W   on adapter 8255(A5) port B: external modem interface (see #P0633)
0382  RW   on adapter 8255(A5) port C: internal control (see #P0634)
0383  ?W   on adapter 8255(A5) mode initialization
0384  RW   on adapter 8253 (programmable counter) counter 0:
		LSB / MSB square wave generator (input for timer 2, connected
		  to 8255 bitC5)
0385  RW   on adapter 8253 counter 1: LSB / MSB inactivity time-outs
		(connected to 8255 bitA7, IRQ4 level)
0386  RW   on adapter 8253 counter 2: LSB / MSB inactivity time-outs
		(connected to 8255 bitA6, IRQ4 level)
0387  ?W   on adapter 8253 mode register (see #P0635)
0388  R-   on adapter 8273 status register (see #P0636)
0388  -W   on adapter 8273 command register (see #P0637)
0389  R-   on adapter 8273 (immediate) result register (see #P0644)
0389  -W   on adapter 8273 parameter register
	    Commands issued via PORT 0388h may need additional parameters,
	      which have to be passed through this port (see table).
038A  R-   on adapter 8273 transmit INT status (DMA/INT)
038A  -W   on adapter 8274 reset
038B  R-   on adapter 8273 receive INT status (DMA/INT)
038C  -W   on adapter 8273 data: direct program control (DPC)
	  scratch-pad

Bitfields for SDLC 8255 port A:
Bit(s)	Description	(Table P0632)
 7	=1 timer 1 output active
 6	=1 timer 2 output active
 5	=1 modem status changed
 4	receive clock active (if pulsing)
 3	=0 clear to send is on from interface
 2	transmit clock active (if pulsing)
 1	=0 data carrier detect is on from interface
 0	=0 ring indicator is on from interface
SeeAlso: #P0633,#P0634

Bitfields for SDLC 8255 port B:
Bit(s)	Description	(Table P0633)
 7	enable IRQ 4 level interrupt
 6	=1 gate timer 1
 5	=1 gate timer 2
 4	=1 reset 8273
 3	=1 reset modem status changed logic
 2	=0 turn on test
 1	=0 turn on select standby at modem interface
 0	=0 turn on data signal rate select at modem interface
SeeAlso: #P0632,#P0634

Bitfields for SDLC 8255 port C:
Bit(s)	Description	(Table P0634)
 7 R-	=? not used (detection: =1 SDLC, =0 may be SDLC or BSC??)
 6 R-	=0 test indicate active
 5 R-	timer 0 output (if pulsing)
 4 R-	receive data (if pulsing)
 3 -W	=0 gate interrupts 3 and 4
 2 -W	=1 electronic wrap
 1 -W	=1 gate external clock
 0 -W	=1 gate internal clock
SeeAlso: #P0632,#P0633

Bitfields for SDLC 8253 mode register:
Bit(s)	Description	(Table P0635)
 7-6	SC1-SC0	 00, 01, 10= select counter 0,1,2; 11=illegal
 5-4	RL1-RL0	 00= couner latching operation
		 01= read/load most significant byte (MSB)
		 10= read/load least significant byte (LSB)
		 11= read/load LSB first, then MSB
 3-1	M2-M0	 000= mode 0
		 001= mode 1
		 x10= mode 2
		 x11= mode 3
		 100= mode 4
		 101= mode 5
 0	BCD	 0= binary counter 16bits
		 1= BCD counter 4 decades

Bitfields for SDLC 8273 status register:
Bit(s)	Description	(Table P0636)
 7	=1 command busy (CBSY)
 6	=1 command buffer full (CBF)
 5	=1 command parameter buffer full (CPBF)
 4	=1 command result buffer full (CRBF)
 3	=1 Rx interupt (RxINT)
 2	=1 Tx interupt (TxINT)
 1	=1 RxINT result available (RxIRA)
 0	=1 TxINT result available (TxIRA)
SeeAlso: #P0637

(Table P0637)
Values for SDCL 8273 command register:
 commands:		   parameters:	results:   result port: int:
  A4: set one-bit delay	    set mask	 -	       -	no
  64: reset one-bit delay   reset mask	 -	       -	no
  97: set data transfer	    set mask	 -	       -	no
  57: reset data transfer   reset mask	 -	       -	no
  91: set operating mode    set mask	 -	       -	no
  51: reset operating mode  reset mask	 -	       -	no
  A0: set serial I/O mode   set mask	 -	       -	no
  60: reset serial I/O mode reset mask	 -	       -	no
  C0: general receive	    B0,B1	 RIC,R0,R1,A,C RXI/R   yes
  C1: selective receive	    B0,B1,A1,A2	 RIC,RD,R1,A,C RXI/R   yes
  C5: receive disable	    -		 -	       -	no
  C8: transmit frame	    L0, L1, A, C TIC	       TXI/R   yes
  C9: transmit transparent  L0, L1	 TIC	       TXI/R   yes
  CC: abort transmit frame  -		 TIC	       TXI/R   yes
  CD: abort transmit	    -		 TIC	       TXI/R   yes
  22: read 8273 port A	    -		 port value    result	no
  23: read 8273 port B	    -		 port value    result	no
  A3: set 8273 port A bit   set mask	 -	       -	no
  63: set 8273 port B bit   reset mask	 -	       -	no
Notes:	B0/B1 LSB/MSB of the receiver buffer length
	L0/L1 LSB/MSB of the Tx buffer length
	A1/A2 receive frame address match field one/two
	A     address fieldof received frame. In non-buffered mode, this
	      result is not provided.
	C     control field of received frame. In non-buffered mode, this
	      result is not provided.
	RXI/R TXI/R receive/transmit interrupt result register
	R0/R1 LBS/MSB of the length of the frame received
	RIC/TIC receiver/transmitter interrupt result code
SeeAlso: #P0638,#P0639,#P0640,#P0641,#P0642,#P0643

Bitfields for SDLC 8273 interal port A: Modem Control Input Port:
Bit(s)	Description	(Table P0638)
 7-5	not used
 4	DSR change (PA4)
 3	CTS change (PA3)
 2	Data Set Ready (PA2)
 1	Carrier Detect (PA1)
 0	Clear to Send (PA0)
SeeAlso: #P0637

Bitfields for SDLC 8273 interal port B: Modem Control Output Port:
Bit(s)	Description	(Table P0639)
 7-6	not used
 5	Flag Detect (PB5)
 4-3	reserved
 2	Data Terminal Ready (PB2)
 1	reserved (PB1)
 0	Request to Send (PB0)
SeeAlso: #P0637

Bitfields for SDLC 8273 internal: Operating Mode Register:
Bit(s)	Description	(Table P0640)
 7-6	not used
 5	=1 HDLC abort enable
 4	=1 EOP interrupt enable
 3	=1 enable early Tx interrupt
 2	=1 Buffered Mode
 1	=1 Two Preframe Sync Characters
 0	=1 Flag Stream Mode
SeeAlso: #P0637

Bitfields for SDLC 8273 internal: Serial I/O Register:
Bit(s)	Description	(Table P0641)
 7-3	not used
 2	=1 Data Loopback
 1	=1 Clock Loopback
 0	=1 NRZI Mode
SeeAlso: #P0637

Bitfields for SDLC 8273 internal: Data Transfer Mode Register:
Bit(s)	Description	(Table P0642)
 7-1	not used
 0	=1 Interrupt Data Transfers
SeeAlso: #P0637

Bitfields for SDLC 8273 internal: One-Bit Delay Mode Register:
Bit(s)	Description	(Table P0643)
 7 =1	One-Bit Delay Enable
 6-0	not used
SeeAlso: #P0637

(Table P0644)
Values for SDLC 8273 result register:
 transmit result codes:		 status after interrupt:
  0C: early transmit interrupt	  transmitter active
  0D: frame transmit complete	  idle or flags
  0E: DMA underrun		  abort
  0F: clear to send error	  abort
  10: abort complete		  idle or flags
 receive result codes:
  X0: A1 match / general receive  active
  X1: A2 match			  active
  03: CRC error			  active
  04: abort detected		  active
  05: idle detected		  disabled
  06: EOP detected		  disabled
  07: frame less than 32 bits	  active
  08: DMA overrun		  disabled
  09: memory buffer overflow	  disabled
  0A: carrier detect failure	  disabled
  0B: receiver interrupt overrun  disabled
 X bits received inlast byte:
   E: all eight bits of last byte (bit7-0)
   0: bit0 only
   8: bit1-0
   4: bit2-0
   C: bit3-0
   2: bit4-0
   A: bit5-0
   6: bit6-0
--------s-P03840387--------------------------
PORT 0384-0387 - Pro Audio Spectrum 16 (PAS16)
Range:	PORT 0280h, PORT 0284h, PORT 0288h, PORT 028Ch, PORT 384h,
	  PORT 0388h (default), or PORT 038Ch
----------P03880389--------------------------
PORT 0388-0389 - AdLib - MONO SOUND OUTPUT
Note:	also supported by SoundBlaster and compatibles
SeeAlso: PORT 0220h-0223h,PORT 0388h-038Fh"soundmachine"

0388  R-  both speakers -- Status
	    bit7  : interrupt request (IRQ)
	    bit6  : timer 1 overflow
	    bit5  : timer 2 overflow
	    bit4-0: reserved
0388  -W  both speakers -- Address port (see #P0645)
	index in OPL2 (YMF3812), OPL3 (YMF262), OPL4 (YF278-F)
0389  -W  data port
Note:	the AdLib requires a delay of 3.3 microseconds between writing to
	  PORT 0388h and writing to PORT 0389h, and a delay of 23 microseconds
	  after a write to PORT 0389h before any other operation is allowed

(Table P0645)
Values for AdLib address port index:
 01h	Enable waveform control
	bit 7-6: (OPL4, OPL3 in OPL2 mode only) lsi test
	bit 5: (OPL2 only) wave select enable (WS)
	       (OPL4, OPL3) lsi test
	bit 4-0: lsi test
 02h	Timer #1 data (OPL2 and OPL3 in OPL2 mode only)
 03h	Timer #2 data (OPL2 and OPL3 in OPL2 mode only)
 04h	Timer control flags (OPL2 and OPL3 in OPL2 mode only)
	bit 7  : reset interrupt (RST)
	bit 6  : timer 1 mask (MASK1)
	bit 5  : timer 2 mask (MASK2)
	bit 4-2: reserved
	bit 1  : start timer 2 (ST2)
	bit 0  : start timer 1 (ST1)
 04h	(OPL3 in OPL3 mode only) connection select
	bit 7-6: reserved
	bit 5-0: connection selection
 05h	(OPL3) compatibility register
	bit 7-1: reserved
	bit 0: enable OPL3 mode (NEW), default disabled
 08h	Speech synthesis mode
	bit 7: (OPL2 only) speech synthesis or FM music mode (CSM)
	bit 6: select keyboard split point (SEL/NTS)
	bit 5-0: reserved
 20h-35h Amplitude Modulation / Vibrato
	bit 7: AM modulation (AM)
	bit 6: vibrato (VIB)
	bit 5: sustain (EG)
	bit 4: keyboard scaling rate (KSR)
	bit 3-0: multi (MF)
 40h-55h Level key scaling / Total level
	bit 7-6: key scale level (KSL)
	bit 5-0: total level (TL)
 60h-75h Attack / Decay rate
	bit 7-4: attack rate
	bit 3-0: decay rate
 80h-95h Sustain / Release rate
	bit 7-4: sustain level
	bit 3-0: release rate
 A0h-A8h Octave / Frequency (LSB)
 A9h-AFh ???
 B0h-B8h Octave / Frequency Number
	bit 7-6: reserved
	bit 5  : key on, mute
	bit 4-2: block, octave
	bit 1-0: f-number (MSB)
 BDh	percussion, vibrato, AM	(OPL2, OPL3 in OPL2 mode only)
	bit 7: amplitude modulation (AM)
	bit 6: vibrato (VIB)
	bit 5: ryhthm, percussion on/off (R)
	bit 4: bass drum on/off (BD)
	bit 3: snare drum on/off (SD)
	bit 2: tom-tom on/off (TOM)
	bit 1: top cymbal on/off (TC)
	bit 0: hi hat on/off (HH)
 C0h-C8h Feedback / Algorithm
	bit 7-4: OPL3: channel D-A
	bit 3-1: feedback
	bit 0: connection
 E0h-F5h Waveform Selection
	bit 7-3: reserved
	bit 2  : (OPL3) waveform bit2
	bit 1-0: waveform
SeeAlso: #P0646

(Table P0646)
Values for Sound Blaster registers inside groups:
Offset
 +00..+02: operators 1-3    modulator channel 1-3
 +03..+05: operators 4-6    carrier channel 1-3
 +08..+0A: operators 7-9    modulator channel 4-6
 +0B..+0D: operators 10-12  carrier channel 4-6
 +10..+12: operators 13-15  modulator channel 7-9
 +13..+15: operators 16-18  carrier channel 7-9
 +06, +07, +0E, +0F: reserved
SeeAlso: #P0645
----------P03880389--------------------------
PORT 0388-0389 - Soundblaster PRO FM-Chip
----------P0388038B--------------------------
PORT 0388-038B - Soundblaster 16 ASP FM-Chip
--------s-P0388038B--------------------------
PORT 0388-038B - Pro Audio Spectrum 16 (PAS16)
Range:	PORT 0280h, PORT 0284h, PORT 0288h, PORT 028Ch, PORT 384h,
	  PORT 0388h (default), or PORT 038Ch
----------P0388038F--------------------------
PORT 0388-038F - mc-soundmachine, mc 03-04/1992 - SPEECH I/O
Note:	Adlib-compatible, Covox 'voice master' & 'speech thing' compatible
	  soundcard
SeeAlso: PORT 022Fh"soundmachine",PORT 0278h"Covox"

0388  -W  Covox 'speech thing' compatible speech output via printer port?
	    enabled if bit 6 set in PORT 038Fh
0388  RW  Adlib compatible (YM3812), enabled if bit 0 set in PORT 038Fh
	    (see PORT 0388h-0389h"Sound Blaster")
0389  -W  Adlib compatible (YM3812), enabled if bit 0 set in PORT 038Fh
	    (see PORT 0388h-0389h"Sound Blaster")
038A  -W  IýC control for TDA7302 NF-MUX and X24C04 EEPROM
	    bit 7: IýC bus SDA out (data),  enabled if bit2=1 in PORT 038Fh
	    bit 0: IýC bus SCL out (clock), enabled if bit2=1 in PORT 038Fh
038B  R-  IýC status for TDA7302 NF-MUX and X24C04 EEPROM
	    bit 7: IýC bus SDA in (data),  enabled if bit2=1 in PORT 038Fh
	    bit 0: IýC bus SCL in (clock), enabled if bit2=1 in PORT 038Fh
038F  RW  configuration port (power on default=0, all features disabled)
	(see #P0647)

Bitfields for mc-soundmachine configuration port:
Bit(s)	Description	(Table P0647)
 7	Covox 'voice master' enabled at PORT 022Fh
 6	 ""   'speech thing' enabled at PORT 03BCh
 5	 ""		     enabled at PORT 0278h
 4	 ""		     enabled at PORT 0378h
 3	not used (0388???)
 2	IýC bus enabled (see PORT 038Ah,PORT 038Bh)
 1	gameport enabled (see PORT 0201h)
 0	AdLib registers (see PORT 0388h,PORT 0389h) enabled
--------s-P038C038F--------------------------
PORT 038C-038F - Pro Audio Spectrum 16 (PAS16)
Range:	PORT 0280h, PORT 0284h, PORT 0288h, PORT 028Ch, PORT 384h,
	  PORT 0388h (default), or PORT 038Ch
----------P03900397--------------------------
PORT 0390-0397 - Sunshine EW-901B, EW-904B
		EPROM writer card for EPROMs up to 27512
0390-0393  ??  adresses of the 8255 on the EW-90xB
----------P0390039F--------------------------
PORT 0390-039F - Cluster adapter (AT)

0390  ??  (adapter 0)	(XT)
0391  ??  (adapter 0)	(XT)
0392  ??  (adapter 0)	(XT)
0393  ??  (adapter 0)	(XT)
----------P03980399--------------------------
PORT 0398-0399 - Dell Enhanced Parallel Port
SeeAlso: PORT 002Eh,PORT 015Ch,PORT 026Eh

0398  -W  index for data port
0399  RW  EPP command data
----------P03980399--------------------------
PORT 0398-0399 - Intel 82091AA Advanced Integrated Peripheral
Range:	PORT 0022h (X-Bus), PORT 0024h (X-Bus), PORT 026Eh (ISA), or
	  PORT 0398h (ISA)
SeeAlso: PORT 0022h"82091AA",PORT 0024h"82091AA",PORT 026Eh"82091AA"

0398  ?W  configuration register index
0399  RW  configuration register data
----------P03A003AC--------------------------
PORT 03A0-03AC - 1st SDLC (Binary Synchronous Data Link Control adapter)
SeeAlso: PORT 0380h"SDLC"
----------P03A003AF--------------------------
PORT 03A0-03AF - 1st BSC (Binary Synchronous Communication) adapter
Notes:	Initialization of the BSC adapter is performed in a typical
	  sequence like this: Setup 8255 port A-C configuration by writing
	  98h to 383h, followed by initializing 8255 port C by writing 0Dh
	  to 382h. Reset 8251A internal registers by pulsing 8255 port B4.
	  After this the 8253 has to be programmed to the desired values
	  (counter 0 not used, counters 1 and 2 to mode 0). Now, the 8251A
	  is ready to be loaded with a set of control words that define the
	  communication environment.
	8251A: The control words are split into two formats, mode
	  instruction and command instruction. The mode instruction must
	  be inserted immediately after a reset operation (via 8255 port B4
	  or setting command instruction bit6 to 'internal reset').
	  The required synchronization characters are next loaded into the
	  8251A (usually 32h for BSC). All control words written to the
	  8251A after this will load the command instruction.
	     reset -> mode instruction
		      SYNC character 1
		      SYNC character 2
		      command instruction
		      data ...
		      command instruction
		      data ...
		      command instruction
		      ...
SeeAlso: PORT 0380h"BSC"

03A0  R-   on adapter 8255(A5) port A: internal/external sensing (see #P0648)
03A1  -W   on adapter 8255(A5) port B: external modem interface (see #P0649)
03A2  RW   on adapter 8255(A5) port C: internal control (see #P0650)
03A3  ?W   on adapter 8255(A5) mode initialization
03A4  RW   on adapter 8253 (programmable counter) counter 0:
		LSB / MSB square wave generator (unused in sync mode)
03A5  RW   on adapter 8253 counter 1: LSB / MSB inactivity time-outs
		(connected to 8255 bitA7, IRQ4 level)
03A6  RW   on adapter 8253 counter 2: LSB / MSB inactivity time-outs
		(connected to 8255 bitA6, IRQ4 level)
03A7  ?W   on adapter 8253 mode register (see #P0651)
03A8  RW   on adapter 8251: data (see #P0652)
03A9  R-   on adapter 8251: command/mode/USART status register (see #P0653)

Bitfields for BSC 8255 port A:
Bit(s)	Description	(Table P0648)
 7	=1 timer 1 output active
 6	=1 timer 2 output active
 5	=1 TxRDY active
 4	receive clock active (if pulsing)
 3	=0 clear to send is on from interface
 2	transmit clock active (if pulsing)
 1	=0 data carrier detect is on from interface
 0	=0 ring indicator is on from interface
SeeAlso: #P0649

Bitfields for BSC 8255 port B:
Bit(s)	Description	(Table P0649)
 7	=1 enable IRQ 4 level interrupt (timer 1 and 2)
 6	=1 gate timer 1
 5	=1 gate timer 2
 4	=1 reset 8251A
 3	=1 not used
 2	=0 turn on test
 1	=0 turn on select standby
 0	=0 turn on data signal rate select
SeeAlso: #P0648,#P0650

Bitfields for BSC 8255 port C:
Bit(s)	Description	(Table P0650)
 7 R-	=0 BSC adapter (=1 may be used to detect SDLC??)
 6 R-	=0 test indicate active
 5 R-	timer 0 output (if pulsing)
 4 R-	receive data (if pulsing)
 3 -W	=0 enable timer 1 and 2 IRQ4 and receive IRQ 4
 2 -W	=1 electronic wrap
 1 -W	=1 gate external clock
 0 -W	=1 gate internal clock
SeeAlso: #P0648,#P0649

Bitfields for BSC 8253 mode register:
Bit(s)	Description	(Table P0651)
 7-6	SC1-SC0	 00, 01, 10= select counter 0,1,2; 11=illegal
 5-4	RL1-RL0	 00= couner latching operation
		 01= read/load most significant byte (MSB)
		 10= read/load least significant byte (LSB)
		 11= read/load LSB first, then MSB
 3-1	M2-M0	 000= mode 0 (for counter 1 and 2)
		 001= mode 1 (not used for BSC)
		 x10= mode 2 (not used for BSC)
		 x11= mode 3 (not used for BSC)
		 100= mode 4 (not used for BSC)
		 101= mode 5 (not used for BSC)
 0	BCD	   0= binary counter 16bits
		   1= BCD counter 4 decades

Bitfields for BSC 8251 data:
Bit(s)	Description	(Table P0652)
---mode instruction (W)---
 7	=0 Double SYNC Character
 6	=1 SYNDET is an Input
 5	=1 Even Parity
 4	=1 Parity Enable
 3-2	Character Length 00=5bits, 01=6bits, 10=7bits, 11=8bits
 1-0	not used (always 0)
---SYNC character 1/2 (W)---
 string of two characters to be sync'ed at (in hunt mode).
---command instruction (W)---
 7	Enter Hunt Mode
 6	Internal Reset
 5	Request to Send
 4	Error Reset
 3	Send Break Character
 2	Receive Enable
 1	Data Terminal Ready
 0	Transmit Enable
---data (RW)---
	any data
SeeAlso: #P0651,#P0653

Bitfields for BSC 8251 command/mode/USART status:
Bit(s)	Description	(Table P0653)
 7	Data Set Ready (indicated that DSR is at 0 level)
 6	SYNDET
 5	Framing Error (not used for synchronous communications)
 4	Overrun Error (OE flag on when Overrun Error occurs)
 3	Parity Error (PE flag on when a parity error occurs)
 2	TxEmpty
 1	RxRDY (causing IRQ 3 level)
 0	TxRDY (has not the same meaning as 8251A TxRDY output pin).
	  THIS one is NOT conditioned by CTS and TxEnable (causing IRQ 4 level)
SeeAlso: #P0652
----------P03AB------------------------------
PORT 03AB - GI1904 Scanner Interface Adapter
Range:	PORT 022Bh, PORT 026Bh, PORT 02ABh (default), PORT 02EBh, PORT 032Bh,
	  PORT 036Bh, PORT 03ABh, PORT 03EBh
----------P03AC------------------------------
PORT 03AC - GS-IF Scanner Interface adapter
Range:	PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
	  PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:	many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
	  others use this interface
--------V-P03B003BF--------------------------
PORT 03B0-03BF - MDA  (Monochrome Display Adapter based on 6845)

03B0  -W  same as 03B4
03B1  RW  same as 03B5
03B2  -W  same as 03B4
03B3  RW  same as 03B5
03B4  -W  MDA CRT index register	 (MDA/mono EGA/mono VGA)
		selects which register (0-11h) is to be accessed through 03B5h
		Note: this port is read/write on some VGAs
		bit7-6: (VGA) reserved (0)
		bit5  : (VGA) reserved for testing (0)
		bit4-0: selects which register is to be accessed through 03B5h
03B5  RW  MDA CRT data register	 (MDA/mono EGA/mono VGA) (see #P0654,#P0708)
		selected by PORT 03B4h. registers 0C-0F may be read
		Color adapters are at 3D4/3D5, but are mentioned here for
		  better overview.
		There are differences in names and some bits functionality
		  on EGA, VGA in their native modes, but clones in their
		  emulation modes emulate the original 6845 at bit level. The
		  default values are for MDA, HGC, CGA only, if not otherwise
		  mentioned.
03B6  -W  same as 03B4h
03B7  RW  same as 03B5h
03B8  rW  MDA mode control register (see #P0655)
03B9  ?W  reserved for color select register on color adapter
03B9  -W  MDA/HGC: set lightpen flipflop (value written is ignored)
		cannot be found on native mono EGA, mono VGA (without
		  translation ROM)
03BA  R-  CRT status register (see #P0656)
	    (EGA/VGA) input status 1 register
03BA  -W  (mono EGA/mono VGA) feature control register
	    (see PORT 03DAh-W for details; VGA, see PORT 03CAh-R)
03BB  -W  light pen strobe reset (on any value)

(Table P0654)
Values for mono video adapter CRT data register index:
				  defaults:    MDA/HGC	HGC   CGA   CGA	  CGA
						 text  graph text1 text2 graph
						   7  720x348  1     3	  5,6
 00h	horizontal total			  61h	35h   38h   71h	  38h
	      ET4000: in VGA mode scanlines-5
		      in EGA mode scanlines-2
 01h	horizontal displayed			  50h	2Dh   28h   50h	  28h
	      horizontal display end-1 (EGA,VGA)
 02h	horizontal sync position		  52h	2Eh   2Dh 5Ah/5Ch 2Dh
 03h	sync pulse width			  0Fh 07h/0Fh 0Ah   0Ah	  0Ah
	       bit7-4 vsync, bit3-0 hsync
	      end horizontal blanking (EGA,VGA)
	       VGA    : bit7=1	  : enable read access to regs
				    10h, 11h (otherwise VGA clones
				    may show lightpen values)
	       EGA,VGA: bit6-5=0-3: display enable skew control
			bit4-0	  : end blanking
 04h	vertical total (vcycle-1)		  19h	5Bh   1Fh   1Fh	  7Fh
	       bit7 only used on MCGA
	      start horizontal retrace (EGA, VGA)
	      Genoa SuperEGA only???:
	       bit7  : start at odd memory address
	       bit6-5: horizontal sync skew
	       bit4-0: start retrace+ retrace width
 05h	vertical total adjust			  06h	02h   06h   06h	  06h
	       bit7-5 only used on MCGA
	      end horizontal retrace (EGA, VGA)
	       bit7  : (EGA) start at odd memory address
		       (VGA) bit5 of end horizontal retrace
	       bit6-5: horizontal sync skew
	       bit4-0: end horizontal retrace
 06h	vertical displayed			  19h	57h   19h   19h	  64h
	       bit7 only used on MCGA
	      (EGA) vertical total-1
	      (VGA) vertical total-2
 07h	vertical sync pulse width-1		  19h	57h   1Ch   1Ch 70h/66h
	       bit7  only used on MCGA
	      controller overflow (EGA,VGA)
	       bit7: (VGA) bit9 of start vertical retrace (10h)
	       bit6: (VGA) bit9 of vertical display end (12h)
	       bit5: (VGA) bit9 of vertical total (06h)
		     (EGA) bit5 of cursor-position (0Ah)
	       bit4: bit8 of line compare (18h)
	       bit3: bit8 of start vertical blanking (15h)
	       bit2: bit8 of vertical retrace start (10h)
	       bit1: bit8 of vertical display end (12h)
	       bit0: bit8 of vertical total (06h)
 08h	interlace mode (not MCGA)		  02h	02h   02h   02h	  02h
	       bit7-2: reserved
	       bit1  : delay
	       bit0=1: interlace on
	      preset row scan (EGA, VGA)
	       bit7  : reserved
	       bit6-5: (VGA) byte panning (low-order bits of display start addr
		  in odd/even and quad modes
	       bit4-0: start row scan after retrace
 09h	maximum scan lines			  0Dh	03h   07h   07h	  01h
	       bit7  : (VGA) double scan active
	       bit6  : (VGA) bit9 of line compare (18h)
	       bit5  : (VGA) bit9 of start vertical blanking (15h)
	       bit4-0: maximum scan line 00..31 (height-1)
 0Ah	cursor start				  0Bh	00h   06h   06h 06h/00h
	       bit7  : reserved
	       bit6-5: original 6845: cursor on/off, blink interval
		       (not on all adapters, as original MDA, CGA have
		       extra circuitrity to avoid this!!)
	       bit6-5: native EGA: not used
	       bit6  : (VGA) not used
	       bit5=0: (VGA) cursor on
	       bit4-0: first cursor scanline
 0Bh	cursor end				  0Ch	00h   07h   07h 07h/00h
	       bit7  : reserved
	       bit6-5: EGA, VGA: cursor skew control
	       bit4-0: end cursor row
 0Ch RW	start address high			  00h	00h   00h   00h	  00h
	       bit7-6 not used by original 6845 (MDA,HGC,CGA)
 0Dh RW	start address low			  00h	00h   00h   00h	  00h
 0Eh RW	cursor location high			  00h	00h   00h   00h	  00h
	       bit7-4 not used by original 6845 (MDA,HGC,CGA)
	       bit5-4 reserved on MCGA
 0Fh RW cursor location low			  00h	00h   00h   00h	  00h
 10h R-	light pen high (MDA/CGA/EGA only, some HGC, few VGA
	       clones in emulation, not with ET4000)
 10h R- MCGA at 3D5h only: mode control status register (see #P0711)
 11h R- light pen low (MDA/CGA/EGA only, some HGC, few VGA
	       clones in emulation, not with ET4000)
 14h -W HGC+,InColor: xMode register
 15h -W HGC+,InColor: underscore register
 16h -W HGC+,InColor: overstrike register
 17h -W	InColor: exception register
 18h -W	InColor: plane mask register
 19h -W	InColor: read/write control register
 1Ah -W	InColor: read/write color register
 1Bh -W	InColor: Latch Protect register
 1Ch RW	InColor: palette register
Notes:	registers 10h and 11h have varying uses on VGA (see #P0708) and
	  MCGA (see #P0710)
	MDA, HGC, CGA: 6845 registers 00h-0Dh are write only, 0Eh, 0Fh
	       are r/w, and 10h-11h are read only.
	       The alternative initial defaults may be used
	       sometimes on modern adapters.
	HGC+(RamFont): as with HGC, but 3 additional registers for font control
	emulations   : more registers may be r/w, but most often it's the
	       same as with native 6845.
	MCGA (CGA+)  : Though this is a mixture of CGA and VGA, most
	       registers are same as with CGA, but with some
	       enhancements and incompatibilities to EGA, VGA.
	native EGA   : registers 00h-0Bh are write only, 0Ch-0Fh are
	       r/w, 10h-11h are read/write, 12h-18h are write
	       only. More regs may be r/w on enhanced clones.
	GenoaSuperEGA: adapter with chips SEQCRT GN006001 and GRAT
	       GN006002, e.g. c't Super-EGA adapter. Is EGA
	       clone with up to 800x600 and full 6845 emulation.
	native VGA   : all registers 00-18h are r/w, but 00h-07h are
	       write-locked if bit7 in 11h is set.
	ET4000	     : same as VGA, but with additional r/w registers
	       32h-37h, protected by 'key' except 33h, 35h
	       (see 3BFh for details). 35h is protected by
	       bit7 in 11h. The 'key' must be issued at least
	       after each power on or synchronous reset.
SeeAlso: #P0708,#P0710,#P0655,#P0656,#P0710

Bitfields for mono video adapter mode control register:
Bit(s)	Description	(Table P0655)
 7 not used by MDA, page number on HGC
 6	not used
 6  R-O	(mono ET4000 only) report status of bit 1 (enable 2nd page) of
	  Hercules compatibility register (PORT 03BFh)
 5	enable blink (0 = intense background, 1 = blink)
 4	not used
 3	video enable
 2	not used
 1	(MDA) not used
	(HGC) graphics enable
	the 6845 has to be reprogrammed completely, if this bit is
	  changed, otherwise the TTL-monitor may be damaged by wrong
	  sync impulses!
 0	high resolution mode (always set on MDA)
---mono ET4000 only, W-O ---
 7-0	=A0h: second part of 'key', see Hercules compatibility register
	  (PORT 03BFh) for details
Note:	this port might be completely or partially readable on very few MDA,
	  HGC clones or emulations (e.g. Genoa SuperEGA), but not with the
	  majority of original and clone chips.	 It cannot be found on
	  native mono EGA, mono VGA, but on most clones, where it is usually
	  R/W.
SeeAlso: #P0654,#P0656

Bitfields for mono video adapter CRT status register:
Bit(s)	Description	(Table P0656)
 7	HGC: vertical sync pulse in progress
 6-4	adapter identification
	(MSD says) if bit 7 changes within 8000h reads then
	    =000 adapter is Hercules or compatible
	    =001 adapter is Hercules+
	    =101 adapter is Hercules InColor
	    else: adapter is unknown
 6-4	=111 on MDA and some HGC clones
 5-4	(mono EGA, mono ET4000) diagnose video display feedback
	select from color plane enable
 3	(MDA,HGC) pixel stream (0=currently black, 1=currently white)
	(mono EGA, mono VGA) vertical retrace in progress
 2-1	(MDA) reserved
 2	(HGC, mono EGA) lightpen flipflop set
	(mono ET4000) reserved (0)
 1	(HGC) lightpen input stream (if set, current value to get from
	  PORT 03B5h registers 10h-11h)
	(mono ET4000) reserved (0)
 0	horizontal drive enabled
SeeAlso: #P0654,#P0655

Bitfields for EGA,VGA mode control register:
Bit(s)	Description	(Table P0657)
 7	0=CRTC reset and stop, 1=resume reset
 6	0=word-mode, 1=byte-mode (VGA: see 14h, bit6)
 5	0=14bit, 1=16bit address wrap
 4	(native VGA only) reserved (0)
 4	(EGA and most VGA clones) output control
	0: video driver active
	1: video driver not active
 3	linear address counter clock (0 = standard, 1 = clock/2)
	(VGA: see register 14h, bit 5)
 2	horizontal retrace clock (0 = standard, 1 = clock/2)
 1	row scan counter
	0: address bit 14 = scan bit 1
	1: address bit 14 not altered
 0	6845 compatibility mode
	0: address bit 13 = scan bit 0 (as with 6845)
	1: address bit 13 not altered
SeeAlso: #P0654
--------P-P03BC03BF--------------------------
PORT 03BC-03BF - PARALLEL PRINTER PORT (MDA's LPT1)
Range:	PORT 0278h, PORT 0378h, or PORT 03BCh
SeeAlso: MEM 0040h:0008h

03BC  -W  data port
03BC  R-  bidirectional port: input from connector
	  unidirectional port: last value written to port
03BD  R-  status port (see #P0658)
03BE  RW  control port (see #P0659)

Bitfields for parallel interface status port:
Bit(s)	Description	(Table P0658)
 7	busy
 6	NOT acknowledge (approx. 5us low pulse)
 5	out of paper
 4	printer is selected
 3	*no* error
 2	IRQ has *not* occurred
	(PS/2) printer returned -ACK
 1-0	reserved
Note:	if bit 2 is clear (i.e. an interrupt has occurred), it is set again on
	  reading the status register
SeeAlso: #P0659

Bitfields for parallel interface control port:
Bit(s)	Description	(Table P0659)
 7-6	reserved
 7	(see PORT 037Bh bit 7)
 5	(PS/2) enable bidirectional port
	(also requires enabling via PORT 0102h)
 4	enable IRQ (via -ACK)
 3	select printer (SLCT IN line)
 2	=0 initialize printer (-RESET line)
 1	automatic line feed
 0	strobe (must be set for minimum of 5 microseconds)
SeeAlso: #P0658
--------V-P03BF------------------------------
PORT 03BF - Hercules configuration switch register
Note:	can also be found on EGA and VGA clones in Hercules emulation

03BF  -W  configuration switch register (see #P0660)
03BF  -W  (ET4000) Hercules compatibility register (see #P0661)
03BF  RW  (Genoa SuperEGA) miscellaneous register
	Note: only available in MDA, HGC, and CGA emulation; should be
	  compatible with Hercules configuration register, but may contain
	  additional features

Bitfields for Hercules configuration switch register:
Bit(s)	Description	(Table P0660)
 7-2	reserved
 1	=0  disables upper 32K of graphics mode buffer
	=1  enables upper 32K of graphics mode buffer
 0	=0  prevents graphics mode
	=1  allows graphics mode
SeeAlso: #P0661

Bitfields for ET4000 compatibility register:
Bit(s)	Description	(Table P0661)
 1	=0 disables upper 32K of graphics mode buffer
	=1 enables upper 32K of graphics mode buffer
 0	reserved (not needed for HGC graphics)
 7-0	=03h: first part of 'key' for access to some extra
	     ET4000 regs. To issue the 'key', the following
	     code must be executed:
	      MOV DX, 3BFh
	      MOV AL, 3
	      OUT DX, AL
	      MOV DX, 3D8h  (3B8h in mono mode)
	      MOV AL, 0A0h
	      OUT DX, AL
SeeAlso: #P0660
--------V-P03C003C1--------------------------
PORT 03C0-03C1 - EGA/VGA - ATTRIBUTE CONTROLLER
Range:	PORT 03C0h or PORT 02C0h (alternate EGA)
SeeAlso: PORT 03C2h,PORT 03D0h,#P0718

03C0  rW  ATC index/data register
		Every write access to this register will toggle an internal
		  index/data selection flipflop, so that consecutive writes to
		  index & data is possible through this port. To get a defined
		  start condition, each read access to the input status register
		  #1 (3BAh in mono / 3DAh in color) resets the flipflop to load
		  index. If values are changed during the vertical retrace
		  period only no flicker will occur.

		index register (flipflop reset to 'index'): (default 20h)
		  bit7-6: reserved
		  bit5	: 0=CPU access (screen dark),
			  1=video access to registers
		  bit4-0: index in ATC (0..31)

		indexed registers in ATC (flipflop set to 'data'): (see #P0662)
03C1  R-  (VGA)	ATC index/data read register

(Table P0662)
Values for EGA/VGA indexed registers in ATC:
 00h-0Fh 16 palette registers (see #P0663)
 10h	mode control register (see #P0664)
 11h	(EGA) overscan color register (see #P0665) (default: 00h)
 11h	(VGA) overscan color register (see #P0666) (default: 00h)
 12h	color enable register (see #P0667)
 13h	horizontal pixel panning register
	bit7-4: reserved
	bit3-0: horizontal pixel panning
 14h	(VGA) color select register (default: 00h)
	bit7-4: reserved
	bit3  : s-color 7
	bit2  : s-color 6
	bit1  : s-color 5 (only with 16 pages   16 regs)
	bit0  : s-color 4 (only with 16 pages   16 regs)
 16h	ET3000, ET4000 only: ATC miscellanenous
	(at least on ET4000 'key' protected)
	This register is also supported by ET3000, but the
	  description is proved for ET4000 only.
	bit7  : bypass the internal palette
		(e.g. for HiColor modes with Sierra RAMDACs)
	bit6  : reserved
	bit5-4: select high resolution / color mode
	bit3-0: reserved
SeeAlso: #P0670,#P0700

Bitfields for EGA/VGA indexed ATC palette register:
Bit(s)	Description	(Table P0663)
 7-6	reserved
 5	secondary red video
 4	secondary green/intensity video
 3	secondary blue/mono video
 2	primary red video
 1	primary green video
 0	primary blue video
SeeAlso: #P0662

Bitfields for EGA/VGA ATC mode control register:
Bit(s)	Description	(Table P0664)
 7	(VGA) SB/SG select (0=4 pages of 64 regs, 1=16 pages of 16 regs)
 6	(VGA) PELCLK/2 (0=4bit color, 1=8bit color)
 5	(VGA) enable pixel panning (0=all, 1=up to line compare register value)
 4	reserved
 3	background intensity (0=16 colors, 1=blink)
 2	line graphics enable (0=background, 1=line 8=9)
 1	1=mono, 0=color select
 0	1=graphics, 0=text select
SeeAlso: #P0662

Bitfields for EGA overscan color register:
Bit(s)	Description	(Table P0665)
 7-6	reserved
 5	secondary red (SR)
 4	secondary green (SR) / intensity
 3	secondary blue (SB)
 2	primary red (PR)
 1	primary green (PG)
 0	primary blue (PB)
SeeAlso: #P0662,#P0666

Bitfields for VGA overscan color register:
Bit(s)	Description	(Table P0666)
 7	secondary intensity border color (SI)
 6	secondary red (SR)
 5	secondary green (SG)
 4	secondary blue (SB)
 3	intensity border color (PI)
 2	primary red (PR)
 1	primary green (PG)
 0	primary blue (PB)
SeeAlso: #P0662,#P0665

Bitfields for EGA/VGA color enable register:
Bit(s)	Description	(Table P0667)
 7-6	reserved
 5-4	diagnose / video status select
	EGA:		VGA, ET4000:
	00b = PR/PB	   PR/PB
	01b = SB/PG	   SG/SB
	10b = SR/SG	   PI/PG
	11b = reserved	   SI/SR
 3	enable plane 3
 2	enable plane 2
 1	enable plane 1
 0	enable plane 0
SeeAlso: #P0662
----------P03C003C7--------------------------
PORT 03C0-03C7 - Sunshine EW-901, EW-901A, EW-904, EW-904A
Desc:	EPROM writer card for EPROMs up to 27512

03C0-03C3	adresses of the 8255 on the EW-90x
--------V-P03C203CF--------------------------
PORT 03C2-03CF - EGA/VGA - MISCELLANEOUS REGISTERS
Range:	PORT 03C2h or PORT 02C2h (alternate EGA)
SeeAlso: PORT 03C0h,PORT 03C4h,PORT 03C6h,PORT 03D0h

03C2  R-  input status 0 register (see #P0668)
03C2  -W  miscellaneous output register (see #P0669)
03C3  RW  (VGA)	video subsystem enable (see also PORT 46E8h)
		for IBM, motherboard VGA only
			 bit7-4=0: reserved
			 bit3	 : select video subsystem (address 46E8h)
			 bit2-1	 : reserved
			 bit0	 : select video subsystem (address 03C3h)

Bitfields for EGA/VGA input status 0 register:
Bit(s)	Description	(Table P0668)
 7	(VGA) vertical retrace interrupt is pending
	(EGA) =0 vertical retrace in progress
 6-5	(VGA) reserved (0)
 6	(EGA and ET4000) feature control 1 (pin17)
 5	(EGA and ET4000) feature control 0 (pin19)
 4	(VGA) monitor sense signal is asserted
 4	(EGA, Genoa SuperEGA) DIP switch sense
	0=closed, 1=open/switches readable
 3-0	reserved (0)

Bitfields for EGA/VGA miscellaneous output register:
Bit(s)	Description	(Table P0669)
---Genoa SuperEGA in all emulation modes---
 7-6: vertical resolution
	00 (EGA) 200 lines
	01 (VGA) 400 lines
	10 (EGA/VGA) 350 lines
	11 (VGA) 480 lines
------
 7	vertical sync polarity (0=positive, 1=negative)
 6	horizontal sync polarity (0=positive, 1=negative)
 5	odd/even pagebit (=1 select second 64K memory page)
 4	EGA: 0=video driver on,
	     1=video driver off (feature connector used)
 3-2	pixelclock
	00 14/25.175 MHz (EGA/VGA)
	01 16/28.322 Mhz (EGA/VGA)
	10 (EGA/VGA) external clock (EGA)
	10 (Genoa SuperEGA) 39Mhz
	11 (EGA/VGA) reserved
	11 (Genoa SuperEGA) 26.824Mhz
	11 (S3 Trio32/Trio64) enable clock programming via sequencer registers
		  12h and 13h
 1	enable CPU RAM access
 0	CRTC port address
	0=3B4h mono
	1=3D4h color
	   (color EGA: enable feature control at 3DAh,status reg 1 at 3D2h)
----------P03C403C5--------------------------
PORT 03C4-03C5 - EGA/VGA - SEQUENCER REGISTERS
Range:	PORT 03C4h or PORT 02C4h (alternate EGA)
SeeAlso: PORT 03C0h,PORT 03C2h,PORT 03C4h"Cirrus",PORT 03C4h"S3"
SeeAlso: PORT 03C4h"Tseng",PORT 03C6h,PORT 03D0h

03C4  -W  EGA	TS index register
		bit7-3 : reserved (VGA only)
		bit2-0 : current TS index
03C4  RW  VGA	sequencer register index (see #P0670)
03C5  -W  EGA	TS data register
03C5  RW  VGA	sequencer register data

(Table P0670)
Values for EGA/VGA indexed TS (sequencer) registers:
 00h	reset register
	bit7-2 : reserved
	bit1 =0: synchronous reset (EGA/VGA)
	bit0 =0: asynchronous reset (EGA, ET4000)
		 synchronous reset, also (VGA)
 01h	clocking mode register / TS mode (see #P0671)
 02h	map mask register (see #P0672)
 03h	character map select register / font select (see #P0673)
 04h	memory mode register (see #P0674)
 07h	(undoc VGA) reset horizontal character counter
	any write to this register holds horizontal character counter at 00h
	  until any other sequencer register is written
Note:	register 07h is documented in the C&T Wingine documentation
SeeAlso: #P0675,#P0696,#P0685

Bitfields for EGA/VGA sequencer clocking mode register:
Bit(s)	Description	(Table P0671)
 7-6	reserved
 5	(VGA) =1: screen refresh off
 4	(VGA) shift load (0=4x8, 1=1x32)
 3	internal character clock (0=normal, 1=dotclock/2)
 2	serial shift video load (0=4x8, 1=2x16)
 1	(EGA) CRTC bandwidth (0=4/5, 1=2/5)
 0	dot clocks per character (0=9, 1=8) (ET4000: see 06h)
SeeAlso: #P0670

Bitfields for EGA/VGA sequencer map mask register:
Bit(s)	Description	(Table P0672)
 7-4	reserved
 4	Genoa SuperEGA only: plane4 ???
 3	write enable display memory plane 3
 2	write enable display memory plane 2
 1	write enable display memory plane 1
 0	write enable display memory plane 0
SeeAlso: #P0670

Bitfields for EGA/VGA sequencer character map select register:
Bit(s)	Description	(Table P0673)
 7-6	reserved
 5	(VGA) bit3 for second text-font
 4	(VGA) bit3 for first text-font
 3-2	second text-font (attr bit3=1)
 1-0	first text-font (attr bit3=0)
	offset in font memory (4-7: VGA only)
	   0 00b =  0KB
	   0 01b = 16KB
	   0 10b = 32KB
	   0 11b = 48KB
	   1 00b =  8KB
	   1 01b = 24KB
	   1 10b = 40KB
	   1 11b = 56KB
SeeAlso: #P0670

Bitfields for EGA/VGA sequencer memory mode register:
Bit(s)	Description	(Table P0674)
 7-4	reserved
 3	=1 (VGA) enable chain 4 linear graphics mode
	(when set, low two bits of CPU address select the plane)
 2	addressing mode
	0 odd/even mode (even addresses access planes 0/2, odd planes 1/3)
	1 sequential mode
 1	=1 extended memory (0=64KB, 1=more)
 0	(EGA) 1=textmode, 0=graphics mode
SeeAlso: #P0670
----------P03C403C5--------------------------
PORT 03C4-03C5 - Cirrus Logic GRAPHICS - EXTENDED SEQUENCER REGISTERS
SeeAlso: PORT 03C4h"EGA",PORT 03C4h"S3",PORT 03C4h"Tseng"

03C4  RW  sequencer register index (see #P0696)
03C5  RW  sequencer register data

(Table P0675)
Values for Cirrus CL-GD7556 extended sequencer registers:
 00h-04h same as EGA/VGA (see #P0670) 
 06h	"SR6" key register -- enable access to extension registers
	set to xxx1x010 to unlock extended sequencer and CRTC registers
 07h	"SR7" extended sequencer mode (see #P0676)
 08h	"SR8" DDC2B control (see #P0677)
 09h	"SR9" scratch pad #0
 0Ah	"SRA" scratch pad #1
 0Bh	"SRB" VCLK0 numerator  !!!gd7556hrm.pdf p.239
 0Ch	"SRC" VCLK1 numerator
 0Dh	"SRD" VCLK2 numerator
 0Eh	"SRE" VCLK3 numerator
 0Fh	"SRF" display memory control (see #P0678)
 10h	"SR10" hardware cursor/icon coarse horizontal position
 11h	"SR11" hardware cursor/icon coarse vertical position
 12h	"SR12" hardware cursor attributes
 13h	"SR13" hardware cursor pattern address
 14h	"SR14" scratch pad #2
 15h	"SR15" scratch pad #3
 17h	"SR17" BitBLT memory map I/O address
 18h	"SR18" signature generator control
 19h	"SR19" signature generator result (low)
 1Ah	"SR1A" signature generator result (high)
 1Bh	"SR1B" VLK0 denominator/post scaler
 1Ch	"SR1C" VLK1 denominator/post scaler
 1Dh	"SR1D" VLK2 denominator/post scaler
 1Eh	"SR1E" VLK3 denominator/post scaler
 1Fh	"SR1F" MCLK frequency / VCLK source select
 20h	"SR20" miscellaneous control 2
 21h	"SR21" test bus control
 22h	"SR22" hardware configuration read 1
 23h	"SR23" software configuration 1
 24h	"SR24" flat panel type switches enable
 25h	"SR25" FasText(tm) mode control
 26h	"SR26" shader signature (low)
 27h	"SR27" shader signature (high)
 28h	"SR28" scratch pad #4
 29h	"SR29" scratch pad #5
 2Ah	"SR2A" hardware icon #0 control
 2Bh	"SR2B" hardware icon #1 control
 2Ch	"SR2C" hardware icon #2 control / byte-swap enable
 2Dh	"SR2D" hardware icon #3 control / cursor memory access
 2Eh	"SR2E" hardware cursor horizontal position extension
 2Fh	"SR2F" half-frame accel. FIFO threshold for surrounding graphics
 32h	"SR32" half-frame accel. FIFO threshold in video window
 33h	"SR33" spare register
 34h	"SR34" Host CPU cycle stop control
Note:	the scratch pad registers are reserved for use by the VGA BIOS
SeeAlso: #P0670,#P0685,#P0696

Bitfields for Cirrus CL-GD7556 extended sequencer mode register:
Bit(s)	Description	(Table P0676)
 7-4	display memory segment
 3-1	CRT Controller character clock divisor
 0	select high-resolution packed-pixel mode
!!!gd7556hrm.pdf p.234
SeeAlso: #P0675

Bitfields for Cirrus CL-GD7556 DDC2B Control register:
Bit(s)	Description	(Table P0677)
 7	DDCD output status (read-only)
 6-3	reserved
 2	DDCC output status (read-only)
 1	DDCD (I2C SDA) output control
 0	DDCC (I2C SCL) output control
Notes:	bits 1 and 0 are used to drive the I2C bus used for DDC communications;
	  bits 7 and 2 are used to read back the current state of the bus lines
	SR24 bit 7 must be cleared to enable access to the bus
SeeAlso: #P0675,#M0079,I2C A0h"DDC"

Bitfields for Cirrus CL-GD7556 Display Memory Control register:
Bit(s)	Description	(Table P0678)
 7	bank select for display memory
 6	!!!gd7556hrm.pdf p.241
 5	reserved
 4-3	display memory data width
 2	RAS# cycle select for display memory
 1	display memory configuration symmetry
 0	multiple-CAS# / multiple-WE# select for display memory
SeeAlso: #P0823
----------P03C403C5--------------------------
PORT 03C4-03C5 - NVIDIA - EXTENDED SEQUENCER REGISTERS
SeeAlso: PORT 03C4h"EGA",PORT 03C4h"S3",PORT 03C4h"Tseng"

03C4  RW  sequencer register index (see #P0679)
03C5  RW  sequencer register data

(Table P0679)
Values for NVIDIA NV3/RIVA128 extended sequencer registers:
 06h	key register (enable access to extended registers when set to 57h,
	  disable access when set to any other value)
 19h	extended start address and offset
	bits 7-5: offset bits 10-8
	bits 4-0: address bits 20-16
 1Ah	flags (see #P0680)
 1Bh	refresh FIFO control (see #P0681)
 20h	FIFO watermark (see #P0682)
 25h	miscellaneous extension bits (see #P0683)
 28h	framebuffer format
 2Dh	extended horizontal bits (see #P0684)
 30h	graphics cursor control 0
 31h	graphics cursor control 1
 ???

Bitfields for NVIDIA NV3 flags:
Bit(s)	Description	(Table P0680)
 !!!nv3ref.h
SeeAlso: #P0679

Bitfields for NVIDIA NV3 refresh FIFO control:
Bit(s)	Description	(Table P0681)
 7	underflow warning
 2-0	burst length
	000 eight
	001 32
	010 64
	011 128
	100 256
SeeAlso: #P0679,#P0682

Bitfields for NVIDIA NV3 FIFO watermark:
Bit(s)	Description	(Table P0682)
 7	reset FIFO
 5-0	watermark, in eight-byte units (refresh FIFO will start refilling
	  when occupancy falls below twice this value)
SeeAlso: #P0679,#P0681

Bitfields for NVIDIA NV3 miscellaneous extension bits:
Bit(s)	Description	(Table P0683)
 5	offset bit 11
 4	horizontal blanking end, bit 6
 3	vertical blanking start, bit 10
 2	vertical retrace start, bit 10
 1	vertical display end, bit 10
 0	vertical total, bit 10
SeeAlso: #P0679,#P0684

Bitfields for NVIDIA NV3 extended horizontal bits:
Bit(s)	Description	(Table P0684)
 4	"inter_half_start" bit 8
 3	horizontal retrace start, bit 8
 2	horizontal blanking start, bit 8
 1	display end, bit 8
 0	display total, bit 8
SeeAlso: #P0679,#P0683
----------P03C403C5--------------------------
PORT 03C4-03C5 - S3 GRAPHICS - EXTENDED SEQUENCER REGISTERS
SeeAlso: PORT 03C4h"EGA",PORT 03C4h"Cirrus",PORT 03C4h"Tseng",PORT 03C4"NVIDIA"

03C4  RW  sequencer register index (see #P0685)
03C5  RW  sequencer register data

(Table P0685)
Values for S3 extended sequencer registers:
 00h-04h same as EGA/VGA (see #P0670) 
 08h	S3 864/964/765 (Trio64V): key register -- enable access to S3 extended
	  registers when set to x6h
---S3 Trio32/Trio64/Trio64V+ ---
 09h	"SR9" MMIO-Only
	bit 7: disable port I/O when memory-mapped I/O is enabled
	bits 6-0: reserved
	bit 1: ??? (set by Stealth64 Video 2001)
 0Ah	"SRA" external bus request control register (see #P0686)
 0Bh	"SRB" miscellaneous extended sequencer register (see #P0687)
 0Dh	"SRD" VSYNC/HSYNC control (see #P0689)
 10h	"SR10" MCLK value (low) (see #P0690)
 11h	"SR11" MCLK value (high) (see #P0691)
 12h	"SR12" DCLK value (low) (see #P0690)
 13h	"SR13" DCLK value (high) (see #P0691)
 14h	"SR14" CLKSYN control 1 (see #P0692)
 15h	"SR15" CLKSYN control 2 (see #P0693)
 16h	"SR16" CLKSYN Test (high) (reserved for testing of clock synth)
 17h	"SR17" CLKSYN Test (low) (reserved for testing of clock synth)
 18h	"SR18" RAMDAC/CLKSYN Control (see #P0694)
---S3 Trio64V+ ---
 1Ch	"SR1C" signal select (see #P0695)
SeeAlso: #P0670,#P0675,#P0696

Bitfields for S3 Trio32/64/64V+ "SRA" external bus request control register:
Bit(s)	Description	(Table P0686)
 7	fast CPU writes
	when set and MCLK is less than 57 MHz, CPU writes take 2 MCLKs instead
	  of 3 MCLKs (for MCLKs of 55-57 MHz, SR15 bit 7 should also be set)
 6	(Trio64) Pin50 function select
	=0 (CR36 bit 2=1) Pin50 outputs a second -OE0 signal
	=1 (CR36 bit 2=1) Pin50 outputs -RAS1
 5	=0 tri-state pixel-data lines (reduces power consumption)
 4-0	maximum 2*MCLKs that secondary memory controllers are granted access to
	  Trio's memory bus
Note:	bit 6 must be set for 4M fast page-mode memory; it has no effect if
	  EDO memory is selected via CR36 bit 2
SeeAlso: #P0685

Bitfields for S3 Trio32/64/64V+ "SRB" misc extended sequencer register:
Bit(s)	Description	(Table P0687)
 7-4	alternate color mode (for feature connector input) (see #P0688)
 3	(Trio32 only) enable packed 24 bpp (mode 12); also requires CR67 bits
		  7-4=0000
 2	reserved
 1	VAFC clocking
	=0 latch pixel data from pass-through feature connector on VCLK
	=1 latch pixel data from VAFC on VCLKI
 0	dot clock select (testing only)
	=0 use internal dot clock
	=1 use VCLKI
SeeAlso: #P0685,#P0751

(Table P0688)
Values for S3 Trio32/Trio64 color mode:
0000	mode 0 = 8-bit, 1 pixel/VCLK
0001	mode 8 = 8-bit, 2 pixels/VCLK
0011	mode 9 = 15-bit, 1 pixel/VCLK
0101	mode 10 = 16-bit, 1 pixel/VCLK
0111	mode 12 = 640x480x24-bit (packed), 1 pixel/3 DCLKs (Trio32 only)
1101	mode 13 = 24-bit, 1 pixel/VCLK
else	reserved
Note:	mode 8 also requires SR18 bit 7=1 and either SR15 bit 4=1 or
	  SR15 bit 6=1
SeeAlso: #P0687,#P0751

Bitfields for S3 "SRD" Trio32/Trio64 VSYNC/HSYNC control:
Bit(s)	Description	(Table P0689)
 7-6	vertical sync control
	00 normal operation
	01 force to 0
	10 force to 1
	11 reserved
 5-0	horizontal sync control (settings as for vsync)
 3-1	reserved
 1	(Trio64V+) feature connector type
	=0 Trio64-compatible
	=1 new LPB type
 0	enable feature connector
Note:	bits 7-4 are used to select the DPMS power mode as follows:
	    0000 On
	    0001 Standby
	    0100 Suspend
	    0101 Off
SeeAlso: #P0685

Bitfields for S3 Trio32/Trio64 "SR10"/"SR12" MCLK/DCLK value (low):
Bit(s)	Description	(Table P0690)
 7	reserved
 6-5	PLL R value
 4-0	PLL N-divider value
SeeAlso: #P0691,#P0685

Bitfields for S3 Trio32/Trio64 "SR11"/"SR13" MCLK/DCLK value (high):
Bit(s)	Description	(Table P0691)
 7	reserved
 6-0	PLL M-divider value
SeeAlso: #P0690,#P0685

Bitfields for S3 Trio32/Trio64 "SR14" CLKSYN control 1:
Bit(s)	Description	(Table P0692)
 7	select external DCLK (testing only; also requires external strapping)
 6	select external MCLK (testing only)
 5	select Pin146 function
	=0 use as -STRD
	=1 tri-state output; use as input (required to enable bit 6)
 4	clear clock synthesizer counters (testing only)
 3	"M TEST" MCLK test
	=0 test DCLK
	=1 test MCLK
 2	enable clock synthesizer counters (testing only)
 1	power down MCLK PLL (testing only)
 0	power down DCLK PLL (testing only)
SeeAlso: #P0693,#P0685

Bitfields for S3 Trio32/Trio64 "SR15" CLKSYN control 2:
Bit(s)	Description	(Table P0693)
 7	enable fast memory writes (2 MCLKs instead of 3 MCLKs) by bypassing
	  VGA lienar addressing logic (requires SRA bit 7 set)
 6	invert DCLK
 5	load MCLK and DCLK immediately on transition from 1 to 0
 4	divide DCLK by 2
 3	VLCK direction
	=0 Pin148 always outputs internal VCLK
	=1 -EVCLK signal determines VLCK direction
 2	MCLK output (testing only)
	=0 Pin147 acts as STWR strobe
	=1 Pin147 outputs internal MCLK
 1	enable new DCLK frequency load (asynchronous)
 0	enable new MCLK frequency load
Notes:	bits 1 and 5 also require that PORT 03C2h bits 3-2=11
	bit 5 must never be left set; it should only be pulsed to cause the
	  MCLK/DCLK load
	bit 0 should be cleared after loading the new MCLK value to avoid
	  repeated loading
	either bit 4 or 6 must be set for clock-doubled RAMDAC operation
	  (see #P0686)
SeeAlso: #P0692,#P0694,#P0685

Bitfields for S3 Trio32/Trio64 "SR18" RAMDAC/CLKSYN control:
Bit(s)	Description	(Table P0694)
 7	enable clock-doubled mode (see also #393)
 6	fast LUT write cycle (1 DCLK instead of default 2 DCLKs)
 5	power down RAMDAC (RAMDAC memory is retained even when powered down)
 4	(testing only) place blue data on internal data bus
 3	(testing only) place green data on internal data bus
 2	(testing only) place red data on internal data bus
 1	(testing only) reset RAMDAC test counter
 0	(testing only) enable test counter
SeeAlso: #P0693

Bitfields for S3 Trio64V+ "SR1C" signal select:
Bit(s)	Description	(Table P0695)
 7-2	reserved
 1-0	signal select
	VL-Bus:
	    00 Pin151 is ENFEAT#, Pin153 is ROMCS# (default)
	    01 Pin151 is GPIOSTR#, Pin153 is ROMCS#
	    10 Pin151 is GOP0, Pin153 is ROMCS#
	    11 Pin151 is GOP0, Pin153 is GOP1
	PCI:
	    00 Pin151 is ENFEAT#, Pin190 is STWR#, Pin153 is ROMEN# (default)
	    01 Pin151 is reserved, Pin190 is STWR#, Pin153 is ROMEN#
	    1x Pin151 is GOP0, Pin190 is GOP1, Pin153 is ROMEN#
SeeAlso: #P0073
----------P03C403C5--------------------------
PORT 03C4-03C5 - Tseng Labs GRAPHICS - EXTENDED SEQUENCER REGISTERS
SeeAlso: PORT 03C4h"EGA",PORT 03C4h"Cirrus",PORT 03C4h"S3"

03C4  RW  sequencer register index (see #P0696)
03C5  RW  sequencer register data

(Table P0696)
Values for Tseng Labs extended sequencer registers:
 00h-04h same as EGA/VGA (see #P0670)
 06h	ET3000 only: Zoom control register
 06h	ET4000 only: TS state control (protected by 'key')
	bit7-3 : reserved
	bit2-1 : timing sequencer state bit2-1
		   (bit0 is bit0 TS mode register)
		   00 0b=  9 dots
		   00 1b=  8 dots
		   01 0b= 10	  (10-16 are ET4000 only)
		   01 1b= 11
		   10 0b= 12
		   11 1b= 16
	bit0	: reserved
 07h	ET3000/ET4000 only: TS auxiliary mode (see #P0697)
SeeAlso: #P0670,#P0675,#P0685

Bitfields for ET3000/ET4000 sequencer auxiliary mode:
Bit(s)	Description	(Table P0697)
 7	compatibility mode (1=VGA, 0=EGA)
 6	select MCLK/2 (with bit0=0)
 5	BIOS ROM address map 2
 4	reserved
 3	BIOS ROM address map 1
 2	reserved (1)
 1	select SCLK input from MCLK
 0	select MCLK/4 (with bit6=1)
 5+3	ROM address
	00 C0000-C3FFF
	01 disabled
	10 C0000-C5FFF, C6800-C7FFF
	11 C0000-C7FFF (default)
Notes:	at least on the ET4000, this register is protected by a 'key'
	this register is also supported by ET3000, but the above description
	  is based on the ET4000
SeeAlso: #P0670
--------V-P03C603C9--------------------------
PORT 03C6-03C9 - EGA/VGA/MCGA - DAC REGISTERS
Range:	PORT 03C6h or PORT 02C6h (alternate)
SeeAlso: PORT 03C0h,PORT 03C2h,PORT 03C4h,PORT 03CAh,PORT 03CEh"EGA",PORT 03D0h
SeeAlso: PORT 83C6h"Wingine"

03C6  RW  (VGA, MCGA) PEL mask register (default FFh)
		 VGA:	AND mask for color-register address.
		 MCGA:	Never change from the default FFh.
03C6  RW  HiColor ET4000 (Sierra RAMDACs e.g. SC11486, SC11481, SC11488):
		 Enable HiColor feature: beside other assignments,
		 consequtive read 3C6h 4 times and write magic value 80h to it.
03C7  -W  (VGA,MCGA,CEG-VGA) PEL address register (read mode)
		 Sets DAC in read mode and assign start of color register
		 index (0..255) for following read accesses to 3C9h.
		 Don't write to 3C9h while in read mode. Next access to
		 03C8h will stop pending mode immediatly.
03C7  -W  (CEG-Color VGA w/ Edsun Labs RAMDACs)
		 Enable and set Countinous Edge Graphics Mode:
		 Consecutive writely the following three key sequences in read
		 mode (!) to 3C9h register DEh : 'CEG', 'EDS', 'UNx' (x see
		 below). Current CEG mode can be read from palette register
		 BFh 'blue', write access to that register will disable CEG
		 features.
		 In CEG modes by combining old with new colors and dynamically
		 changing palette values, the effective colors displayable
		 are enhanced dramatically (in EDP modes up to virtually 32bit
		 truecolor) on standard 16/256 color VGA. Also, effective
		 resolution enhancement takes effect by anti-aliasing.
		 Necessary EDP escape sequences should be moved to image
		 border or single colored areas, if possible.

		 REP-mode: if pixel are doubled in current video mode
		 EDP-mode: pseudo-truecolor with Edsun dynamic palette
		 (see #P0698,#P0699)

		 Palette-color-register single-byte-format (each 3 times):
		  Mode A:		  Mode C:
		   bit7-4: mix code	   bit3	 : 0=color, 1=code
		   bit3-0: color code	   bit2-0: color / mix code
		  Mode B:		  Mode D:
		   bit7-5: mix code	   bit7-0: see mix code table
		   bit4	 : 0=new, 1=old	  Non-CEG modes:
		   bit3-0: color code	   bit7-0: as usual

		 In EDP modes, video-memory-palette-changing escape-sequences:
		  Mode A:     Mode B:	  Mode C:     Mode D:
		   7/escape    7/escape	   7/escape    0BFh
		   red	       red	   red7-4      red
		   green       green	   red3-0      green
		   blue	       blue	   green7-4    blue
		   address     address	   green3-0    address
					   blue7-4
					   blue3-0
					   address
03C7  R-  VGA	DAC state register
		bit7-2 reserved
		bit1-0: 00b write palette cycle (write mode)
			01h reserved
			10b reserved
			11b read palette cycle (read mode)
03C8  RW  (VGA,MCGA) PEL address register (write mode)
		 Sets DAC in write mode and assign start of color register
		 index (0..255) for following write accesses to 3C9h.
		 Don't read from 3C9h while in write mode. Next access to
		 03C8h will stop pending mode immediatly.
03C8  RW  (Genoa SuperEGA) SuperEGA control register (all emulation modes)
		  bit7-2: reserved
		  bit1	: 0=EGA mode, 1=backward compatibility mode
		  bit0	: not used
03C8  R?  (S3 Trio32/64) General Input Port (see #P0738)
03C9  RW  (VGA,MCGA) PEL data register
		 Three consequtive reads (in read mode) or writes (in write
		 mode) in the order: red, green, blue. The internal DAC index
		 is incremented each 3rd access.
		  bit7-6: HiColor VGA DACs only: color-value bit7-6
		  bit5-0:			 color-value bit5-0

(Table P0698)
Values for EDSUN CEG (Continuous Edge Graphics) modes::
 x:  mode:	 colors:  mix:	pixel depth:  effective colors:
 0 = disabled	   256	   -	     8		    256
 1 = A		    16	  16	     8		   1920
 2 = A+REP	    16	  16	  8 dblscn	   1920
 3 = A+EDP	    15	  16			truecolor
 4 = reserved	     -	   -	     -		     -
 5 = B		    16	   8	     8		    960
 6 = B+REP	    16	   8	  8 dblscn	    960
 7 = B+EDP	    15	   8			truecolor
 8 = reserved	     -	   -	     -		     -
 9 = C		     8	   8	     4		    224
 10 = C+REP	     8	   8	  4 dblscn	    224
 11 = C+EDP	     7	   8			truecolor
 12 = reserved	     -	   -	     -		     -
 13 = D		   223	  32	     8		 792096
 14 = D+REP	   223	  32	  8 dblscn	 792096
 15 = D+EDP	   223	  32			truecolor
SeeAlso: #P0699

(Table P0699)
Values for EDSUN CEG mixing codes:
 Mode A:	       |  Mode C:
 mix: new:	old:   |   mix: new:   old:   colorcode:
   0 = 32/32	0/32   |    0 =	  -	 -     0
   1 = 30/32	2/32   |    1 =	  -	 -     1
   2 = 28/32	4/32   |    2 =	  -	 -     2
   3 = 26/32	6/32   |    3 =	  -	 -     3
   4 = 24/32	8/32   |    4 =	  -	 -     4
   5 = 22/32   10/32   |    5 =	  -	 -     5
   6 = 20/32   12/32   |    6 =	  -	 -     6
   7 = 18/32   14/32   |    7 =	  -	 -     7/EDP
   8 = 16/32   16/32   |    8 = 30/32	2/32   -
   9 = 14/32   18/32   |    9 = 28/32	4/32   -
  10 = 12/32   20/32   |   10 = 26/32	6/32   -
  11 = 10/32   22/32   |   11 = 24/32	8/32   -
  12 =	8/32   24/32   |   12 = 22/32  10/32   -
  13 =	6/32   26/32   |   13 = 20/32  12/32   -
  14 =	4/32   28/32   |   14 = 18/32  14/32   -
  15 =	2/32   30/32   |   15 = 16/32  16/32   -
---Mode B:	       |  Mode D:
 mix: new:	old:   |   mix:	      new:   old:  description:
   0 = 30/32	2/32   |   00h..BEh =	-      -   normal color
   1 = 26/32	6/32   |   BFh	    =	-      -   EDP
   2 = 22/32   10/32   |   C0h	    = 32/32   0/32
   3 = 18/32   14/32   |   C1h	    = 31/32   1/32
   4 = 14/32   18/32   |   C2h	    = 30/32   2/32
   5 = 10/32   22/32   |   ...	    =  ...    ...
   6 =	6/32   26/32   |   DFh	    =  0/32  32/32
   7 =	2/32   30/32   |   E0h-FFh  =	-      -   normal color
SeeAlso: #P0698
--------V-P03CA03CD--------------------------
PORT 03CA-03CD - EGA/VGA/MCGA - GRAPHICS POSITION
Range:	PORT 03C0h or PORT 02C0h (alternate)
SeeAlso: PORT 03C0h,PORT 03C2h,PORT 03C4h,PORT 03C6h,PORT 03CEh"EGA",PORT 03D0h

03CA  -W  EGA	graphics 2 position register
03CA  R-  VGA	feature control register (see PORT 03BAh,PORT 03DAh-W)
03CB  RW  (ET4000/W32) GDC segment select register 2 ('key' protected?)
		The existence of this r/w register 0..255 is often
		 used to decide between ET4000 and ET4000/W32.
		 bit7-6: reserved, but existent
		 bit5-4: bits 5-4 of read segment pointer
		 bit3-2: reserved, but existent
		 bit1-0: bits 5-4 of write segment pointer
03CC  -W  EGA	graphics 1 position register
03CC  R-  VGA	miscellaneous output register (see PORT 03C2h-W,#P0669,#P0820)
03CD  RW  (ET3000, ET4000, ET4000/W32) GDC segment select ('key' protected)
		The existence of this r/w register is often used as
		detection of ET3000, ET4000 and ET4000/W32 chips.
		 bit7-4: read segment pointer for mapping to A0000h
		 bit3-0: write segment pointer for mapping to A0000h
--------V-P03CE03CF--------------------------
PORT 03CE-03CF - EGA/VGA/MCGA - GRAPHICS CONTROLLER REGISTERS
Range:	PORT 03CEh or PORT 02CEh (alternate EGA)
SeeAlso: PORT 03C0h,PORT 03C2h,PORT 03C4h,PORT 03C6h,PORT 03D0h
SeeAlso: PORT 03CEh"Chips&Technologies"

03CE  -W  EGA	GDC index register
03CE  RW  VGA	graphics address register / GDC index
		      bit7-4: reserved
		      bit3-0: index
03CF  -W  EGA	GDC data register (see #P0700)
03CF  RW  VGA	other graphics register (see #P0700)

(Table P0700)
Values for EGA/VGA indexed registers in GDC:
 00h	set/reset register (default 00h)
	functionality depending on write mode (register 05h) (see #P0704)
	bit7-4: reserved
	bit3  : 0=write 00h, 1=write FFh in plane 3
	bit2  : 0=write 00h, 1=write FFh in plane 2
	bit1  : 0=write 00h, 1=write FFh in plane 1
	bit0  : 0=write 00h, 1=write FFh in plane 0
 01h	enable set/reset register (default 00h) (see #P0701)
 02h	color compare register (default 00h) (see #P0702)
 03h	data rotate register (default 00h) (see #P0703)
 04h	read map select register (default 00h)
	bit7-3: reserved
	bit2  : EGA?? & Genoa SuperEGA: map select bit2
	bit1-0: map select (0..3)
 05h	mode register (see #P0704)
 06h	miscellaneous register (see #P0705)
 07h	color don't care register
	bit7-4: reserved
	bit3=1: color plane 3 don't care (ignore bit3)
	bit2=1: color plane 2 don't care (ignore bit2)
	bit1=1: color plane 1 don't care (ignore bit1)
	bit0=1: color plane 0 don't care (ignore bit0)
 08h	bit mask register (default FFh)
	bit7-0: bitmask for latch/databyte
	      (bit set=change allowed)
---Paradise SuperVGA---
 0Fh	lock register
	The ability to write and reread 00h..07h to this register
	is often used as detection of Paradise chips.
	bit7-0 = 01h lock/hide Paradise specific registers
	       = 05h unlock Paradise specific registers
	bit7-3: reserved
	bit2-0: flipflops, reserved
SeeAlso: #P0706

Bitfields for EGA/VGA GDC enable set/reset register:
Bit(s)	Description	(Table P0701)
 7-4	reserved (used on Genoa SuperEGA???)
 3	enable set/reset plane 3
 2	enable set/reset plane 2
 1	enable set/reset plane 1
 0	enable set/reset plane 0
 3-0	0=CPU access, 1=set/reset access to plane
SeeAlso: #P0700

Bitfields for EGA/VGA GDC color compare register:
Bit(s)	Description	(Table P0702)
 7-4	reserved
 3	color compare 3
 2	color compare 2
 1	color compare 1
 0	color compare 0
 3-0	(color number)
SeeAlso: #P0700

Bitfields for EGA/VGA data rotate register (GR3):
Bit(s)	Description	(Table P0703)
 7-5	reserved
 4-3	logical function select
	00 CPU-data overwrites
	01 CPU-data AND with latch-register
	10 CPU-data OR with latch-register
	11 CPU-data XOR with latch-register
 2-0	rotate count
SeeAlso: #P0700

Bitfields for EGA/VGA GDC mode register:
Bit(s)	Description	(Table P0704)
 7	reserved
 6	(VGA) 0=standard, 1=enable 256 colors
 5	shift register mode, 0=standard, 1=CGA-graphics
	  (not used on Genoa SuperEGA???)
 4=1	enable odd/even address mode
 3	read mode, 0=mode0, 1=mode1
 2	(EGA) test condition, 0=standard, 1=output tristate
 1-0	write mode
	00 mode0, plane source is CPU or set/reset
	01 mode1, plane source is latch-register
	10 mode2, plane source is CPU as set/reset
	11 (VGA) mode3, CPU as set/reset AND bitmask
SeeAlso: #P0700

Bitfields for EGA/VGA GDC miscellaneous register:
Bit(s)	Description	(Table P0705)
 7-4	reserved (=0)
 3-2	memory map
	00b = A0000..BFFFF (128KB)
	01b = A0000..AFFFF (64KB)
	10b = B0000..B7FFF (32KB)
	11b = B8000..BFFFF (32KB)
 1	chain odd maps to even, 1=subst addess bit0
 0	0=textmode, 1=graphics mode
SeeAlso: #P0700
--------V-P03CE03CF--------------------------
PORT 03CE-03CF - Chips&Technologies - GRAPHICS CONTROLLER EXTENDED REGISTERS
SeeAlso: PORT 03CE"EGA"

03CE  RW  graphics address register / GDC index
03CF  RW  other graphics register (see #P0706)

(Table P0706)
Values for Cirrus CL-GD7556 extended GDC registers:
 00h-08h same as EGA/VGA (see #P0700)
 09h	"GR9" display memory offset 0
 0Ah	"GRA" display memory offset 1
 0Bh	"GRB" graphics controller mode extensions
 0Ch	"GRC" color key compare value / chroma key Y minimum
 0Dh	"GRD" color key compare mask / chroma key Y maximum
 0Eh	"GRE" DPMS control
 10h	"GR10" background color expansion 1
 11h	"GR11" foreground color expansion 1
 13h	"GR13" foreground color expansion 2
 16h	"GR16" scanline counter readback (low)
 17h	"GR17" scanline counter readback (high)
 18h	"GR18" EDO RAM control
 1Ah	"GR1A" scratch pad #6
 1Bh	"GR1B" scratch pad #7
 1Ch	"GR1C" chroma-key U minimum
 1Dh	"GR1D" chroma-key U maximum
 1Eh	"GR1E" chroma-key V minimum
 1Fh	"GR1F" chroma-key V maximum
 20h	"GR20" BitBLT width (low)
 21h	"GR21" BitBLT width (high)
 22h	"GR22" BitBLT height (low)
 23h	"GR23" BitBLT height (high)
 24h	"GR24" BitBLT destination pitch (low)
 25h	"GR25" BitBLT destination pitch (high)
 26h	"GR26" BitBLT source pitch (low)
 27h	"GR27" BitBLT source pitch (high)
 28h	"GR28" BitBLT destination address (low)
 29h	"GR29" BitBLT destination address (middle)
 2Ah	"GR2A" BitBLT destination address (high)
 2Ch	"GR2C" BitBLT source address (low)
 2Dh	"GR2D" BitBLT source address (middle)
 2Eh	"GR2E" BitBLT source address (high)
 2Fh	"GR2F" BitBLT destination write mask
 30h	"GR30" BitBLT mode
 31h	"GR31" BitBLT start/status
 32h	"GR32" BitBLT raster operation
 33h	"GR33" BitBLT mode extensions
!!! (details to be added)
Note:	the scratch pad registers are reserved for use by the VGA BIOS
SeeAlso: #P0700
--------V-P03CE03CF--------------------------
PORT 03CE-03CF - Compaq Qvision - Functionality Level

03CE  -W  graphics address register (index for next port) (see #P0707)
03CF  RW  other graphics register

(Table P0707)
Values for Compaq QVision graphics register index:
 0Ch  RO    controller version
		2Fh Advanced VGA
		37h early QVision 1024
		71h QVision 1280 or later QVision 1024
 0Dh	    extended controller version
 0Eh	    extended controller capabilities
 0Fh	    environment info
 54h	    available memory
 55h	    phase-locked-loop clock
 56h-57h    controller capabilities
--------V-P03D003D3--------------------------
PORT 03D0-03D3 - CGA (Color Graphics Adapter) - MIRRORS OF 03D4/03D5

03D0  -W  same as PORT 03D4h
03D1  RW  same as PORT 03D5h
03D2  -W  same as PORT 03D4h
03D3  RW  same as PORT 03D5h
--------V-P03D403D5--------------------------
PORT 03D4-03D5 - COLOR VIDEO - CRT CONTROL REGISTERS

03D4  rW  CRT (6845) register index   (CGA/MCGA/color EGA/color VGA)
	selects which register (0-11h) is to be accessed through 03D5
	this port is r/w on some VGA, e.g. ET4000
	    bit 7-6 =0: (VGA) reserved
	    bit 5   =0: (VGA) reserved for testage
	    bit 4-0   : selects which register is to be accessed through 03D5
03D5  -W  CRT (6845) data register   (CGA/MCGA/color EGA/color VGA) (see #P0708)
	selected by PORT 03D4h. registers 0C-0F may be read
	  (see also PORT 03B5h)
	MCGA, native EGA and VGA use very different defaults from those
	  mentioned for the other adapters; for additional notes and
	  registers 00h-0Fh and EGA/VGA registers 10h-18h and ET4000
	  registers 32h-37h see PORT 03B5h (see #P0654)
	registers 10h-11h on CGA, EGA, VGA and 12h-14h on EGA, VGA are
	  conflictive with MCGA (see #P0710)

(Table P0708)
Values for EGA/VGA+ CRT Controller register index:
 00h-0Fh	same as MDA/CGA (see #P0654)
 10h R-	native VGA with bit7=1 in end horizontal blanking (03h) and ET4000:
	       start vertical retrace
 10h -W start vertical retrace
 11h R- native VGA with bit7=1 in end horizontal blanking (03h):
	       end vertical retrace
 11h -W end vertical retrace
	       bit7  : VGA: protection bit
			    =0 enable write access to 00h-07h
			    =1 read only regs 00h-07h with the exception
			       of bit4 in 07h. ET4000: protect 35h also.
	       bit6  : VGA: =0 three, =1 five refreshcycles/line
		       ET4000: reserved
	       bit5=0: (MCGA also) enable vertical interrupt
	       bit4=0: (MCGA also) clear vertical interrupt
		   =1:		   no effect
	       bit3-0: (MCGA also) vertical retrace end
 12h	vertical display end register
 13h	row offset register
	       logical screen line width in
		byte mode : bytes/(line/2)
		word mode : bytes/(line/4)
		dword mode: bytes/(line/8)
 14h	underline location register
	       bit7: reserved (0)
	       bit6: (VGA) 0=word-mode, 1=dword-mode (see 17h, bit6)
	       bit5: (VGA) 0=standard address counter clock
			   1=address counter clock/4 (see 17h, bit3)
	       bit4-0: horizontal underline row scan
 15h	(EGA,VGA) start vertical blanking-1
 16h	(EGA,VGA) end vertical blanking register
	       bit7-5 : EGA: reserved, but used on original EGA???
	       bit4-0 : end vertical blanking
 17h	(EGA,VGA) "CR17" mode control register (see #P0657)
 18h	(EGA,VGA) "CR18" line compare register
 19h	Genoa SuperEGA only: double scan control
	       at 3B5h only in MDA, HGC emulation, but at 3D5h even in
	       mono EGA modes.
	       bit7-5 : reserved
	       bit4   : HR/VR width adjust flag for double scan mode
	       bit3-1 : 1=test, 0=normal
	       bit0   : double scan enable
 22h	(VGA) "CR22" CPU Latch Data Register (read-only)
 24h	(VGA) "CR24" Attribute Controller Toggle register (R-O) (see #P0709)
 3xh	(VGA)  !!!chips\64200.pdf p.57
Notes:	registers 10h-14h on the MCGA have conflicting uses (see #P0710)
	registers 22h,24h, and 3xh exist on the standard IBM VGA but were not
	  documented
SeeAlso: #P0756,#P0716,#P0717

Bitfields for VGA "CR24" Attribute Controller Toggle register:
Bit(s)	Description	(Table P0709)
 7-3	current attribute controller index
 2	palette address source
 1	reserved
 0	state of attribute-controller flip-flop (0 = index, 1 = data)
Note:	this register was not documented for the original IBM VGA; this
	   description is from the C&T Wingine documentation
SeeAlso: #P0708,#P0718

(Table P0710)
Values for MCGA (only) CRT Controller register index:
 00h-0Fh	same as MDA/CGA (see #P0654)
 10h -W mode control register (defaults 18h, 1Ah, 19h) (see #P0711)
 10h R-	mode control status register (see #P0712)
 11h -W	interrupt control register (default 30h) (see #P0713)
 12h RW	character generator/sync polarity register (see #P0714)
 12h R-	display sense register (int. control reg [11h] bit7=1)
	bit 7-2	 : not used
	bit 1-0	 : pins 11 & 12 in monitor cable
		00b = reserved
		01b = analogue monochrom monitor
		10b = analogue color graphics monitor
		11b = no monitor
 13h -W character font pointer register (see #P0710)
	only 00h, 10h, 20h, 30h (default 00h) are allowed here
	  for textmode fonts at A0000, A2000, A4000, A6000
 14h -W	number of characters to load during vert. retrace period (default FFh)
Note:	registers 10h-14h can appear at PORT 03D5h only, not at 03B5h
SeeAlso: #P0654,#P0708,#P0756,#P0715

Bitfields for MCGA (only) CRT mode control register:
Bit(s)	Description	(Table P0711)
 7	suppress hsync/vsync
 6	reserved (0)
 5	reserved
 4	dot clock rate
 3	refresh calculations in 80x25 modes
 2	reserved
 1	videomode 11h active
 0	videomode 13h active
SeeAlso: #P0710,#P0712

Bitfields for MCGA (only) CRT mode control status register:
Bit(s)	Description	(Table P0712)
 7	status bit0 CGA mode control register
 6	reserved
 5	clockrate 640 pixel, =0: clockrate/2 320 pixel
 4	clock rate is 25,175Mhz
 3	currently in textmode
 2	double-scan activated
 1	videomode 11h active
 0	videomode 13h active
SeeAlso: #P0710,#P0711

Bitfields for MCGA (only) CRT interrupt control register:
Bit(s)	Description	(Table P0713)
 7	set output driver to tristate
	=0: for reading of character generator reg (12h)
	=1: for reading of display sense register (12h)
 6   R	intr generated by memory controller
 5	=0 requested intr ok to handle
 4	=0 free interrupt latch register
 3-0	reserved
SeeAlso: #P0710

Bitfields for MCGA (only) CRT character generator/sync polarity register:
Bit(s)	Description	(Table P0714)
 7	character generator active
 6	=1 load codepage during display
	=0 load codepage during retrace
 5	codepage number (0,1)
 4	512 characters active
 3	reserved (0)
 2	enable hsync/vsync
 1	positive vsync polarity
 0	positive hsync polarity
Note:	default 46h in all modes, except 04h in mode 11h)
SeeAlso: #P0710
--------V-P03D403D5--------------------------
PORT 03D4-03D5 - Chips&Technologies VIDEO CHIPS - EXTENDED CRT CONTROL REGISTERS
SeeAlso: PORT 03D4h"COLOR VIDEO",PORT 03D4h"Tseng"

03D4  RW  CRT control register index (see #P0715)
03D5  RW  CRT control register value

(Table P0715)
Values for Chips&Technologies CRT Controller register index:
 00h-18h same as EGA/VGA (see #P0708)
 22h	same as VGA (see #P0708)
 24h	same as VGA (see #P0708)
---C&T 82C4xx---
 D3h RW "RD3" 82C426: gray-level control 1 !!!chips\82c426.pdf p.16
 D4h RW "RD4" 82C426: gray-level control 2
 D5h RW "RD5" 82C426: general purpose
 D6h RW "RD6" 82C426: sleep
 D7h RW "RD7" 82C426: panel size
 D8h RW "RD8" 82C426: panel configuration
 D9h RW "RD9" AC control   !!!chips\82c425.pdf p.27
 DAh RW "RDA" threshold
 DBh RW "RDB" shift parameter
 DCh RW "RDC" horizontal sync width
 DDh RW "RDD" vertical sync width / blink control
 DEh RW "RDE" timing control
 DFh RW "RDF" function control
SeeAlso: #P0654,#P0710,#P0756,#P0716
--------V-P03D403D5--------------------------
PORT 03D4-03D5 - Cirrus Logic VIDEO CHIPS - EXTENDED CRT CONTROL REGISTERS
SeeAlso: PORT 03D4h"COLOR VIDEO",PORT 03D4h"Tseng"

03D4  RW  CRT control register index (see #P0716)
03D5  RW  CRT control register value

(Table P0716)
Values for Cirrus Logic CRT Controller register index:
 00h-18h same as EGA/VGA (see #P0708)
---Cirrus CL-GD7556---
 19h	"CR19" Interlace End
 1Ah	"CR1A" miscellaneous control
 1Bh	"CR1B" extended display control
 1Ch	"CR1C" horizontal total and sync
 1Dh	"CR1D" color key compare type
 22h	same as VGA (see #P0708)
 24h	same as VGA (see #P0708)
 25h	"CR25" revision
 26h	"CR26" attribute controller index readback
 27h	"CR27" device identification
 30h	"CR30" TV-OUT control
 31h	"CR31" Video Window horizontal upscaling coefficient
 32h	"CR32" Video Window vertical upscaling coefficient
 33h	"CR33" Video Window horizontal start (high)
 34h	"CR34" Video Window horizontal start (low)
 35h	"CR35" Video Window brightness
 36h	"CR36" Video Window vertical position extension
 37h	"CR37" Video Window vertical start
 38h	"CR38" Video Window vertical height
 ...
 42h	"CR42" Video Window FIFO threshold / chroma-key mode
 50h	"CR50" V-Port hardware configuration
 ...
 5Fh	"CR5F" V-Port capture window start address (low)
 80h	"CR80" power management control
 ...
 91h	"CR91" shading map offset
 A0h	"CRA0" CRT horizontal 8-dot character clock
 ...
 BFh	"CRBF" CRT vertical back porch
!!! details to be added
SeeAlso: #P0654,#P0756,#P0717
--------V-P03D403D5--------------------------
PORT 03D4-03D5 - S3 VIDEO CHIPS - EXTENDED CRT CONTROL REGISTERS
SeeAlso: PORT 03D4h"COLOR VIDEO",PORT 03D4h"Tseng"

03D4  RW  CRT control register index (see #P0717)
03D5  RW  CRT control register value

(Table P0717)
Values for S3, Inc. CRT Controller register index:
 00h-18h same as EGA/VGA (see #P0708)
 22h	same as VGA (see #P0708)
 24h	"CR24" attribute controller index/data status
 26h R- "CR24" (duplicate of 24h)
 2Dh R- "CR2D" new Chip ID (high) (same as high byte of PCI device ID)
 2Eh R- "CR2E" new chip ID (low) (same as low byte of PCI device ID)
		10h Trio32
		11h Trio64
 2Fh R- "CR2F" S3 7xx/866/x68: chipset revision
		chip ID 8811h is Trio64/64V+; revision 4xh or 5xh is Trio64V+
 30h RW	"CR30" chip ID/revision (see #P0719)
 31h RW	"CR31" memory configuration (see #P0720)
 32h RW "CR32" backward compatibility 1 (see #P0721)
 33h RW "CR33" backward compatibility 2 (see #P0722)
 34h RW "CR34" backward compatibility 3 (see #P0723)
 35h RW "CR35" CRT register lock (see #P0724)
 36h R	"CR36" Reset State read 1 (see #P0725)
 37h R	"CR37" Reset State read 2 (see #P0726)
 38h RW	"CR38" S3 Register lock 1
	set reg 38h to 48h and reg 39h to A5h to unlock other S3 registers
 39h RW	"CR39" S3 Register lock 2
 3Ah RW "CR3A" S3 Miscellaneous 1 (see #P0727)
	bit 4: ???
 3Bh RW "CR3B" Data Transfer Execute position (see #P0728)
 3Ch RW "CR3C" Interlace Retrace start position (see also #P0730)
 40h RW "CR40" System Configuration (see #P0729)
 41h	"CR41" BIOS Flag register (used by S3 BIOS)
 42h RW "CR42" mode control (see #P0730)
 43h RW "CR43" extended mode (see #P0731)
 45h RW "CR45" hardware graphics cursor mode (see #P0732)
 46h RW "CR46" hardware cursor origin X (hi), bits 2-0 only
 47h RW "CR47" hardware cursor origin X (lo)
	testing that register 47h can be read and written once the S3 registers
	  are unlocked is used as an S3 installation check
 48h RW	"CR48" hardware cursor origin Y (hi), bits 2-0 only
	the cursor X/Y position is latched on writing the high byte of Y
 49h RW "CR49" hardware cursor origin Y (lo)
 4Ah RW "CR4A" hardware graphics cursor foreground stack
	read register 45h, then write 2 or 3 color bytes (16/24-bit color)
	  to specify foreground color of hardware cursor
 4Bh RW "CR4B" hardware graphics cursor background stack
	read register 45h, then write 2 or 3 color bytes (16/24-bit color)
	  to specify background color of hardware cursor
 4Ch RW "CR4C" hardware graphics cursor map start address (hi), bits 3-0 only
 4Dh RW "CR4D" hardware graphics cursor map start address (lo)
 4Eh RW "CR4E" hardware cursor pattern start X (bits 5-0 only)
 4Fh RW "CR4F" hardware cursor pattern start Y (bits 5-0 only)
 50h RW "CR50" S3 801+: Extended System Control 1 (see #P0733)
 51h RW "CR51" S3 801+: Extended System Control 2 (see #P0734)
 52h RW "CR52" S3 801+: Extended BIOS Flag 1
		bits 7-6 are sync polarities (see #P0669) for Diamond cards
 53h RW "CR53" S3 801+: Extended Memory Control 1 (see #P0735)
 54h RW "CR54" S3 801+: Extended Memory Control 2 (see #P0736,#P0737)
 55h RW "CR55" S3 801+: Extended Video DAC Control (see #P0738)
 56h RW "CR56" S3 801+: External Sync Control 1 (see #P0739)
 57h RW "CR57" S3 801+: External Sync Control 2 (see #P0740)
 58h RW "CR58" S3 801+: Linear Address Window Control (see #P0741)
 59h RW "CR59" S3 801+: Linear Address Window Position (bits 31-24)
 5Ah RW "CR5A" S3 801+: Linear Address Window Position (bits 23-16)
	Notes:	the address is forced to be a multiple of the memory window
		  size (see #P0741) by ignoring the lowest bits
		for Trio64 new memory-mapped I/O, the LAW must be on a 64M
		  boundary
 5Bh RW "CR5B" S3 801+: Extended BIOS Flag 2
 5Ch RW "CR5C" S3 801+: General Output Port (see #P0742)
 5Dh RW "CR5D" S3 801+: Extended Horizontal Overflow (see #P0743)
 5Eh RW "CR5E" S3 801+: Extended Vertical Overflow (see #P0744)
 5Fh RW "CR5F" S3 928/964: Bus Grant Termination Position
 60h RW "CR60" S3 864/964: extended memory control 3 (see #P0745)
 61h RW "CR61" S3 864/964/Trio: extended memory control 4 (see #P0746)
 62h RW "CR62" S3 864/964: extended memory control 5
 63h RW "CR63" S3 864/964: external sync delay adjustment (high) (see #P0747)
 64h RW "CR64" S3 864/964: genlocking adjustment
 65h RW "CR65" S3 864/964: extended miscellaneous control (see #P0748)
 66h RW "CR66" S3 864/964: extended miscellaneous control 1 (see #P0749)
 67h RW "CR67" S3 864/964: extended miscellaneous control 2 (see #P0750)
 67h RW "CR67" S3 Trio32/64: extended miscellaneous control 2 (see #P0751)
 68h RW "CR68" S3 864/964: configuration 3 (see #P0752)
 69h RW "CR69" S3 864/964: extended system control 3 (see #P0753)
 6Ah RW "CR6A" S3 864/964: extended system control 4
		(bits 5-0 = offset of 64K bank)
 6Bh RW "CR6B" S3 864/964: extended BIOS flag 3
 6Ch RW "CR6C" S3 864/964: extended BIOS flag 4
 6Dh RW "CR6D" S3 864/964: extended miscellaneous control
 6Dh RW "CR6D" S3 Trio64V+: extended BIOS flag 5 (reserved for BIOS)
 6Eh RW "CR6E" S3 Trio64V+: extended BIOS flag 6 (reserved for BIOS)
 6Fh RW "CR6F" S3 Trio64V+: configuration 4 (see #P0755)
SeeAlso: #P0654,#P0710,#P0756,#P0716,#P0715

Bitfields for S3 "CR24" Attribute Index register:
Bit(s)	Description	(Table P0718)
 7	inverse of current state of internal address flip-flop
 6	reserved (0)
 5	video display is enabled (mirror of PORT 03C0h bit 5)
 4-0	current attribute contorller index (from PORT 03C0h)
SeeAlso: #P0708,#P0709,PORT 03C0h

(Table P0719)
Values for S3 chip ID/Revision register "CR30":
 81h	86c911
 82h	86c911A/924
 90h	86c928 (original)
 ...
 A0h	86c801/805 A-step or B-step
 ...
 B0h	86c928 PCI
 C0h	Vision864
 C1h	Vision864P
 D0h	Vision964
 D1h	Vision964P
 Exh	Trio32/64, 86c866, 86c868, 86c968; actual ID and revision stored in
	  PORT 03B5h registers 2Dh, 2Eh, and 2Fh
SeeAlso: #P0720

Bitfields for S3 "CR31" memory configuration register:
Bit(s)	Description	(Table P0720)
 7	(except 864/964) enable BIOS ROM address space C6800h-C7FFFh
	(Trio64V+) reserved
 6	enable page-mode memory access for text-mode font access
 5-4	display start address, bits 17&16.  See also registers 51h and 69h
 3	video memory above 256K accessible
 2	VGA 16-bit memory bus (clear for 8-bit memory bus)
 1	two-page screen image (enables 2048-pixel wide screen)
 0	enable base-address offset (turn on bank-switched operation)
SeeAlso: #P0708,#P0719,#P0721

Bitfields for S3 "CR32" Backwards Compatibility 1 register:
Bit(s)	Description	(Table P0721)
 7	(928,964) tri-state serial output pins SC, SOE0, and SXNR
 6	fix VGA screen page using display start address bits 16&17 (see #P0720)
	(Trio64V+) force wrap on 256K boundary even when display start address
	  changed
 5	???
 4	enable hardware interrupts
 3	backward-compatible modes (set for MDA/CGA/EGA/HGC)
 2	force full character clock for horizontal timing (CGA/HGC emulation),
	  rather than 1/2 dot clock rate
 1-0	character clock period
	00 IBM-compatible, 8 or 9 dots
	01 7 dots
	10 9 dits
Note:	on the Trio64V+, bits 7, 5, and 3-0 are reserved
SeeAlso: #P0720,#P0722,#M0076

Bitfields for S3 "CR33" Backwards Compatibility 2 register:
Bit(s)	Description	(Table P0722)
 7	override CGA "enable video" at PORT 03D8h bit 3
 6	lock palette/overscan registers
 5	blank signal does not include border area, is same as display enable
 4	disable writes to RamDAC
 3	VCLK is internal DCLK rather than inverted DCLK/2 or external VCLK
 2	reserved (Trio32/64)
 1	disable VDE protection (PORT 03D4h register 11h bit 7 will not act
	  on PORT 03D4h register 7h bits 1 and 6)
 0	reserved (Trio32/64)
Note:	on the Trio64V+, bits 7, 2, and 0 are reserved
SeeAlso: #P0708,#P0721,#P0723

Bitfields for S3 "CR34" Backwards Compatibility 3 register:
Bit(s)	Description	(Table P0723)
 7-5	(Trio32/64/64V+) reserved
 7	lock PORT 03C2h bits 2,3
 5	lock SR1 bit 5
 4	enable Start Display FIFO Fetch register (CR3B) (see #398)
 3	(Trio32/64/64V+) reserved
 2	PCI retries not handled during DAC cycles (requires bit 0 clear)
 1	do not handle PCI master aborts during DAC cycles (requires bit 0 clear)
 0	disable PCI master aborts/retries during DAC cycles
SeeAlso: #P0722,#P0724

Bitfields for S3 "CR35" Register Lock register:
Bit(s)	Description	(Table P0724)
 7-6	(Trio32/Trio64) reserved
 5	lock horizontal timing registers
 4	lock vertical timing registers
 3-0	CPU base address (in 64K units), bits 17-14
SeeAlso: #P0708,#P0723,#P0725

Bitfields for S3 "CR36" Configuration 1 register:
Bit(s)	Description	(Table P0725)
 7-5	video memory size
	111 less than 1M
	110 one meg
	100 two megs
	010 three megs
	000 four megs
	101 six megs
	011 eight megs
 4	(Trio32/64, VL-Bus only) enable video BIOS accesses
 3-2	(Trio32/64) memory type
	00 reserved
	01 reserved
	10 EDO
	11 fast page mode
 1-0	(Trio32/64) system bus type
	00 reserved
	01 VESA local bus
	10 PCI
	11 reserved
Note:	the default value of this register is latched from external pins at
	  power-up; bits 1-0 are read-only
SeeAlso: #P0708,#P0724,#P0726

Bitfields for S3 "CR37" Configuration 2 register:
Bit(s)	Description	(Table P0726)
 7-5	monitor type
 7-5	(Trio64V+) reserved
 4	(VL-Bus) enable RAMDAC write snooping
 3	use internal DCLK/MCLK (clear this bit for testing only)
 2	(VL-Bus) video BIOS ROM size (=0 64K, =1 32K)
 1	test mode select (=0 tri-state all outputs, =1 normal operation)
 1	(Trio64V+) reserved
 0	(VL-Bus) enable Trio chip (if 0, disabled except for video BIOS access)
Notes:	the default value of this register is latched from external pins at
	  power-up
	the description of this register is based on the Trio32/Trio64/Trio64V+
	  documentation and may vary somewhat for other S3 chips
SeeAlso: #P0708,#P0725

Bitfields for S3 "CR3A" Miscellaneous 1 register:
Bit(s)	Description	(Table P0727)
 7	disable PCI burst read cycles
	(must set CR66 bit 7 before setting this bit)
 6	reserved
 5	enable high-speed text font writes (only required for DCLK > 40MHz)
 4	enable >= 8 bpp color enhanced modes
 3	enable top-of-memory access (simultaneous VGA text and enhanced mode)
 2	enable alternate refresh count control (bits 1-0)
	when enabled, bits 1-0 override CR11 bit 6
 1-0	alternate refresh count: number of refresh cycles per scan line
Note:	the description of this register is based on the Trio32/Trio64/Trio64V+
	  documentation and may vary somewhat for other S3 chips
SeeAlso: #P0708

Bitfields for S3 "CR3B" Start Display FIFO Register:
Bit(s)	Description	(Table P0728)
 7-0	bits 7-0 of time in characters clocks from start of active display
	  until FIFO data fetching restarts after start of horizontal blanking
	  (bit 8 is in CR5D bit 6)
Note:	the value for this register is typically CR0 less 5, and helps ensure
	  adequate time for RAM refresh, etc. taht require control of display
	  memory
SeeAlso: #P0708

Bitfields for S3 "CR40" System Configuration register:
Bit(s)	Description	(Table P0729)
 7-6	reserved (0)
 5	reserved ("WDL_DELAY") (1)
 4	(VL-Bus) Ready Control
	=0 zero wait-states from -SADS to -SRDY
	=1 minimum one wait state (controlled by CR58 bit 3)
 3-1	reserved (0)
 0	enable enhanced (8514/A superset) register access at PORT x2E8h
SeeAlso: #P0708

Bitfields for S3 "CR42" Mode Control register:
Bit(s)	Description	(Table P0730)
 7-6	reserved (0)
 5	interlaced video
 4-0	reserved
Note:	bit 5 also enables CR3C
SeeAlso: #P0708,#P0731

Bitfields for S3 "CR43" Extended Mode register:
Bit(s)	Description	(Table P0731)
 7	double horizontal CRT parameters (CRTC registers 00h, etc.)
 6-3	reserved (0)
 3	(Trio64V+) ??? used by BIOS, officially reserved
 2	logical screen width (CR13), bit 8
 1-0	reserved (0)
Note:	bit 2 is disabled unless CR51 bits 5-4=00
SeeAlso: #P0708,#P0730

Bitfields for S3 "CR45" Hardware Graphics Cursor Mode register:
Bit(s)	Description	(Table P0732)
 7-5	reserved (0)
 4	enable Hardware Cursor Right Storage (last 256 bytes of 1K line, or
	  last 512 bytes of 2K line)
 3-1	reserved (0)
 0	enable hardware graphics cursor in Enhanced (8514/A) mode
SeeAlso: #P0708

Bitfields for S3 "CR50" Extended System Control 1 register:
Bit(s)	Description	(Table P0733)
 7-6	Graphics Engine screen width
	(note: bit 0 below is MSB for the following)
	000 = 1024 (2048 if CR31 bit 1 set)
	001 = 640
	010 = 800 (1600x1200x4 if PORT 4AE8h bit 2 set)
	011 = 1280
	100 = 1152
	101 reserved
	110 = 1600
	111 reserved
 5-4	pixel length for command execution through Graphics Engine (8514/A)
	00 one byte (4 or 8 bits/pixel)
	01 two bytes (16 bpp)
	10 reserved
	11 four bytes (32 bpp)
 3	reserved (0)
 2	enable -BREQ/-BGNT functions (reserved on Trio64V+)
 1	reserved (0)
 0	bit 2 of Graphics Engine screen width (refer to bits 7-6 above)
SeeAlso: #P0708,#P0735,#P0734

Bitfields for S3 "CR51" Extended System Control 2 register:
Bit(s)	Description	(Table P0734)
 7-6	reserved (0)
 5-4	logical screen width, bits 9-8
 3-2	CPU base address, bits 19-18
 1-0	display start address, bits 19-18
Notes:	if the upper four bits of the display start address have been set via
	  CR69 bits 3-0, then bits 1-0 and CR31 bits 5-4 are ignored
	if the upper 6 base address bits have been set via CR6A bits 5-0, then
	  bits 3-2 and CR35 bits 3-0 are ignored
SeeAlso: #P0708,#P0733

Bitfields for S3 "CR53" Extended Memory Control 1 register:
Bit(s)	Description	(Table P0735)
 7	reserved
 6	(Trio32/64/64V+) swap nybbles in each byte of video memory read or
	  written
 5	(801/805) memory interleaving
	(928) pixel multiplexing
	(Trio64V+) enable memory-mapped I/O at B8000h-BFFFFh instead of
	  A0000h-AFFFFh (only takes effect if bits 4-3=10)
 4	enable memory-mapped I/O (Trio32, Trio64 and Trio64V+)
 3	enable new memory-mapped I/O (Trio64V+)
 2-1	(Trio64V+) byte swapping for linear addressing
	00 none (default)
	01 swap bytes of word
	10 swap all bytes of doublewords
	11 reserved
	(used for big-endian addressing)
 0	(Trio32/64) enable write per bit
	(Trio64V+) reserved
SeeAlso: #P0708,#P0736

Bitfields for S3 Trio32/64 "CR54" Extended Memory Control 2 register:
Bit(s)	Description	(Table P0736)
 7-3	"M" number of 8-byte memory cycles not dedicated to filling display
	  FIFO (less one)
 2-0	reserved (0)
SeeAlso: #P0737,#P0708,#P0735

Bitfields for S3 Trio64V+ "CR54" Extended Memory Control 2 register:
Bit(s)	Description	(Table P0737)
 2,7-3	"M" maximum number of 8-byte memory cycles before LPB/CPU/Graphics
	  Engine must yield the memory bus
 1-0	big-endian byte-swapping (except for linear addressing/image writes)
	00 none (default)
	01 swap bytes within a word
	10 swap all bytes within a doubleword
	11 swap according to bus' byte-enable lines
		BE#[3:0]=0000 swap all bytes
		BE#[3:0]=0011 or 1100 swap bytes within selected word
		else no swapping
SeeAlso: #P0708,#P0736 

Bitfields for S3 "CR55" Extended RAMDAC Control register:
Bit(s)	Description	(Table P0738)
 7	tri-state VCLK output
 6-5	reserved (0)
 4	hardware cursor mode
	=0 MS-Windows
	=1 X11
 3	reserved (0)
 2	enable General Input Port read (at PORT 03C8h)
 1-0	reserved (0)
SeeAlso: #P0708

Bitfields for S3 "CR56" External Sync Control 1 register:
Bit(s)	Description	(Table P0739)
 7-5	reserved (0)
 4	preset frame select
	=0 start with odd frame after V-counter reset
	=1 start with even frame
 3	reset only vertical counter on falling edge of VSYNC input when
	  genlocking
 2	tri-state VSYNC output
 1	tri-state HSYNC output
 0	enable VSYNC input for genlocking
Note:	bits 4-3 are reserved on the Trio64V+
SeeAlso: #P0708,#P0740

Bitfields for S3 "CR57" External Sync Control 2 register:
Bit(s)	Description	(Table P0740)
 7-0	delay in scan lines from falling edge of VSYNC to reset of V-counter
Note:	this register must NOT be 00h when genlocking is enabled (CR56 bit 0)
SeeAlso: #P0708,#P0739

Bitfields for S3 "CR58" Linear Addressing Control register:
Bit(s)	Description	(Table P0741)
 7	RAS Pre-Charge time adjust
	=0 CR68 bit 3 defines pre-charge time
	=1 decrease pre-charge time by 0.5 MCLKs, increase RAS time by 0.5 MCLKs
 6-5	reserved
 4	enable linear addressing (see also #P1022)
 3	(VL-Bus) addresses latched in T1 cycle, instead of delaying one clock
	  until T2 cycle; only in effect when CR40 bit 4 is set
 2	reserved
 1-0	linear address window size
	00 = 64K (not available when new MMIO enabled)
	01 = 1M
	10 = 2M
	11 = 4M (Trio64/64V+, not Trio32)
Note:	this description is based on the Trio32/Trio64 documenation; the
	  bits may vary slightly for other S3 chips
SeeAlso: #P0723

Bitfields for S3 "CR5C" General Output Port:
Bit(s)	Description	(Table P0742)
 7-0	system-specific
---Diamond---
 0	???
 1	???
---STB Pegasus---
 7	map video memory with bits 31-26 = 011111
SeeAlso: #P0708

Bitfields for S3 "CR5D" Extended Horizontal Overflow register:
Bit(s)	Description	(Table P0743)
 7	bit 8 of Bus-Grant Terminate Position (CR5F)
	(Trio64V+) reserved
 6	bit 8 of Start FIFO Fetch (CR3B)
 5	extend horizontal sync pulse by 32 DCLKs
 4	bit 8 of Start Horizontal Sync Position (CR4)
 3	extend horizontal blank pulse by 64 DCLKs
 2	bit 8 of Start Horizontal Blank (CR2)
 1	bit 8 of Horizontal Display End (CR1)
 0	bit 8 of Horizontal Total (CR0)
SeeAlso: #P0708,#P0744

Bitfields for S3 "CR5E" Extended Vertical Overflow register:
Bit(s)	Description	(Table P0744)
 7	reserved (0)
 6	line compare position (CR18), bit 10
 5	reserved (0)
 4	vertical retrace start (CR10), bit 10
 3	reserved (0)
 2	start of vertical blank (CR15), bit 10
 1	vertical display end (CR12), bit 10
 0	vertical total (CR6), bit 10
SeeAlso: #P0708,#P0743

Bitfields for S3 Trio32/64 "CR60" Extended Memory Control 3 register:
Bit(s)	Description	(Table P0745)
 7-0	"N" maximum number of 4-byte (1M video memory) or 8-byte (2M/4M) units
	  written to display FIFO in an uninterruptible burst
SeeAlso: #P0708,#P0746

Bitfields for S3 Trio64V+ "CR61" Extended Memory Control 4 register:
Bit(s)	Description	(Table P0746)
 7	reserved
 6-5	byte-swapping for image writes
	00 none (default)
	01 swap bytes within each word
	10 swap all bytes within a doubleword
	11 reserved
 4-0	reserved
SeeAlso: #P0708,#P0745

Bitfields for S3 Trio32/64 "CR63" External Sync Control 3 register:
Bit(s)	Description	(Table P0747)
 7-4	character clock reset delay
 3-0	HSYNC reset adjustment, in character clocks
Notes:	these two values are used to align the external and internally-generated
	  video during genlocking
	this register is not documented for the Trio64V+, and may not exist
SeeAlso: #P0708

Bitfields for S3 Trio32/64/64V+ "CR65" Extended Miscellaneous Control register:
Bit(s)	Description	(Table P0748)
 7-5	reserved (0)
 4-3	(Trio32/64V+) delay -BLANK by N DCLKs
	a two-DCLK delay is required for color mode 12
 2	video subsystem setup address
	(Trio64V+) reserved
	=0 PORT 46E8h
	=1 PORT 03C3h
 1-0	reserved (0)
SeeAlso: #P0708,#P0749

Bitfields for S3 Trio32/64/64V+ "CR66" Extended Miscellaneous Control 1 reg:
Bit(s)	Description	(Table P0749)
 7	enable PCI bus disconnect on misaligned burst memory accesses
 6	tri-state pixel address bus
---Trio32/64---
 5-0	reserved (0)
---Trio64V+ ---
 5	??? (officially reservd, but set by BIOS)
 4	reserved
 3	generate PCI bus disconnect when trying to write to a full FIFO or read
	  from an empty FIFO
	(bit 7 must also be set to enable this feature)
 2	reserved
 1	software reset graphics engine
 0	enable enhanced functions (this is a mirror of
	  PORT 4AE8h bit 0)
SeeAlso: #P0708,#P0748,PORT 4AE8h

Bitfields for S3 864/964 "CR67" Extended Miscellaneous Control 2 register:
Bit(s)	Description	(Table P0750)
 7-4	color mode???
	(values of 0000/0010/0101/0111 indicate a 16-bit pixel port)
 3-2	???
SeeAlso: #P0708,#P0723,#P0751

Bitfields for S3 Trio32/64/64V+ "CR67" Extended Miscellaneous Control 2 reg:
Bit(s)	Description	(Table P0751)
 7-4	color mode (see #P0688)
 3-2	(Trio32/Trio64) reserved (0)
 3-2	(Trio64V+) streams mode
	00 disable Streams Processor
	01 overlay secondary stream on VGA-mode background
	10 reserved
	11 full Streams Processor operation
 1	reserved (0)
 0	VCLK phase (=0 VCLK is inverted DCLK; =1 VCLK in phase with DCLK)
Note:	the streams mode should only be changed during vertical sync
	  (PORT 03DAh bit 3)
SeeAlso: #P0708,#P0750,#P0687

Bitfields for S3 Trio32/64/64V+ "CR68" Configuration 3 register:
Bit(s)	Description	(Table P0752)
 7	(Trio32/64 VL-Bus) Upper Address Decode
	=0 decode all 32 bits of system address bus
	=1 SAUP input used to decode upper address lines
 7	(Trio64V+) memory data bus size
	=0 32 bits
	=1 64 bits (if >= 2M of memory)
 6-4	monitor information (used by S3 bios)
 3	RAS precharge timing (0 = 3.5 MCLKs, 1 = 2.5 MCLKs)
 2	RAS low timing (0 = 4.5 MCLKs, 1 = 3.5 MCLKs)
 1-0	-CAS and -OE stretch, -WE delay
	00 = 6.5ns stretch, 2 units delay
	01 = 5ns stretch, 1 unit delay
	10 = 3.5ns stretch, no delay
	11 = no stretch, no delay
Note:	the default value of this register is latched from external pins at
	  power-up
SeeAlso: #P0708

Bitfields for S3 Trio32/Trio64 "CR69" Extended System Control 3 register:
Bit(s)	Description	(Table P0753)
 7-4	reserved (0)
 3-0	display start address, bits 19-16
SeeAlso: #P0708,#P0754

Bitfields for S3 Trio32/Trio64 "CR6A" Extended System Control 4 register:
Bit(s)	Description	(Table P0754)
 7-6	reserved
 5-0	bits 19-14 of CPU base address
Note:	CR31 bit 0 must be set to enable this register
SeeAlso: #P0708,#P0753

Bitfields for S3 Trio64V+ "CR6F" Configuration 4 register:
Bit(s)	Description	(Table P0755)
 7-5	reserved
 4-3	WE# delay (on both rising and falling edges)
	00 three units
	01 two units
	10 one unit
	11 no delay
 2	disable I/O PORT mirror of serial port (MMIO FF20h)
	=0 allow access via either MMIO FF20h or port selected by bit 1
 1	serial port address select (only has effect if bit 2 clear)
	=0 mirror MMIO FF20h at PORT 00E8h
	=1 mirror MMIO FF20h at PORT 00E2h
 0	configure for Trio64-compatible mode instead of LPB mode
 !!! p.19-16
SeeAlso: #P0708,MEM A000h:FF00h"S3"
--------V-P03D403D5--------------------------
PORT 03D4-03D5 - Tseng Labs VIDEO CHIPS - EXTENDED CRT CONTROL REGISTERS
SeeAlso: PORT 03D4h"COLOR VIDEO",PORT 03D4h"S3",PORT 03D4h"Cirrus"

03D4  RW  CRT control register index (see #P0756)
03D5  RW  CRT control register value

(Table P0756)
Values for Tseng Labs ET3000/ET4000 CRT Controller register index:
 00h-18h same as EGA/VGA (see #P0708)
---ET3000 only---
 1Bh	x-zoom start register
	The existence of this register is often used to decide between ET3000
	  and ET4000, as the ET4000 does not offer hardware-zoom features.
 1Ch	x-zoom end register
 1Dh	y-zoom start register low
 1Eh	y-zoom end register low
 1Fh	y-zoom start & end high register
 20h	zoom start address register low
 21h	zoom start address register medium
 23h	extended start address (see register 33h)
 24h	compatibility register (see register 34h)
 25h	overflow high register (see registers 35h, 07h)
---ET4000---
 32h	RAS/CAS configuration ('key' protected) (see #P0757)
 33h	extended start address
	      This register is often used to decide between ET4000
	      and ET3000, when bit3-0 can be reread after write.
	       bit7-4 : reserved
	       bit3-2 : cursor address bit 17-16
	       bit1-0 : linear start address bits 17-16
 34h	6845 compatibility control register ('key' protected)
	  (see #P0758)
 35h	overflow high register (protected by 11h, bit7) (see #P0759)
 36h	video system configuration 1 ('key' protected) (see #P0760)
 37h	video system configuration 2 ('key' protected) (see #P0761)
SeeAlso: #P0654,#P0716,#P0717

Bitfields for ET4000 RAS/CAS configuration register:
Bit(s)	Description	(Table P0757)
 7	static column memory
	ET4000/W32i: interleave mode
 6	RAL RAS&CAS column setup time
 5	RCD RAS & CAS time
 4-3	RSP, RAS pre-charge time
 2	CPS, CAS pre-charge time
 1-0	CSW, CAS low pulse width
SeeAlso: #P0708,#P0758

Bitfields for ET4000 compatibility control register:
Bit(s)	Description	(Table P0758)
 7	6845 compatibility enabled
 6	ENBA enable double scan/underline in AT&T mode
 5	ENXL enable translation ROM on writing
 4	ENXR enable translation ROM on reading
 3	ENVS VSE register port address
 2	TRIS tristate ET4000 output pins
 1	CS2 MCLCK clock select 2
 0	EMCK enable translation of CS0 bit
SeeAlso: #P0708,#P0757,#P0759

Bitfields for ET4000 overflow high register:
Bit(s)	Description	(Table P0759)
 7	vertical interlace mode
 6	alternate RMW control
 5	external sync reset (gen-lock) the line/chr counter
 4	line compare bit10
 3	vertical sync start bit10
 2	vertical display end bit10
 1	vertical total bit10
 0	vertical blank start bit10
SeeAlso: #P0708,#P0758,#P0760

Bitfields for ET4000 video system configuration 1 register:
Bit(s)	Description	(Table P0760)
 7	enable 16bit I/O read/write
 6	enable 16bit display memory read/write
 5	addressing mode (0=IBM, 1=TLI)
 4	0=segment / 1=linear system configuration
 3	font width control (1=up to 16bit, 0=8bit)
 2-0	refresh count per line-1
SeeAlso: #P0708,#P0759,#P0761

Bitfields for ET4000 video system configuration 2 register:
Bit(s)	Description	(Table P0761)
 7	DRAM display memory type (1=VRAM, 0=DRAM)
 6	test (1=TLI interal test mode)
 5	priority threshold control (0=more mem BW)
 4	disable block read-ahead
 3	display memory data depth
 2	bus read data latch control
 1-0	display memory data bus width
SeeAlso: #P0708,#P0760
----------P03D603D7--------------------------
PORT 03D6-03D7 - CGA (Color Graphics Adapter) - MIRRORS OF 03D4/03D5

03D6  -W  same as 03D4
	(under OS/2, reads return 0 if full-screen DOS session,
	  nonzero if windowed DOS session)
03D7  RW  same as 03D5
----------P03D603D7--------------------------
PORT 03D6-03D7 - Chips&Technologies VGA - EXTENSION REGISTERS

03D6  -W  extension register index (see #P0762,#P0763)
03D7  RW  extension register data

(Table P0762)
Values for Chips&Technologies 64200 extension register index:
 00h	"XR00"	chip version (see #P0764)
 01h	"XR01"	configuration (see #P0765)
 02h	"XR02"	CPU interface control (see #P0767)
 03h	"XR03"	master control (see #P0768)
 04h	"XR04"	memory control (see #P0770)
 05h	"XR05"	clock control (see #P0771)
 06h	"XR06"	color palette control / DRAM interface
 07h	"XR07"	reserved
 08h	"XR08"	general purpose output select B
 09h	"XR09"	general purpose output select A
 0Ah	"XR0A"	cursor address top
 0Bh	"XR0B"	CPU paging (see #P0777)
 0Ch	"XR0C"	start address top (see #P0778)
 0Dh	"XR0D"	auxiliary offset (see #P0780)
 0Eh	"XR0E"	text mode control (see #P0781)
 0Fh	"XR0F"	configuration register 2
 10h	"XR10"	single/low map register (see #P0782)
 11h	"XR11"	high map register (see #P0783)
 14h	"XR14"	emulation mode (see #P0784)
 15h	"XR15"	write protect (see #P0785)
 16h	"XR16"	trap enable
 17h	"XR17"	trap status
 18h	"XR18"	alternate horizontal display end
 19h	"XR19"	alternate horizontal sync start / half-line
 1Ah	"XR1A"	alternate horizontal sync end (see #P0789)
 1Bh	"XR1B"	alternate horizontal total
 1Ch	"XR1C"	alternate horizontal blank start / horizontal panel size
 1Dh	"XR1D"	alternate horizontal blank end (see #P0790)
 1Eh	"XR1E"	alternate offset
 1Fh	"XR1F"	virtual EGA switch (see #P0791)
 20h	"XR20"	453 Interface ID
 21h	"XR21"	Sliding Hold A
 22h	"XR22"	Sliding Hold B
 23h	"XR23"	SHC / WBM Control
 24h	"XR24"	Flat-Panel Alternate Max Scanline / SHD / WBM Pattern
 25h	"XR25"	Flat-Panel "AltGrHVirtPanelSize" / 453 Pin Definition
 26h	"XR26"	453 Configuration
 27h	"XR27"	reserved
 28h	"XR28"	video interface (see #P0792)
 29h	"XR29"	function control
 2Ah	"XR2A"	frame interrupt count
 2Bh	"XR2B"	default video color (to be displayed when screen blanked)
 2Ch	"XR2C"	Flat-Panel VSync (FLM) Delay / force H high
 2Dh	"XR2D"	Flat-Panel HSync (LP) delay / force H low
 2Eh	"XR2E"	Flat-Panel HSync (LP) delay / force V high
 2Fh	"XR2F"	Flat-Panel HSync (LP) width / force V low
 30h	"XR30"	graphics cursor start address (high)
 31h	"XR31"	graphics cursor start address (low)
 32h	"XR32"	graphics cursor end address
 33h	"XR33"	graphics cursor X (high)
 34h	"XR34"	graphics cursor X (low)
 35h	"XR35"	graphics cursor Y (high)
 36h	"XR36"	graphics cursor Y (low)
 37h	"XR37"	graphics cursor mode
 38h	"XR38"	graphics cursor mask
 39h	"XR39"	graphics cursor color 0
 3Ah	"XR3A"	graphics cursor color 1
 3Bh	"XR3B"	reserved
 3Ch	"XR3C"	serial / row count (see #P0799)
 3Dh	"XR3D"	multiplexor mode (see #P0801)
 41h	"XR41"	virtual EGA switch register (82C453)
 44h	"XR44"	software flag register 1
 45h	"XR45"	software flag register 2 / foreground color
 50h	"XR50"	panel format
 51h	"XR51"	display type
 52h	"XR52"	power-down control / panel size
 53h	"XR53"	line graphics override
 54h	"XR54"	flat-panel interface / alternate miscellaneous output
 55h	"XR55"	horizontal compensation / text 350_A compensation
 56h	"XR56"	horizontal centering / text 350_B compensation
 57h	"XR57"	vertical compensation / text 400 compensation
 58h	"XR58"	vertical centering / graphics 350 compensation
 59h	"XR59"	vertical line insertion / graphics 400 compensation
 5Ah	"XR5A"	vertical line replication / FP vertical display start 400
 5Bh	"XR5B"	flat-panel vertical display end 400 
 5Ch	"XR5C"	weight control clock A
 5Dh	"XR5D"	weight control clock B
 5Eh	"XR5E"	ACDCLK control
 5Fh	"XR5F"	power-down mode refresh
 60h	"XR60"	blink rate control
 61h	"XR61"	SmartMap(tm) control
 62h	"XR62"	SmartMap(tm) shift parameter
 63h	"XR63"	SmartMap(tm) color mapping control
 64h	"XR64"	flat-panel alternate vertical total
 65h	"XR65"	flat-panel alternate overflow
 66h	"XR66"	flat-panel alternate vertical sync start
 67h	"XR67"	flat-panel alternate vertical sync end
 68h	"XR68"	flat-panel vertical panel size / alternate vertical DE end
 69h	"XR69"	flat-panel vertical display start 350
 6Ah	"XR6A"	flat-panel vertical display end 350
 6Bh	"XR6B"	flat-panel vertical overflow 2
 6Ch	"XR6C"	weight control clock C
 6Dh	"XR6D"	FRC control
 6Eh	"XR6E"	polynomial FRC control
 6Fh	"XR6F"	frame buffer control
 70h	"XR70"	setup/disable control (see #P0807)
 71h-7Ch	reserved
 7Dh	"XR7D"	flat-panel compensation diagnostic
 7Eh	"XR7E"	CGA/Hercules color selection (see #P0815)
 7Fh	"XR7F"	diagnostics (see #P0816)
!!! chips\64200.pdf p.28, p.72
Note:	not all C&T chips support all of the above registers; see the tables
	  for the individual registers for a list of supporting chipsets
SeeAlso: #P0763

(Table P0763)
Values for Chips&Technologies 64310 extension register index:
 00h	"XR00"	chip version (see #P0764)
 01h	"XR01"	configuration (see #P0766)
 02h	"XR02"	CPU interface control (see #P0767)
 03h	"XR03"	CPU interface control 2 (see #P0769)
 04h	"XR04"	memory control (see #P0770)
 05h	"XR05"	memory control 2 (see #P0772)
 06h	"XR06"	color palette control / DRAM interface (see #P0773)
 07h	"XR07"	DRxx I/O base ???
 08h	"XR08"	linear frame buffer base address low register (see #P0774)
 09h	"XR09"	linear frame buffer base address high register (see #P0775)
 0Ah	"XR0A"	XRAM mode register (see #P0776)
 0Bh	"XR0B"	CPU paging (see #P0777)
 0Ch	"XR0C"	start address top (see #P0779)
 0Dh	"XR0D"	auxiliary offset (see #P0780)
 0Eh	"XR0E"	text mode control (see #P0781)
 0Fh	"XR0F"	software flag register 0 (reserved for BIOS/driver use)
 10h	"XR10"	single/low map register (see #P0782)
 11h	"XR11"	high map register (see #P0783)
 12h-13h	reserved
 14h	"XR14"	emulation mode (see #P0784)
 15h	"XR15"	write protect (see #P0785)
 16h	"XR16"	vertical overflow register (see #P0786)
 17h	"XR17"	horizontal overflow register (see #P0787)
 18h	"XR18"	reserved
 19h	"XR19"	alternate horizontal sync start / half-line (see #P0788)
 1Ah-1Bh	reserved
 1Ch	"XR1C"	alternate horizontal blank start / horizontal panel size
 1Dh-27h	reserved
 28h	"XR28"	video interface (see #P0792)
 29h-2Ah	reserved
 2Bh	"XR2B"	software flag register 1 (used by device drivers)
 2Ch-2Fh	reserved
 30h	"XR30"	clock divide control register (see #P0793)
 31h	"XR31"	clock M-divisor register (see #P0794)
 32h	"XR32"	clock N-divisor register (see #P0795)
 33h	"XR33"	clock control register (see #P0796)
 34h-39h	reserved
 3Ah	"XR3A"	color key compare data 0 (see #P0797)
 3Bh	"XR3B"	color key compare data 1 (see #P0798)
 3Ch	"XR3C"	color key compare data 2 (see #P0800)
 3Dh	"XR3D"	color key compare mask 0 (see #P0802)
 3Eh	"XR3E"	color key compare mask 1 (see #P0803)
 3Fh	"XR3F"	color key compare mask 2 (see #P0804)
 40h	"XR40"	BitBlt config register (see #P0805)
 41h	"XR41"	reserved
 42h-43h	reserved
 44h	"XR44"	software flag register 2 (reserved for BIOS/driver use)
 45h	"XR45"	reserved
 46h-4Fh	reserved
 50h-51h	reserved
 52h	"XR52"	refresh control register (see #P0806)
 53h-5Fh	reserved
 60h	"XR60"	blink rate control
 61h-6Fh	reserved
 70h	"XR70"	setup/disable control (see #P0807)
 71h	"XR71"	GPIO control register (see #P0808)
 72h	"XR72"	GPIO data register (see #P0809)
 73h	"XR73"	misc control register (see #P0810)
 74h	"XR74"	configuration register 2 (see #P0811)
 75h	"XR75"	software flag register 3 (reserved for BIOS/driver use)
 76h-79h	reserved
 7Ah	"XR7A"	test index register (see #P0812)
 7Bh	"XR7B"	test control register (see #P0813)
 7Ch	"XR7C"	test data register (see #P0814)
 7Dh	"XR7D"	diagnostic register (reserved; should not be read or written)
 7Eh	"XR7E"	reserved
 7Fh	"XR7F"	diagnostic register (reserved; should not be read or written)
SeeAlso: #P0762

Bitfields for Chips&Technologies "XR00" chip version:
Bit(s)	Description	(Table P0764)
 7-4	chip type
	0000 = 82C451
	0001 = 82C452
	0010 = 82C455
	0011 = 82C453
	0100 = 82C450
	0101 = 82C456
	0110 = 82C457
	0111 = 65520
	1000 = 65530 / 65525
	1001 = 65510 Flat-Panel Controller
	1010 = 64200 Wingine
	1011 = 64300/301 Wingine DGX (if bit 3 clear)
	1011 = 64310 Wingine DGX-PCI (if bit 3 set)
 3-0	chip revision (0000 = first silicon)
Note:	this register is read-only
SeeAlso: #P0762,#P0765

Bitfields for Chips&Technologies 64200 "XR01" configuration:
Bit(s)	Description	(Table P0765)
 7-4	configuration bits 7-4 (latched from pins on falling edge of RESET)
 3	memory configuration
	0 video memory pins always drive
	1 video memory pins only driven when XR03 bit 0 is clear (VGA mode)
 2	source of pixel clock
	0 oscillator (CLK0-CLK3 are pixel-clock inputs, which are selected by
	  MSR bits 3-2)
	1 clock chip (CLK0 is pixel clock input, CLK1-CLK3 are CSELx outputs)
 1-0	bus type
	00 PCI
	01 Microchannel
	10 local bus
	11 ISA
Note:	this register is read-only
SeeAlso: #P0762,#P0764,#P0767,#P0766

Bitfields for Chips&Technologies 64300/64310 "XR01" configuration:
Bit(s)	Description	(Table P0766)
 7-6	(64310) reserved (0)
 7	(64300) VL-Bus CPU speed???
 6	(64300) VL-Bus zero wait state???
 5	(64310) OSC source
	0 = external
	1 = internal
 4	(64310) clock source
	0 = external (82C404C)
	1 = internal
 3	(64310) chip (bus interface and RAMDAC) enable
 2	(64310) 64310 isolate
	0 = 64310 cannot be disabled
	1 = 64310 can be disabled using port 106h in setup mode
	(64310 may also be disabled using PCI configuration registers)
 1-0	(64310) bus type
	00 reserved
	01 32-bit PCI
	10 reserved
	11 32-bit local bus
SeeAlso: #P0763,#P0765

Bitfields for Chips&Technologies "XR02" CPU interface register:
Bit(s)	Description	(Table P0767)
 7	status of attribute flip-flop (read-only) (0 = index, 1 = data)
 6	(64200) palette address decoding
	0 access only at PORT 03C6h-03C9h
	1 also access at PORT 83C6h-83C9h (for RAMDACs with 8 registers)
	(64310) reserved (0)
 5	I/O address decoding
	0 decode all 16 bits of address
	1 only decode low ten bits of address for 3B4h,3B5h,3B8h,3BAh,3BFh,
	  3C0h-3C2h,3C4h,3C5h,3CEh,3CFh,3D4h,3D5h,3D8h-3DAh
 4-3	mapping of Attribute Controller
	00 VGA mapping - write index and data at 03C0h (8-bit only)
	01 16-bit mapping - write index at 03C0h, data at 03C1h
	10 (64200 only) EGA mapping - write index at 03C0h, data at 03C0h or
		  03C1h (8-bit)
	11 reserved
 2-0	reserved (0)
SeeAlso: #P0762,#P0765,PORT 83C6h

Bitfields for Chips&Technologies "XR03" Master Control register:
Bit(s)	Description	(Table P0768)
 7	XREQ# direction (=0 input, =1 output)
 6	XREQ# divide (=0 DispEnable for all lines, =1 even-numbered lines)
 5	XREQ# mode (=0 DispEnable only, =1 split-buffer VRAM transfer timing)
	(see #P0799"XR3C",#P0801"XR3D")
 4	alternate VGA address
	=1 map at PORT 02C6h-02C9h instead of 03C6h-03C9h
 3-2	reserved
 1	alternate palette address
	=1 map at PORT 02Bxh or PORT 02Dxh instead of 03Bxh/03Dxh
 0	Wingine/VGA select
	=0 VGA
	=1 Wingine (memory pins are tri-stated)
Note:	a write-only copy of this register may be accessed at PORT 0022h
	  (index E0h) and PORT 0023h; a read-write copy exists in systems with
	  built-in Wingine support
SeeAlso: #P0762,#P0767,#P0770,#P0769

Bitfields for Chips&Technologies 64310 "XR03" CPU interface register 2:
Bit(s)	Description	(Table P0769)
 7-2	reserved (0)
 1	DRxx register access enable (I/O port defined in XR07 ???)
 0	palette write shadow
SeeAlso: #P0763,#P0768

Bitfields for Chips&Technologies "XR04" Memory Control register:
Bit(s)	Description	(Table P0770)
 7-6	(64200) reserved (0)
 7	(64310) FIFO depth
	0 = bus FIFO is 8 deep
	1 = bus FIFO is 4 deep
 6	(64310) PCI burst enable
 5	(64200) enable CPU memory write buffer
	(64310) CPU bus FIFO enable
 4-3	reserved (0)
 2	memory wraparound
	=1 enable bit 17 of CRTC address counter
 1-0	(64310) memory configuration
	   data path  chips   config   total
	00    16-bit	  4  256Kx4   1/2 MB
			  1  256Kx16  1/2 MB
	01    32-bit	  8  256Kx4	1 MB
			  2  256Kx16	1 MB
	10    32-bit	 16  256Kx4	2 MB
			  4  256Kx16	2 MB
	11  reserved
 1	(64200) reserved (0)
 0	(64200) memory configuration
	=0 8-bit data, two DRAM chips of 256Kx4
	=1 16-bit data, four DRAM chips of 256Kx4
SeeAlso: #P0762,#P0768,#P0763

Bitfields for Chips&Technologies "XR05" Clock Control register:
Bit(s)	Description	(Table P0771)
 !!!
SeeAlso: #P0762

Bitfields for Chips&Technologies 64310 "XR05" Memory Control register 2:
Bit(s)	Description	(Table P0772)
 7	VAFC PCLK/2
	0 = DCLK=PCLK
	1 = DCLK=PCLK/2
 6	VAFC enable (XR71 bits 5, 3 and 2 must be 0)
 5	reserved (0)
 4	256Kx16 access format
	0 = 2 CAS / 1 WE
	1 = 2 WE / 1 CAS
 3-0	reserved
SeeAlso: #P0763

Bitfields for Chips&Technologies "XR06" color palette control / DRAM interface:
Bit(s)	Description	(Table P0773)
 7-5	(64310) reserved (0)
 4	(64310) video overlay on color key enable
 3-2	(64310) display mode color depth
	00 = 4BPP / 8BPP
	01 = 15BPP (5-5-5) Sierra compatible
	10 = 24BPP
	11 = 16BPP (5-6-5) XGA compatible
 1	(64310) internal DAC disable
 0	(64310) enable external pixel data
	0 = VID15-0 and KEY inputs for live video overlay
	1 = P7-0 and BLANK# outputs for external feature connector/external
	  color keying (XR73 bit 5 must be set)
SeeAlso: #P0763

Bitfields for Chips&Technologies 64310 "XR08" linear frame buffer base low:
Bit(s)	Description	(Table P0774)
 7-6	linear frame buffer base address low (VL-Bus only)
	(bits 23-22 of linear frame buffer base address)
	(LFB is 4 MB boundary within 4 GB address space. Upper 2 MB is used
	  for memory mapped I/O.)
 5-0	reserved (0)
SeeAlso: #P0763,#P0775

Bitfields for Chips&Technologies 64310 "XR09" linear frame buffer base high:
Bit(s)	Description	(Table P0775)
 7-0	linear frame buffer base address high (VL-Bus only)
	(bits 23-22 of linear frame buffer base address)
	(LFB is 4 MB boundary within 4 GB address space. Upper 2 MB is used
	  for memory mapped I/O.)
SeeAlso: #P0763,#P0774

Bitfields for Chips&Technologies 64310 "XR0A" XRAM mode register:
Bit(s)	Description	(Table P0776)
 7	reserved (0)
 6	disable upper XRAM in 2MB modes
	0 = upper XRAM not enabled
	1 = upper XRAM enabled
	(used in systems with 2MB frame buffer but only single 256Kx4 XRAM)
 5	XRAM diagnostic 64 (0)
 4	synchronous XRAM enable
 3	asynchronous XRAM enable
 2-1	BitBlt update
	00 = no update during BitBlt
	11 = BitBlt update enabled
 0	XRAM test enable
	0 = XRAM normal mode
	1 = XRAM read/write
SeeAlso: #P0763

Bitfields for Chips&Technologies "XR0B" CPU Paging register:
Bit(s)	Description	(Table P0777)
 7-3	(64200) reserved (0)
 7	(64310) big-endian byte swap (32 bpp swap)
	0 = no swap
	1 = swap bytes 0-3 and 1-2
 6	(64310) big-endian byte swap (16 bpp swap)
	0 = no swap
	1 = swap bytes 0-1 and 2-3
 4	(64310) linear addressing enable
 3	(64310) reserved (0)
 2	divide CPU addresses by 4 (chain-4 mode)
 1	use two maps for CPU to access extended video memory (see #P0782,#P0783)
 0	memory-mapping mode
	=0 VGA-compatible
	=1 extended mapping for >= 512K video memory
SeeAlso: #P0762,#P0778,#P0763

Bitfields for Chips&Technologies 64200 "XR0C" Start Address Top register:
Bit(s)	Description	(Table P0778)
 7-1	reserved (0)
 0	high-order bit of display start address when 512K display memory used
SeeAlso: #P0762,#P0777,#P0779

Bitfields for Chips&Technologies 64310 "XR0C" Start Address Top register:
Bit(s)	Description	(Table P0779)
 7	reserved
 6	high map bit 8
 4	low map bit 8
 3-0	high-order bits of display start address
SeeAlso: #P0763,#P0778

Bitfields for Chips&Technologies "XR0D" Auxiliary Offset register:
Bit(s)	Description	(Table P0780)
 7-3	reserved (0)
 2	(64200) reserved (0)
	(64310) msb of row offset register (CRT controller register 13h)
 1-0	(64310) reserved (0)
 1	(64200) LSB of memory offset (CR13) in Chain and Chain-4 modes
 0	(64200) LSB of alternate memory offset (XR1E) in Chain/Chain-4 modes
SeeAlso: #P0762

Bitfields for Chips&Technologies "XR0E" Text Mode Control register:
Bit(s)	Description	(Table P0781)
 7-4	reserved (0)
 3	cursor style (0 = replace, 1 = XOR)
 2	disable cursor blink
 1	reserved (0)
 0	(64200) reserved (0)
	(64310) extended text mode font scrambling in plane 2 enable
SeeAlso: #P0762,#P0763

Bitfields for Chips&Technologies "XR10" Single/Low Map register:
Bit(s)	Description	(Table P0782)
 7-0	(64310) single/low map base address bits 17-10
	(single map mode base address if XR0B bit 1 = 0, dual map mode lower
	  map base address if XR0B bit 1 = 1)
!!!chips\64200.pdf p.80
SeeAlso: #P0762,#P0783,#P0763

Bitfields for Chips&Technologies "XR11" High Map register:
Bit(s)	Description	(Table P0783)
 7-0	(64310) dual map mode high map base address bits 17-10
	  (if XR0B bit 1 = 1)
SeeAlso: #P0762,#P0782

Bitfields for Chips&Technologies "XR14" Emulation Mode register:
Bit(s)	Description	(Table P0784)
 7	enable interrupt output function (=0 tri-state IRQ# line)
 6	(64200) enable VSync status bit at PORT 03BAh/03DAh
	(64310) reserved (0)
 5	vertical retrace status
	=0 PORT 03BAh/03DAh bit 3 is vertical retrace (CGA/EGA/VGA)
	=1 PORT 03BAh/03DAh bit 3 is video active (MDA/Herc)
 4-0	(64310) reserved (0)
 4	(64200) display enable status
	=0 PORT 03BAh/03DAh bit 0 is display enable (CGA/EGA/VGA)
	=1 PORT 03BAh/03DAh bit 0 is HSync (MDA/Herc)
 3-2	(64200) (read-only) Hercules configuration register readback
	  (see PORT 03BFh)
 1-0	(64200) emulation mode
	00 VGA
	01 CGA
	10 MDA/Hercules
	11 EGA
SeeAlso: #P0762,#P0763

Bitfields for Chips&Technologies "XR15" Write Protect register:
Bit(s)	Description	(Table P0785)
 7	write protect AR11 (both bits 7 and 0 must be clear to write AR11)
 6
 5
 4
 3
 2
 1
 0	!!!chips\64200.pdf p.82
SeeAlso: #P0762

Bitfields for Chips&Technologies 64310 "XR16" vertical overflow register:
Bit(s)	Description	(Table P0786)
 7	resrved (0)
 6	line compare bit 10
 5	resrved (0)
 4	vertical blank start bit 10
 3	resrved (0)
 2	vertical sync start bit 10
 1	vertical display enable end bit 10
 0	vertical total bit 10
SeeAlso: #P0763

Bitfields for Chips&Technologies 64310 "XR17" horizontal overflow register:
Bit(s)	Description	(Table P0787)
 7	half line compare bit 8 (bits 7-0 in XR19)
 6	overflow end bits (XR17 bits 5 and 3) enable
 5	horizontal blank end bit 6
 4	horizontal blank start bit 8
 3	horizontal sync end bit 5
 2	horizontal sync start bit 8
 1	horizontal display enable end bit 8
 0	horizontal total bit 8
SeeAlso: #P0763

Bitfields for Chips&Technologies "XR19" alt. horizontal sync start/half-line:
Bit(s)	Description	(Table P0788)
 7-0	(64310) CRT half-line value
SeeAlso: #P0763

Bitfields for Chips&Technologies "XR1A" Alternate Horizontal Sync End register:
Bit(s)	Description	(Table P0789)
 7
 6-5
 4-0
SeeAlso: #P0762,#P0790

Bitfields for Chips&Technologies "XR1D" Alternate Horizontal Blank End reg:
Bit(s)	Description	(Table P0790)
 7
 6-5
 4-0
SeeAlso: #P0762,#P0789

Bitfields for Chips&Technologies "XR1F" Virtual EGA Switch register:
Bit(s)	Description	(Table P0791)
 7
 6-4	reserved (0)
 3-0	virtual EGA switches
SeeAlso: #P0762

Bitfields for Chips&Technologies "XR28" Video Interface register:
Bit(s)	Description	(Table P0792)
 7	reserved
 6	(64310) wide video pixel panning (if bit 4 = 1 and port 3C0h
	  register 10h bit 6 = 1)
	0 = pixel panning controlled by port 3C0h register 13h bits 2-1
	1 = pixel panning controlled by port 3C0h register 13h bits 2-0
 5	interlaced video
 4	(64310) wide video path (doubles values in all horizontal CRTC
	  registers)
	0 = 4-bit video data path
	1 = 8-bit video data path (horizontal pixel panning controlled by
	  bit 6; port 3CEh register 5h bit 5 must be 0)
 3	reserved (0)
 2	shut off video
 1	(64310) BLANK#/display enable select
	0 = BLANK# pin outputs BLANK#
	1 = BLANK# pin outputs display enable
 0	(64310) BLANK#/display enable polarity
	0 = negative polarity
	1 = positive polarity
SeeAlso: #P0762,#P0763

Bitfields for Chips&Technologies 64310 "XR30" clock divide control register:
Bit(s)	Description	(Table P0793)
 7-4	reserved (0)
 3-1	post divisor select
	000 = divide by 1
	001 = divide by 2
	010 = divide by 4
	011 = divide by 8
	100 = divide by 16
	101 = divide by 32
	110-111 = reserved
 0	reference divisor select
	0 = divide by 4
	1 = divide by 1
Note:	Registers XR30-32 are used to program either memory clock or video
	  clock VCO, selected by XR33 bit 5. Data must be written in sequence
	  to all three registers, after which they are transferred to VCO
	  simultaneously.
SeeAlso: #P0763

Bitfields for Chips&Technologies 64310 "XR31" clock M-divisor register:
Bit(s)	Description	(Table P0794)
 7	reserved (0)
 6-0	VCO M-divisor (program value - 2)
Note:	Registers XR30-32 are used to program either memory clock or video
	  clock VCO, selected by XR33 bit 5. Data must be written in sequence
	  to all three registers, after which they are transferred to VCO
	  simultaneously.
SeeAlso: #P0763

Bitfields for Chips&Technologies 64310 "XR32" clock N-divisor register:
Bit(s)	Description	(Table P0795)
 7	reserved (0)
 6-0	VCO N-divisor (program value - 2)
Note:	Registers XR30-32 are used to program either memory clock or video
	  clock VCO, selected by XR33 bit 5. Data must be written in sequence
	  to all three registers, after which they are transferred to VCO
	  simultaneously.
SeeAlso: #P0763

Bitfields for Chips&Technologies 64310 "XR33" clock control register:
Bit(s)	Description	(Table P0796)
 7-6	reserved (0)
 5	clock register program pointer
	0 = VCLK VCO
	1 = MCLK VCO
 4	PCLK equals MCLK instead of VCLK
 3	reserved (0)
 2	OSC enable (if XR01 bit 5 = 1)
 1	MCLK VCO enable (if XR01 bit 4 = 1)
 0	VCLK VCO enable (if XR01 bit 4 = 1)
SeeAlso: #P0763

Bitfields for Chips&Technologies 64310 "XR3A" color key compare data 0:
Bit(s)	Description	(Table P0797)
 7-0	color compare data 0
	(Compared to lowest 8 bits of 64310 memory data, masked with XR3D. If
	  match occurs and XR06 bit 4 = 1, external video is sent to screen.
	  Color comparison occurs before RAMDAC. Palette LUT index is used in
	  4BPP and 8BPP modes.)
SeeAlso: #P0763

Bitfields for Chips&Technologies 64310 "XR3B" color key compare data 1:
Bit(s)	Description	(Table P0798)
 7-0	color compare data 1
	(Compared to bits 15-8 of 64310 memory data, masked with XR3E. If
	  match occurs and XR06 bit 4 = 1, external video is sent to screen.
	  This register should be masked in 4BPP and 8BPP modes by setting
	  XR3E to FFh.)
SeeAlso: #P0763

Bitfields for Chips&Technologies 64200 "XR3C" Serial/Row Count register:
Bit(s)	Description	(Table P0799)
 7-6	reserved (0)
 5-3	row count (number of transfer cycles)
	000 = 64
	001 = 128
	010 = 256
	011 = 512
	1x0 = 1024
	1x1 = 2048
 2-0	serial count (same as for bits 5-3, but in units of serial clocks)
SeeAlso: #P0762,#P0801,#P0768

Bitfields for Chips&Technologies 64310 "XR3C" color key compare data 2:
Bit(s)	Description	(Table P0800)
 7-0	color compare data 2
	(Compared to bits 23-16 of 64310 memory data, masked with XR3F. If
	  match occurs and XR06 bit 4 = 1, external video is sent to screen.
	  This register should only be used in 24BPP modes, and masked in
	  other modes by setting XR3F to FFh.)
SeeAlso: #P0763,#P0802

Bitfields for Chips&Technologies 64200 "XR3D" Multiplexer Mode register:
Bit(s)	Description	(Table P0801)
 7-5	reserved
 4
 3
 2-0	multiplexer mode
SeeAlso: #P0762,#P0799,#P0768

Bitfields for Chips&Technologies 64310 "XR3D" color key compare mask 0:
Bit(s)	Description	(Table P0802)
 7-0	color compare mask 0 (masks XR3A)
	0 = bit compared
	1 = bit masked from comparison
SeeAlso: #P0763,#P0800,#P0803

Bitfields for Chips&Technologies 64310 "XR3E" color key compare mask 1:
Bit(s)	Description	(Table P0803)
 7-0	color compare mask 1 (masks XR3B)
	0 = bit compared
	1 = bit masked from comparison
SeeAlso: #P0763,#P0802,#P0804

Bitfields for Chips&Technologies 64310 "XR3F" color key compare mask 2:
Bit(s)	Description	(Table P0804)
 7-0	color compare mask 2 (masks XR3C)
	0 = bit compared
	1 = bit masked from comparison
SeeAlso: #P0763,#P0802,#P0803

Bitfields for Chips&Technologies 64310 "XR40" BitBlt config register:
Bit(s)	Description	(Table P0805)
 7-2	reserved (0)
 1-0	BitBlt draw mode
	00 = reserved
	01 = 8bpp
	10 = 16bpp
	11 = reserved
	(24bpp handled in 8bpp mode; no nibble mode for 4bpp)
SeeAlso: #P0763

Bitfields for Chips&Technologies 64310 "XR52" refresh control register:
Bit(s)	Description	(Table P0806)
 7-3	reserved (0)
 2-0	VGA refresh cycles per scan line
	000 = default
	001-101 = 1-5 refresh cycles
	110-111 = illegal
SeeAlso: #P0763

Bitfields for Chips&Technologies "XR70" Setup/Disable Control register:
Bit(s)	Description	(Table P0807)
 7
 6-0	reserved (0)
SeeAlso: #P0762

Bitfields for Chips&Technologies 64310 "XR71" GPIO control register:
Bit(s)	Description	(Table P0808)
 7-5	GPOE
	0 = respective GPIO pin is input
	1 = respective GPIO pin is output
	(if standard feature connector is enabled (XR73 bit 5 = 1), GPIO pin 5
	  becomes an alternate fixed function input (ECLK#) and bit 5 must be
	  set to 0)
	(if external clock is selected (XR01 bit 4 = 0), bits 7-6 have no
	  effect and GPIO pins 7-6 become CLKSEL1-0 and output contents of
	  port 3CCh bits 3-2)
 4	reserved (0)
 3-2	GPOE
	0 = respective GPIO pin is input
	1 = respective GPIO pin is output
	(if standard feature connector is enabled (XR73 bit 5 = 1), GPIO pins
	  3 and 2 become alternate fixed function inputs (EVIDEO#, ESYNC#) and
	  bits 3-2 must be set to 0)
 1-0	reserved (0)
SeeAlso: #P0763

Bitfields for Chips&Technologies 64310 "XR72" GPIO data register:
Bit(s)	Description	(Table P0809)
 7-5	GPIO (input from/output to respective GPIO pin)
	(if standard feature connector is enabled (XR73 bit 5 = 1), GPIO pin 5
	  becomes an alternate fixed function input (ECLK#))
	(if external clock is selected (XR01 bit 4 = 0), GPIO pins 7-6 become
	  CLKSEL1-0 and output contents of port 3CCh bits 3-2)
 4	reserved (0)
 3-2	GPIO (input from/output to respective GPIO pin)
	(if standard feature connector is enabled (XR73 bit 5 = 1), GPIO pins
	  3 and 2 become alternate fixed function inputs (EVIDEO#, ESYNC#))
 1-0	reserved (0)
SeeAlso: #P0763

Bitfields for Chips&Technologies 64310 "XR73" misc control register:
Bit(s)	Description	(Table P0810)
 7	ROMCS# write access enable
 6	external color key enable
 5	standard feature connector enable (must be set before XR06 bit 0)
 4	reserved (0)
 3	VSYNC control
	0 = CRTC VSYNC is output on VSYNC pin 126
	1 = bit 2 is output on VSYNC pin 126
 2	VSYNC data (if bit 3 = 1, this bit will be output on VSYNC pin)
 1	HSYNC control
	0 = CRTC HSYNC is output on HSYNC pin 125
	1 = bit 0 is output on HSYNC pin 125
 0	HSYNC data (if bit 1 = 1, this bit will be output on HSYNC pin)
SeeAlso: #P0763

Bitfields for Chips&Technologies 64310 "XR74" configuration register 2:
Bit(s)	Description	(Table P0811)
 7-0	(64300) ???
	(64310) reserved (0)
SeeAlso: #P0763

Bitfields for Chips&Technologies 64310 "XR7A" test index register:
Bit(s)	Description	(Table P0812)
 7-0	test index (select XR7B function)
	00h = reserved
	01h = CRC signature analysis
	02h-FFh = reserved
SeeAlso: #P0763

Bitfields for Chips&Technologies 64310 "XR7B" test control register:
Bit(s)	Description	(Table P0813)
---XR7A = 01h---
 7	CRC status (read-only)
	0 = CRC ARM=0 or CRC data is being generated (CRC data should not be
	  read)
	1 = CRC ARM=1 and CRC data is ready
 6	CRC arm
	1 = arm CRC generation to start after the next VSYNC and stop after the
	  VSYNC following that (should not be set to 0 until entire CRC value
	  is read)
 5-4	CRC data select (select data to be read from XR7C)
	00 = CRC bit 7-0
	01 = CRC bits 15-8
	10 = 0 and CRC bits 22-16
	11 = 00h
 3-2	CRC qualification
	00 = take all data
	01 = take data when not blank (DE + overscan)
	10 = take data when DE is active
	11 = take data in PC Video window only
 1-0	video data select
	00 = red video data before DAC output
	01 = green video data before DAC output
	10 = blue video data before DAC output
	11 = control data (VSYNC, HSYNC, blank, internal display enable,
	  0, 0, 0, 0)
SeeAlso: #P0763,#P0812

Bitfields for Chips&Technologies 64310 "XR7C" test data register:
Bit(s)	Description	(Table P0814)
---XR7A = 01h---
 7-0	CRC data (read-only)
SeeAlso: #P0763,#P0812

Bitfields for Chips&Technologies "XR7E" CGA Color Select register:
Bit(s)	Description	(Table P0815)
 7-6	reserved
 5
 4
 3-0
Note:	this is a mirror of the register accessed via PORT 03D9h, which is
	  always visible, while PORT 03D9h is only visible in CGA emulation
SeeAlso: #P0762,PORT 03D9h

Bitfields for Chips&Technologies "XR7F" Diagnostic register:
Bit(s)	Description	(Table P0816)
 7	special test function (should remain cleared)
 6	enable test function in bits 5-2
 5-2	test function
 1	tri-state output pins: !!!
 0	tri-state output pins: !!! chips\64200.pdf p.90
SeeAlso: #P0762
----------P03D803DF--------------------------
PORT 03D8-03DF - COLOR VIDEO - CRT MODE AND STATUS REGISTERS

03D8  RW  CGA mode control register  (except PCjr) (see #P0817)
	cannot be found on native color EGA, color VGA, but on most clones
03D9  RW  CGA palette register (see #P0819)
	(MCGA) CGA border control register
	Cannot be found on native EGA, VGA (without translation ROM) but
	  only most clones. Read access on Genoa SuperEGA is 'reset'???
03DA  R-  CGA status register (see #P0818)
	color EGA/VGA: input status 1 register
03DA  -W  color EGA/color VGA feature control register (see #P0820)
	(at PORT 03BAh w in mono mode, VGA: 3CAh r)
03DA  -W  HZ309 (MDA/HGC/CGA clone) card from in Heath/Zenith HZ150 PC
	bit7-1=0: unknown, zero is default and known to function
		   properly at least in CGA modes.
	bit 0 = 1 override 3x8h bit3 control register that switches
		   CRT beam off if bit3 is cleared. So screens always
		   stays on.
	bit 0 = 0 3x8h bit3 indicates if CRT beam is on or off.
		   No more info available. Might conflict with EGA/VGA.
03DB  rW  clear light pen latch	(not MCGA)
		  (R/W only with Genoa SuperEGA)
03DC  RW  (not MCGA) preset light pen latch
03DC  -W  (CGA) set light pen latch
03DD  -W  (MCGA)  Extended mode control register
	  (Plantronics & Genoa SuperEGA: Plantronics ColorPlus control,
		      compatible with MCGA???)
	(default is 00h, in mode 13h: 04h)
	bit7 =1: DAC active, cannot be read
	     =0: DAC not active, read allowed
	bit6-3 : reserved
	bit2 =1: videomode 13h with 256 colors active
	bit1	: reserved
	bit0 =0: reserved
03DE  --  (MCGA) reserved
03DE  -W  (AT&T & color ET4000 in AT&T compatibility mode & C&T 82C426)
	  AT&T mode control register (see #P0821)
	(register enabled in ET4000, if bit7=1 in CRTC 3D4h/34h.)
03DF  --  (MCGA) reserved
03DF  ?W  CRT/CPU page register	 (PCjr only)

Bitfields for CGA/Hercules mode control register:
Bit(s)	Description	(Table P0817)
 7-0	=A0h color ET4000: second part of 'key', see Hercules compatibility
	  register (see PORT 03BFh) for details. For resetting the key, e.g.
	  write 01h to PORT 03BFh and 29h to PORT 03D8h.
 7	(Hercules) page select
	=0 B0000h
	=1 B8000h
 6	color ET4000 only, read-only: report status of bit 1 (enable 2nd page)
	  of hercules compatibility register (see PORT 03BFh)
 5	=1  blink enabled instead of foreground high-int.
 4	=1  640*200 graphics mode (CGA)
 3	=1  video enabled (HZ309, see PORT 03DAh bit 0)
 2	=1  monochrome signal
		(MCGA) in mode 6 and 11h color comes from palette
		  regs 00 (black) and 07 (white), and can be changed there.
 1	=0  text mode
	=1  320*200 graphics mode
 0	text columns (0 = 40*25 text mode, 1 = 80*25 text mode)
SeeAlso: #P0818

Bitfields for CGA status register:
Bit(s)	Description	(Table P0818)
 7-6	not used
 7	(C&T Wingine) vertical sync in progress (if enabled by XR14)
 5-4	color EGA, color ET4000, C&T: diagnose video display feedback, select
	  from color plane enable
 3	in vertical retrace
	(C&T Wingine) video active (retrace/video selected by XR14)
 2	(CGA,color EGA) light pen switch is off
	(MCGA,color ET4000) reserved (0)
	(VGA) reserved (1)
 1	(CGA,color EGA) positive edge from light pen has set trigger
	(VGA,MCGA,color ET4000) reserved (0)
 0	horizontal retrace in progress
	=0  do not use memory
	=1  memory access without interfering with display
	    (VGA,Genoa SuperEGA) horizontal or vertical retrace
	(C&T Wingine) display enabled (retrace/DE selected by XR14)
SeeAlso: #P0817,#P0819,#P0762

Bitfields for CGA palette register:
Bit(s)	Description	(Table P0819)
 7-6	not used
 5	=0 active 320x200x4 color set: red, green brown
	=1 active 320x200x4 color set: cyan, magenta, white
 4	intense colors in graphics, background colors text
 3	intense border in 40*25, intense background in 320*200, intense
	  foreground in 640*200
 2	red border in 40*25, red background in 320*200,	red foreground in
	  640*200
 1	green border in 40*25, green background in 320*200, green foreground
	  in 640*200
 0	blue border in 40*25, blue background in 320*200, blue foreground in
	   640*200
SeeAlso: #P0817,#P0818

Bitfields for color EGA/VGA feature control register:
Bit(s)	Description	(Table P0820)
 7	ET4000 only: enable NMI generation ('key' protected)
 6-4	not used
 3	(VGA) 0 = normal vsync, 1 = vsync OR display enable
 2	reserved (0)
	(C&T Wingine) disable 16-bit operations
 1	(EGA,ET4000,Wingine) FEAT1 control bit1 (pin17 feature connector)
	(VGA) reserved (0)
 0	(EGA,ET4000,Wingine) FEAT0 control bit0 (pin19 feature connector)
	(VGA) reserved (0)
SeeAlso: #P0818

Bitfields for AT&T mode control register:
Bit(s)	Description	(Table P0821)
 7	reserved
 6	underline color attribute enable
	ET4000: enabled, if bit6=1 in CRTC 3D4h/34h.
 5	reserved
 4	reserved
 3	alternate page select (=1: 2nd 16KB page, with bit0=0)
 2	alternate font select (0=default font block)
 1	reserved
 0	double scan line mode (0=IBM 200, 1=AT&T 400 line graphics)
	(ET4000) enabled, if bit7-6=11b in CRTC 3D4h/34h.
----------P03E003E1--------------------------
PORT 03E0-03E1 - OPTi 82C824 - CardBus Bridge registers
Range:	PORT 03E0h or PORT 03E2h
SeeAlso: PORT 03E2h"CardBus"

03E0  ?W  index for data register
03E1  RW  CardBus registers
--------X-P03E003E1--------------------------
PORT 03E0-03E1 - Cirrus Logic CL-PD6710/6722/6729 - PC-CARD HOST ADAPTER
Notes:	the CL-PD6729 has compatible registers, but the port address
	  is set via the PCI configuration space (two consecutive ports
	  starting at Base Address 0)
	the CL-PD6832 supports a superset of this register set
SeeAlso: PORT 03E0h"CardBus"

03E0  ?W  index for data register (see #P0822)
03E1  RW  register data

Bitfields for Cirrus Logic CL-PD6710/6722 index register:
Bit(s)	Description	(Table P0822)
 7	device number (when dual CL-PD67xx's are used)
	(CL-PD6729) reserved
 6	socket number (CL-PD6722 dual-socket adapter only)
 5-0	register index (see #P0823)

(Table P0823)
Values for Cirrus Logic CL-PD6710/6722 register number:
 00h	chip revision (affects both sockets) (see #P0824)
 01h	interface status (see #P0825)
 02h	power control (see #P0826)
 03h	interrupt and general control (see #P0827)
 04h	card status change (see #P0828)
 05h	management interrupt configuration (see #P0829)
 06h	mapping enable (see #P0830)
 07h	I/O window control (see #P0831)
 08h	system I/O map 0 start address low
 09h	system I/O map 0 start address high
 0Ah	system I/O map 0 end address low
 0Bh	system I/O map 0 end address high
 0Ch	system I/O map 1 start address low
 0Dh	system I/O map 1 start address high
 0Eh	system I/O map 1 end address low
 0Fh	system I/O map 1 end address high
 10h	system memory map 0 start address low (address bits 19-12)
 11h	system memory map 0 start address high (see #P0832)
 12h	system memory map 0 end address low (address bits 19-12)
 13h	system memory map 0 end address high (see #P0833)
 14h	card memory map 0 offset address low (address bits 19-12)
 15h	card memory map 0 offset address high (see #P0834)
 16h	misc control 1 (see #P0835)
 17h	FIFO control (see #P0836)
 18h	system memory map 1 start address low (address bits 19-12)
 19h	system memory map 1 start address high (see #P0832)
 1Ah	system memory map 1 end address low (address bits 19-12)
 1Bh	system memory map 1 end address high (see #P0833)
 1Ch	card memory map 1 offset address low (address bits 19-12)
 1Dh	card memory map 1 offset address high (see #P0834)
 1Eh	misc control 2 (affects both sockets) (see #P0837)
 1Fh	chip information (affects both sockets) (see #P0838)
 20h	system memory map 2 start address low (address bits 19-12)
 21h	system memory map 2 start address high (see #P0832)
 22h	system memory map 2 end address low (address bits 19-12)
 23h	system memory map 2 end address high (see #P0833)
 24h	card memory map 2 offset address low (address bits 19-12)
 25h	card memory map 2 offset address high (see #P0834)
 26h	ATA control (see #P0839)
 27h	scratchpad
 28h	system memory map 3 start address low (address bits 19-12)
 29h	system memory map 3 start address high (see #P0832)
 2Ah	system memory map 3 end address low (address bits 19-12)
 2Bh	system memory map 3 end address high (see #P0833)
 2Ch	card memory map 3 offset address low (address bits 19-12)
 2Dh	card memory map 3 offset address high (see #P0834)
 2Eh	(CL-PD6722/6729) extended index for extended data register (see #P0842)
 2Fh	extended data
 30h	system memory map 4 start address low (address bits 19-12)
 31h	system memory map 4 start address high (see #P0832)
 32h	system memory map 4 end address low (address bits 19-12)
 33h	system memory map 4 end address high (see #P0833)
 34h	card memory map 4 offset address low (address bits 19-12)
 35h	card memory map 4 offset address high (see #P0834)
 36h	card I/O map 0 offset address low (see #P0840)
 37h	card I/O map 0 offset address high (address bits 15-8)
 38h	card I/O map 1 offset address low (see #P0840)
 39h	card I/O map 1 offset address high (address bits 15-8)
 3Ah	setup timing 0 (see #P0841)
 3Bh	command timing 0 (see #P0841)
 3Ch	recovery timing 0 (see #P0841)
 3Dh	setup timing 1 (see #P0841)
 3Eh	command timing 1 (see #P0841)
 3Fh	recovery timing 1 (see #P0841)
SeeAlso: #P0822

Bitfields for Cirrus Logic CL-PD6710/6722/6729 chip revision:
Bit(s)	Description	(Table P0824)
 7-6	interface ID (read-only)
	00 = I/O only
	01 = memory only
	10 = I/O and memory
	11 = reserved
 5-4	reserved (read-only)
 3-0	revision (read-only)
SeeAlso: #P0823

Bitfields for Cirrus Logic CL-PD6710/6722/6729 interface status:
Bit(s)	Description	(Table P0825)
 7	-VPP_VALID pin status
	0 = -VPP_VALID high
	1 = -VPP_VALID low (asserted)
	(CL-PD6729) reserved (1)
 6	card power on
 5	(memory card) ready
 4	(memory card) write protect
 3-2	card detect status
	00 = no card or card not fully inserted
	01 = card not fully inserted
	10 = card not fully inserted
	11 = card fully inserted
 1-0	(memory card) battery voltage
	00 = card data lost
	01 = battery low warning
	10 = card data lost
	11 = battery/data ok
	(I/O card) status change (ignore bit 1)
Note:	this register is read-only
SeeAlso: #P0823

Bitfields for Cirrus Logic CL-PD6710/6722/6729 power control:
Bit(s)	Description	(Table P0826)
 7	card enable (if card present (register 01h bits 3-2 = 11) and power
	  supplied (bit 4 = 1))
 6	reserved (82365SL compatibility)
 5	auto-power enable
 4	Vcc power on (if bit 5 = 0, or bit 5 = 1 and register 01h
	  bits 3-2 = 11) (voltage selected by register 16h bit 1)
 3-2	reserved (82365SL compatibility)
 1-0	Vpp1 power
	00 = zero V
	01 = selected card Vcc
	10 = +12V
	11 = zero V
SeeAlso: #P0823

Bitfields for Cirrus Logic CL-PD6710/6722/6729 interrupt and general control:
Bit(s)	Description	(Table P0827)
 7	(I/O card) ring indicate enable
 6	card reset signal
	0 = active
	1 = inactive
 5	card interface mode
	0 = memory card
	1 = I/O card
 4	management interrupt
	0 = selected by register 05h bits 7-4
	1 = redirected to -INTR line
	    (CL-PD6729) reserved
 3-0	card IRQ select
	0000 = IRQ disabled
	0001-0010 = reserved
	0011-0101 = IRQ3-IRQ5 (INTA#-INTC# on CL-PD6729)
	0110 = reserved
	0111 = IRQ7 (INTD# on CL-PD6729)
	1000 = reserved
	1001 = IRQ9 (may be used as ISA bus DACK on CL-PD6722)
	1010 = IRQ10 (may be used as ISA bus DRQ on CL-PD6722)
	1011 = IRQ11
	1100 = IRQ12 (may be used for LED on CL-PD6710/6722)
	1101 = reserved
	1110 = IRQ14 (may be used as external clock input on CL-PD6729)
	1111 = IRQ15 (may be used as ring indicate output)
SeeAlso: #P0823

Bitfields for Cirrus Logic CL-PD6710/6722/6729 card status change:
Bit(s)	Description	(Table P0828)
 7-4	reserved (0)
 3	card detect change
 2	ready change (always 0 for I/O card)
 1	battery warning change (ignore on I/O card)
 0	(memory card) battery dead change
	(I/O card) status change
Note:	reading this read-only register resets all bits to 0
SeeAlso: #P0823

Bitfields for Cirrus Logic CL-PD6710/6722/6729 management interrupt config:
Bit(s)	Description	(Table P0829)
 7-4	management IRQ
	0000 = IRQ disabled
	0001-0010 = reserved
	0011-0101 = IRQ3-IRQ5 (INTA#-INTC# on CL-PD6729)
	0110 = reserved
	0111 = IRQ7 (INTD# on CL-PD6729)
	1000 = reserved
	1001 = IRQ9 (on CL-PD6722 may be used as ISA bus DACK)
	1010 = IRQ10 (on CL-PD6722 may be used as ISA bus DRQ)
	1011 = IRQ11
	1100 = IRQ12 (on CL-PD6710/6722 may be used for LED)
	1101 = reserved
	1110 = IRQ14 (on CL-PD6729 may be used as external clock input)
	1111 = IRQ15 (may be used as ring indicate output)
 3	management interrupt on card detect change enable
 2	management interrupt on ready change enable
 1	management interrupt on battery warning change enable (ignored on
	  I/O card)
 0	(memory card) management interrupt on battery dead change enable
	(I/O card) management interrupt on status change enable
SeeAlso: #P0823

Bitfields for Cirrus Logic CL-PD6710/6722/6729 mapping enable:
Bit(s)	Description	(Table P0830)
 7	I/O map 1 enable
 6	I/O map 0 enable
 5	reserved (82365SL compatibility: MEMCS16 full decode)
 4	memory map 4 enable
 3	memory map 3 enable
 2	memory map 2 enable
 1	memory map 1 enable
 0	memory map 0 enable
SeeAlso: #P0823

Bitfields for Cirrus Logic CL-PD6710/6722/6729 I/O window control:
Bit(s)	Description	(Table P0831)
 7	timing register select 1
	0 = accesses made with timings specified in timer set 0
	1 = accesses made with timings specified in timer set 1
 6	reserved (82365SL compatibility)
 5	I/O window 1 auto-size enable (size determined by -IOIS16 signal) (set
	  for proper ATA operation)
 4	I/O window 1 size (if bit 5 = 0)
	0 = 8-bit data path
	1 = 16-bit data path
 3	timing register select 0 (same values as bit 7)
 2	reserved (82365SL compatibility)
 1	I/O window 0 auto-size enable (size determined by -IOIS16 signal)
 0	I/O window 0 size (if bit 1 = 0) (same values as bit 4)
SeeAlso: #P0823

Bitfields for Cirrus Logic CL-PD6710/6722/6729 system memory map start high:
Bit(s)	Description	(Table P0832)
 7	window data size
	0 = 8-bit
	1 = 16-bit
 6	reserved (82365SL compatibility)
 5-4	scratchpad
 3-0	start address bits 23-20
SeeAlso: #P0823

Bitfields for Cirrus Logic CL-PD6710/6722/6729 system memory map end high:
Bit(s)	Description	(Table P0833)
 7-6	card timer
	00 = timer set 0
	01-11 = timer set 1
 5-4	scratchpad
 3-0	end address bits 23-20
SeeAlso: #P0823

Bitfields for Cirrus Logic CL-PD6710/6722/6729 card memory map offset high:
Bit(s)	Description	(Table P0834)
 7	window write protect enable
 6	-REG active for window accesses
 5-0	offset address bits 25-20
SeeAlso: #P0823

Bitfields for Cirrus Logic CL-PD6710/6722/6729 misc control 1:
Bit(s)	Description	(Table P0835)
 7	INPACK enable (no effect on CL-PD6729)
 6-5	scratchpad
 4	speaker enable
 3	system IRQ triggering
	0 = level
	1 = pulse
 2	management interrupt triggering (as for bit 3)
 1	Vcc voltage
	0 = 5V
	1 = 3.3V
 0	(CL-PD6710) voltage detect
	0 = 3.3V card detected
	0 = old or 5V card detected
	(CL-PD6722) reserved (A_GPSTB/B_GPSTB level read on some versions)
	(CL-PD6729) multimedia enable (tri-state socket address lines A25-4)
	  (register 2Fh extended index 25h bit 7 must be 1)
SeeAlso: #P0823

Bitfields for Cirrus Logic CL-PD6710/6722/6729 FIFO control:
Bit(s)	Description	(Table P0836)
 7	(read) FIFO status
	0 = data in FIFO
	1 = FIFO empty
	(write) FIFO flush
	0 = no operation
	1 = flush FIFO
 6-0	scratchpad
SeeAlso: #P0823

Bitfields for Cirrus Logic CL-PD6710/6722/6729 misc control 2:
Bit(s)	Description	(Table P0837)
 7	IRQ15 connected to ring indicate pin
 6	(CL-PD6710/6729) reserved
	(CL-PD6722) DMA system enable
 5	floppy change bit compatibility enable (tri-state bit 7 of socket I/O
	  at addresses 3F7h and 377h)
	(CL-PD6729) reserved
 4	drive LED enable (should be set to 0 in memory card interface mode)
	(CL-PD6729) reserved
 3	core voltage
	0 = 3.3V
	1 = 5V
 2	suspend mode enable
 1	low-power dynamic mode
	0 = clock always runs
	1 = stop clock when possible (normal operation)
 0	frequency synthesizer bypass
	0 = internal clock = CLK input * 7/4 (normal operation)
	1 = internal clock = CLK input
	(CL-PD6729) external clock enable
	0 = internal clock = PCI_CLK input / 2
	1 = internal clock = IRQ14/EXT_CLK / 2
SeeAlso: #P0823

Bitfields for Cirrus Logic CL-PD6710/6722/6729 chip information:
Bit(s)	Description	(Table P0838)
 7-6	Cirrus Logic host-adapter identification (read-only)
	00 = second read after I/O write to this register
	11 = first read after I/O write to this register
 5-0	(CL-PD6729) CL-PD6729 revision (read-only)
	21h = register 2Fh extended indexes 34h-3Bh indicate chip revision and
	  features
 5	(CL-PD6710/6722) CL-PD67xx sockets (read-only)
	0 = single (CL-PD6710)
	1 = dual (CL-PD6722)
 4-1	(CL-PD6710/6722) CL-PD67xx revision (read-only)
 0	(CL-PD6710) reserved (0) (read-only)
	(CL-PD6722) reserved (1) (read-only)
SeeAlso: #P0823

Bitfields for Cirrus Logic CL-PD6710/6722/6729 ATA control:
Bit(s)	Description	(Table P0839)
 7	(ATA mode) A25 / CSEL pin value (vendor specific)
 6	(ATA mode) A24 / M/S pin value (vendor specific)
 5	(ATA mode) A23 / VU pin value (vendor specific)
 4	(ATA mode) A22 pin value (vendor specific)
 3	(ATA mode) A21 pin value (vendor specific)
 2	scratchpad
 1	speaker is LED input (if register 1Eh bit 4 = 1) (should be set to 0
	  in memory card interface mode)
	(CL-PD6729) speaker is LED input (if register 2Fh extended index 03h
	  bit 4 = 1) (should be set to 0 in memory card interface mode)
 0	ATA mode enable
SeeAlso: #P0823

Bitfields for Cirrus Logic CL-PD6710/6722/6729 card I/O map offset address low:
Bit(s)	Description	(Table P0840)
 7-1	offset address bits 7-1
 0	reserved (must be 0)
SeeAlso: #P0823

Bitfields for Cirrus Logic CL-PD6710/6722/6729 setup/command/recovery timing:
Bit(s)	Description	(Table P0841)
 7-6	prescaler
	00 = 1
	01 = 16
	10 = 256
	11 = (CL-PD6710/6722) 8192
	     (CL-PD6729) 4096
 5-0	multiplier value
Notes:	internal clock cycles = (prescalar * multiplier) + 1
	changes take effect immediately and should only be changed when FIFO
	  is empty (register 17h bit 7 = 1)
SeeAlso: #P0823

(Table P0842)
Values for Cirrus Logic CL-PD6722/6729 extended index:
 00h	scratchpad
 01h	(CL-PD6722) data mask 0 (see #P0843)
	(CL-PD6729) reserved
 02h	(CL-PD6722) data mask 1 (see #P0843)
	(CL-PD6729) reserved
 03h	extension control 1 (see #P0844)
 04h	(CL-PD6722) maximum DMA acknowledge delay (see #P0845)
	(CL-PD6729) reserved
 05h-09h (CL-PD6722) reserved
 05h	(CL-PD6729) system memory map 0 upper address (start/end address
	  bits 31-24)
 06h	(CL-PD6729) system memory map 1 upper address (start/end address
	  bits 31-24)
 07h	(CL-PD6729) system memory map 2 upper address (start/end address
	  bits 31-24)
 08h	(CL-PD6729) system memory map 3 upper address (start/end address
	  bits 31-24)
 09h	(CL-PD6729) system memory map 4 upper address (start/end address
	  bits 31-24)
 0Ah	(CL-PD6722) external data (see #P0846)
	(CL-PD6729 socket B) external data (see #P0847)
 0Bh	(CL-PD6722) extension control 2 (see #P0848)
 25h	(CL-PD6729) misc. control 3 (see #P0849)
---CL-PD6729 socket A---
 34h	mask revision byte (read-only)
 35h	product ID byte (read-only) (see #P0850)
 36h	device capability byte A (read-only) (see #P0851)
 37h	device capability byte B (read-only) (see #P0852)
 38h	device implementation byte A (see #P0853)
 39h	device implementation byte B (see #P0854)
 3Ah	device implementation byte C (see #P0855)
 3Bh	device implementation byte D (see #P0856)
SeeAlso: #P0823

Bitfields for Cirrus Logic CL-PD6722 data mask:
Bit(s)	Description	(Table P0843)
 7-0	data mask for corresponding I/O map
	0 = no mask
	1 = mask corresponding bit from data
SeeAlso: #P0842

Bitfields for Cirrus Logic CL-PD6722/6729 extension control 1:
Bit(s)	Description	(Table P0844)
 7-6	(CL-PD6722) DMA mode
	00 = disabled
	01 = enabled, INPACK used as active-low DREQ input
	10 = enabled, WP/IOIS16 used as active-low DREQ input
	11 = enabled, BVD2/SPKR used as active-low DREQ input
	(CL-PD6729) reserved
 5	pull-ups disable
 4-3	(CL-PD6722) reserved
 4	(CL-PD6729) management IRQ output invert
	0 = management IRQ is active-high
	1 = management IRQ is active-low and open-drain
 3	(CL-PD6729) card IRQ output invert
	0 = card IRQ is active-high
	1 = card IRQ is active-low and open-drain
 2	LED activity enable
 1	auto power clear disable (register 02h bit 4 is not cleared when card
	  is removed)
 0	Vcc power bit (register 02h bit 4) lock enable
SeeAlso: #P0842

Bitfields for Cirrus Logic CL-PD6722 maximum DMA acknowledge delay:
Bit(s)	Description	(Table P0845)
 7-0	maximum DMA acknowledge delay
	10h = 14 clocks
	20h = 10 clocks
	30h = 18 clocks
	40h = 8 clocks
	50h = 16 clocks
	60h = 12 clocks
	80h = 7 clocks
	90h = 15 clocks
	A0h = 11 clocks
	B0h = 19 clocks
	C0h = 9 clocks
	D0h = 17 clocks
	E0h = 13 clocks
SeeAlso: #P0842

Bitfields for Cirrus Logic CL-PD6722 external data (socket A):
Bit(s)	Description	(Table P0846)
--- register 2Fh extended index 0Bh bits 4-3 = 00 ---
 7-0	(socket A) scratchpad
 7-4	(socket B) scratchpad
 3	(socket B) socket B VS2# input level (read-only)
 2	(socket B) socket B VS1# input level (read-only)
 1	(socket B) socket A VS2# input level (read-only)
 0	(socket B) socket A VS1# input level (read-only)
--- register 2Fh extended index 0Bh bits 4-3 = 01 ---
 7-0	external read port
--- register 2Fh extended index 0Bh bits 4-3 = 10 ---
 7-0	external write port (read returns value written)
--- register 2Fh extended index 0Bh bits 4-3 = 10 ---
 7-0	reserved
------
Note:	for software compatibility this register should only be used as write
	  port, and bits 7-4 should be ignored
SeeAlso: #P0842

Bitfields for Cirrus Logic CL-PD6729 external data:
Bit(s)	Description	(Table P0847)
 7-4	reserved
 3	socket B VS2# input level (read-only)
 2	socket B VS1# input level (read-only)
 1	socket A VS2# input level (read-only)
 0	socket A VS1# input level (read-only)
SeeAlso: #P0842

Bitfields for Cirrus Logic CL-PD6722 extension control 2:
Bit(s)	Description	(Table P0848)
 7-6	reserved (0)
 5	GPSTB output
	0 = active-low
	1 = active-high
 4	GPSTB on IOW
	0 = A_GPSTB used as voltage sense
	1 = A_GPSTB used to strobe I/O writes on SD15-8
 3	GPSTB on IOR
	0 = B_GPSTB used as voltage sense
	1 = B_GPSTB used to strobe I/O writes on SD15-8
 2	totem-pole GPSTB
	0 = GPSTB outputs are open-collector
	1 = GPSTB outputs are totem-pole (high level driven to +5V pin level
	  instead of high-impedance)
 1-0	reserved (0)
SeeAlso: #P0842

Bitfields for Cirrus Logic CL-PD6729 misc. control 3:
Bit(s)	Description	(Table P0849)
 7	multimedia arm enable
 6	multimedia expand enable (allows 24-bit video)
 5-0	reserved
SeeAlso: #P0842

Bitfields for Cirrus Logic CL-PD6729 product ID byte:
Bit(s)	Description	(Table P0850)
 7-4	family code (read-only)
	2h = CL-PD6729 family
 3-0	product code (read-only)
--- family code = 2h ---
	0h = CL-PD6729 PCI/PCMCIA controller, dual isolated sockets, 208 pin
	1h-Fh = reserved
SeeAlso: #P0842

Bitfields for Cirrus Logic CL-PD6729 device capability byte A:
Bit(s)	Description	(Table P0851)
 7	output LEDs (read-only)
	0 = single LED
	1 = LED per socket
 6	reserved (read-only)
 5	general purpose strobe (GPSTB) capable (read-only)
 4	reserved (read-only)
 3	DMA slave (read-only)
 2	IDE interface (read-only)
 1-0	number of sockets (read-only)
	00 = two
Note:	CL-PD6729 does not support GPSTB even if bit 5 = 1
SeeAlso: #P0842

Bitfields for Cirrus Logic CL-PD6729 device capability byte B:
Bit(s)	Description	(Table P0852)
 7	extended definitions (read-only)
	0 = not available (device capability and implementation definitions
	  stop to extended register 3Bh)
 6-3	reserved (read-only)
 2	CLKRUN support (read-only)
 1	LOCK# support (read-only)
 0	CardBus transfer cycle support (read-only)
SeeAlso: #P0842

Bitfields for Cirrus Logic CL-PD6729 device implementation byte A:
Bit(s)	Description	(Table P0853)
 7	RI_OUT wired to ring indicate circuitry
 6	hardware suspend wired to power management circuitry
 5	GBSTB B wired
 4	GBSTB A wired
 3	VS1/VS2 wired
 2	slave DMA wired
 1	sockets present 1
 0	sockets present 0
SeeAlso: #P0842

Bitfields for Cirrus Logic CL-PD6729 device implementation byte B:
Bit(s)	Description	(Table P0854)
 7	reserved
 6	radio frequency rated sockets
 5	VPP_VCC 1A capable
 4	VPP 12V support
 3	x.xV capable
 2	y.yV capable
 1	5.0V capable
 0	3.3V capable
SeeAlso: #P0842

Bitfields for Cirrus Logic CL-PD6729 device implementation byte C:
Bit(s)	Description	(Table P0855)
 7-5	reserved
 4	socket B wired for ZV operation
 3	socket A wired for ZV operation
 2	speaker wired to SPKR_OUT
 1	separate status LED for each socket
 0	status LED wired to LED_OUT#
SeeAlso: #P0842

Bitfields for Cirrus Logic CL-PD6729 device implementation byte D:
Bit(s)	Description	(Table P0856)
 7	reserved
 6	external clock wired to EXT_CLK
 5-2	reserved
 1	LOCK# wired
 0	CLKRUN wired
SeeAlso: #P0842
----------P03E003E7--------------------------
PORT 03E0-03E7	- LPT port address on the UniRAM card by German magazine c't
Range:	selectable from PORT 0260h, PORT 02E0h, PORT 02E8h, PORT 02F0h,
	  PORT 03E0h, or PORT 03E8h.
SeeAlso: PORT 03E8h"UniRAM"
----------P03E003E7--------------------------
PORT 03E0-03E7 - COM port addresses on UniRAM card by German magazine c't
Range:	selectable from PORT 0238h, PORT 02E8h, PORT 02F8h, PORT 0338h,
	  PORT 03E0h, PORT 03E8h, or PORT 03F8h
SeeAlso: PORT 03E0h"UniRAM"
----------P03E203E3--------------------------
PORT 03E2-03E3 - OPTi 82C824 - CardBus Bridge registers
Range:	PORT 03E0h or PORT 03E2h
SeeAlso: PORT 03E0h"CardBus"

03E2  ?W  index for data register
03E3  RW  CardBus registers
----------P03E803EF--------------------------
PORT 03E8-03EF - serial port, same as 02E8, 02F8 and 03F8 (COM3)
SeeAlso: PORT 03F8h-03FFh
----------P03E803EF--------------------------
PORT 03E8-03EF - COM port addresses on UniRAM card by German magazine c't
Range:	selectable from PORT 0238h, PORT 02E8h, PORT 02F8h, PORT 0338h,
	  PORT 03E0h, PORT 03E8h, or PORT 03F8h
SeeAlso: PORT 03E0h"UniRAM"
----------P03E803EF--------------------------
PORT 03E8-03EF - LPT port address on the UniRAM card by German magazine c't
Range:	selectable from PORT 0260h, PORT 02E0h, PORT 02E8h, PORT 02F0h,
	  PORT 03E0h, or PORT 03E8h.
SeeAlso: PORT 03E8h"UniRAM"
----------P03EB------------------------------
PORT 03EB - GI1904 Scanner Interface Adapter
Range:	PORT 022Bh, PORT 026Bh, PORT 02ABh (default), PORT 02EBh, PORT 032Bh,
	  PORT 036Bh, PORT 03ABh
----------P03EC------------------------------
PORT 03EC - GS-IF Scanner Interface adapter
Range:	PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default),
	  PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh
Note:	many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and
	  others use this interface
----------P03F003F7--------------------------
PORT 03F0-03F7 - FDC 1	(1st Floppy Disk Controller)	second FDC at 0370
Note:	floppy disk controller is usually an 8272, 8272A, NEC765 (or
	  compatible), or an 82072 or 82077AA for perpendicular recording at
	  2.88M
SeeAlso: PORT 0370h-0377h

03F0  R-  diskette controller status A (PS/2) (see #P0857)
03F0  R-  diskette controller status A (PS/2 model 30) (see #P0858)
03F0  R-  diskette EHD controller board jumper settings (82072AA) (see #P0859)
03F1  R-  diskette controller status B (PS/2) (see #P0860)
03F1  R-  diskette controller status B (PS/2 model 30) (see #P0861)
03F2  -W  diskette controller DOR (Digital Output Register) (see #P0862)
03F3  ?W  tape drive register (on the 82077AA)
	bit 7-2	 reserved, tri-state
	bit 1-0	 tape select
		=00  none, drive 0 cannot be a tape drive.
		=01  drive1
		=10  drive2
		=11  drive3
03F4  R-  diskette controller main status register (see #P0865)
	Note:	in non-DMA mode, all data transfers occur through
		  PORT 03F5h and the status registers (bit 5 here
		  indicates data read/write rather than than
		  command/status read/write)
03F4  -W  diskette controller data rate select register (see #P0866)
03F5  R-  diskette command/data register 0 (ST0) (see #P0867)
	status register 1 (ST1) (see #P0868)
	status register 2 (ST2) (see #P0869)
	status register 3 (ST3) (see #P0870)
03F5  -W  diskette command register.  The commands summarized here are
	  mostly multibyte commands. This is for brief recognition only.
	  (see #P0873)
03F6  --  reserved on FDC
03F6  rW  FIXED disk controller data register (see #P0871)
03F7  RW  harddisk controller (see #P0872)
03F7  R-  diskette controller DIR (Digital Input Register, PC/AT mode)
		 bit 7 = 1 diskette change
		 bit 6-0   tri-state on FDC
03F7  R-  diskette controller DIR (Digital Input Register, PS/2 mode)
	  (see #P0863)
03F7  R-  diskette controller DIR (Digital Input Register, PS/2 model 30)
	  (see #P0864)
03F7  -W  configuration control register (PC/AT, PS/2)
		 bit 7-2       reserved, tri-state
		 bit 1-0 = 00  500 Kb/S mode (MFM)
			 = 01  300 Kb/S mode (MFM)
			 = 10  250 Kb/S mode (MFM)
			 = 11  1   Mb/S mode (MFM) (on 82072/82077AA)
	conflict bit 0	   FIXED DISK drive 0 select
03F7  -W  configuration control register (PS/2 model 30)
		 bit 7-3       reserved, tri-state
		 bit 2	       NOPREC (has no function. set to 0 by hardreset)
		 bit 1-0 = 00  500 Kb/S mode (MFM)
			 = 01  300 Kb/S mode (MFM)
			 = 10  250 Kb/S mode (MFM)
			 = 11  1   Mb/S mode (MFM) (on 82072/82077AA)
	conflict bit 0	   FIXED DISK drive 0 select

Bitfields for diskette controller status A (PS/2):
Bit(s)	Description	(Table P0857)
 7	interrupt pending
 6	-DRV2	second drive installed
 5	step
 4	-track 0
 3	head 1 select
 2	-index
 1	-write protect
 0	+direction
SeeAlso: #P0858,#P0860

Bitfields for diskette controller status A (PS/2 model 30):
Bit(s)	Description	(Table P0858)
 7	interrupt pending
 6	DRQ
 5	step F/F
 4	-track 0
 3	head 1 select
 2	+index
 1	+write protect
 0	-direction
SeeAlso: #P0857,#P0859,#P0861

Bitfields for diskette EHD controller board jumper settings:
Bit(s)	Description	(Table P0859)
 7-6	drive 3
 5-4	drive 2
 3-2	drive 1
 1-0	drive 0
	 00  1.2Mb
	 01  720Kb
	 10  2.8Mb
	 11  1.4Mb
SeeAlso: #P0857

Bitfields for diskette controller status B (PS/2):
Bit(s)	Description	(Table P0860)
 7-6	reserved (1)
 5	drive select (0=A:, 1=B:)
 4	write data
 3	read data
 2	write enable
 1	motor enable 1
 0	motor enable 0
SeeAlso: #P0857,#P0861

Bitfields for diskette controller status B (PS/2 model 30):
Bit(s)	Description	(Table P0861)
 7	-DRV2 second drive installed
 6	-DS1
 5	-DS0
 4	write data F/F
 3	read data F/F
 2	write enable F/F
 1	-DS3
 0	-DS2
SeeAlso: #P0858,#P0860

Bitfields for diskette controller Digital Output Register (DOR):
Bit(s)	Description	(Table P0862)
 7-6	reserved on PS/2
 7	drive 3 motor enable
 6	drive 2 motor enable
 5	drive 1 motor enable
 4	drive 0 motor enable
 3	diskette DMA enable (reserved PS/2)
 2	=1  FDC enable	(controller reset)
	=0  hold FDC at reset
 1-0	drive select (0=A 1=B ..)
SeeAlso: #P0857,#P0865,#P0866,#P0863

Bitfields for diskette controller Digital Input Register (PS/2 mode):
Bit(s)	Description	(Table P0863)
 7	= 1 diskette change
 6-3	= 1
 2	datarate select1
 1	datarate select0
 0	= 0 high density select (500Kb/s, 1Mb/s)
 0	(conflict) FIXED DISK drive 0 select
SeeAlso: #P0864,#P0862

Bitfields for diskette controller Digital Input Register (PS/2 model 30):
Bit(s)	Description	(Table P0864)
 7	= 0 diskette change
 6-4	= 0
 3	-DMA gate (value from DOR register)
 2	NOPREC (value from CCR register)
 1	datarate select1
 0	datarate select0
 0	(conflict) FIXED DISK drive 0 select
SeeAlso: #P0863

Bitfields for diskette controller main status register:
Bit(s)	Description	(Table P0865)
 7	=1  RQM	 data register is ready
	=0  no access is permitted
 6	=1  transfer is from controller to system
	=0  transfer is from system to controller
 5	non-DMA mode
 4	diskette controller is busy
 3	drive 3 busy (reserved on PS/2)
 2	drive 2 busy (reserved on PS/2)
 1	drive 1 busy (= drive is in seek mode)
 0	drive 0 busy (= drive is in seek mode)
SeeAlso: #P0862

Bitfields for diskette controller data rate select register:
Bit(s)	Description	(Table P0866)
 7-2	reserved on 8272
 7	software reset (self clearing)	82072/82077AA
 6	power down			82072/82077AA
 5	(8272/82077AA) reserved (0)
	(82072) PLL select bit
 4-2	write precompensation value, 000 default
 1-0	data rate select
	=00  500 Kb/S MFM	250 Kb/S FM
	=01  300 Kb/S MFM	150 Kb/S FM
	=10  250 Kb/S MFM	125 Kb/S FM
	=11  1Mb/S	MFM	illegal	 FM on 8207x
SeeAlso: #P0862

Bitfields for diskette command/data register 0 (ST0):
Bit(s)	Description	(Table P0867)
 7-6	last command status
	00  command terminated successfully
	01  command terminated abnormally
	10  invalid command
	11  terminated abnormally by change in ready signal
 5	seek completed
 4	equipment check occurred after error
 3	not ready
 2	head number at interrupt
 1-0	unit select (0=A 1=B .. ) (on PS/2: 01=A  10=B)
SeeAlso: #P0868,#P0869,#P0870

Bitfields for diskette status register 1 (ST1):
Bit(s)	Description	(Table P0868)
 7	end of cylinder; sector# greater then sectors/track
 6	=0
 5	CRC error in ID or data field
 4	overrun
 3	=0
 2	sector ID not found
 1	write protect detected during write
 0	ID address mark not found
SeeAlso: #P0867,#P0869,#P0870

Bitfields for diskette status register 2 (ST2):
Bit(s)	Description	(Table P0869)
 7	=0
 6	deleted Data Address Mark detected
 5	CRC error in data
 4	wrong cylinder detected
 3	scan command equal condition satisfied
 2	scan command failed, sector not found
 1	bad cylinder, ID not found
 0	missing Data Address Mark
SeeAlso: #P0867,#P0868,#P0870

Bitfields for diskette status register 3 (ST3):
Bit(s)	Description	(Table P0870)
 7	fault status signal
 6	write protect status
 5	ready status
 4	track zero status
 3	two sided status signal
 2	side select (head select)
 1-0	unit select (0=A 1=B .. )
SeeAlso: #P0867,#P0868,#P0869

Bitfields for fixed disk controller data register:
Bit(s)	Description	(Table P0871)
 7-4	reserved
 3	=0  reduce write current
	=1  head select 3 enable
 2	disk reset enable
 1	disk initialization disable
 0	reserved
SeeAlso: #P0862,#P0872

Bitfields for hard disk controller:
Bit(s)	Description	(Table P0872)
 6	FIXED DISK write gate
 5	FIXED DISK head select 3 / reduced write current
 4	FIXED DISK head select 2
 3	FIXED DISK head select 1
 2	FIXED DISK head select 0
 1	FIXED DISK drive 1 select
 0	FIXED DISK drive 0 select
SeeAlso: #P0871

(Table P0873)
Values for diskette commands:
	MFM = MFM mode selected, opposite of MF mode
	HDS = head select
	DS  = drive select
	MT  = multi track operation
	SK  = skip deleted data address mark
   Command	     # bytes	D7  6	5   4	3   2	1   0
 read track		9	0  MFM	0   0	0   0	1   0
				0   0	0   0	0 HDS DS1 DS0
 specify		3	0   0	0   O	O   O	1   1
 sense drive status	2	0   0	0   0	0   1	0   0
				0   0	0   0	0 HDS DS1 DS0
 write data		9	MT MFM	0   0	0   1	0   1
				0   0	0   0	0 HDS DS1 DS0
 read data		9	MT MFM SK   0	0   1	1   0
				0   0	0   0	0 HDS DS1 DS0
 recalibrate		2	0   0	0   0	0   1	1   1
				0   0	0   0	0   0 DS1 DS0
 sense interrupt status 1	0   0	0   0	1   0	0   0
 write deleted data	9	MT MFM	0   0	1   0	0   1
				0   0	0   0	0 HDS DS1 DS0
 read ID		2	0  MFM	0   0	1   0	1   0
				0   0	0   0	0 HDS DS1 DS0
 read deleted data	9	MT MFM SK   0	1   1	0   0
				0   0	0   0	0 HDS DS1 DS0
 format track		10	0  MFM	0   0	1   1	0   1
				0   0	0   0	0 HDS DS1 DS0
 dumpreg **		1	0   0	0   0	1   1	1   0
 seek			3	0   0	0   0	1   1	1   1
				0   0	0   0	0 HDS DS1 DS0
 version** (see #P0874) 1	0   0	0   1	0   0	0   0
 scan equal *		9	MT MFM SK   1	0   0	0   1
				0   0	0   0	0 HDS DS1 DS0
 perpendicular mode **	2	0   0	0   1	0   0	1   0
				0   0	0   0	0   0 WGATE GAP
 configure **		4	0   0	0   1	0   0	1   1
				0   0	0   0	0   0	0   0
 unlock FIFO **		1	0   0	0   1	0   1	0   0
 verify			9	MT MFM SK   1	0   1	1   0
				EC  0	0   0	0 HDS DS1 DS0
 partid ** (see #P0874) 1	0   0	0   1	1   0	0   0
 scan low or equal *	9	MT MFM SK   1	1   0	0   1
				0   0	0   0	0 HDS DS1 DS0
 scan high or equal *	9	MT MFM SK   1	1   1	0   1
				0   0	0   0	0 HDS DS1 DS0
 exit standby mode ***	1	0   0	1   1	0   1	0   0
 enter standby mode ***	1	0   0	1   1	0   1	0   1
 hard reset ***		1	0   0	1   1	0   1	1   0
 lock FIFO **		1	1   0	0   1	0   1	0   0
 relative seek **	3	1  DIR	0   0	1   1	1   1
				0   0	0   0	0 HDS DS1 DS0
BEWARE: not every invalid command is treated as invalid!
 *   Note: the scan commands aren't mentioned for the 82077AA.
 **  Note: EHD controller commands.
 *** Note: Supported by NEC72065B only.

(Table P0874)
Values for FDC Controller chip type identification:
  version lFIFO partid Chip type
    80h	   80h	  -    NEC D765, Intel 8272A or compatible
    80h	   00h	  -    Intel 82072
    81h	    -	  -    Very Early Intel 82077 or compatible
    90h	   80h	  -    Old Intel 82077, no FIFO
    90h	    ?	  ?    NEC 72065B
    90h	   00h	 80h   New Intel 82077 (82077AA if port 3x3h bits 1-0 are R/W)
    90h	   00h	 41h   Intel 82078
    90h	   00h	 73h   National Semiconductor PC87306
    90h	   00h	other  Intel 82078 compatible
    A0h	    -	  -    SMC FDC37c65C+
Note:	Before issuing the partid command, one must first issue an unlock
	  FIFO, immediately followed by a lock FIFO instruction. The status
	  byte returned by the lock FIFO instruction is used in the table above
SeeAlso: #P0873
----------P03F003F1--------------------------
PORT 03F0-03F1 - PCTech RZ1000 IDE controller
Note:	to unlock access to these ports instead of the standard floppy
	  controller status ports at these two addresses, you must perform
	  two immediately successive 8-bit OUTs of 55h to PORT 03F0h (there
	  is a fairly small time limit between the two accesses, so there
	  should be no other instructions between the two OUTs); after
	  that, values written to PORT 03F0h select the data accessed through
	  PORT 03F1h until an AAh is written to 03F0h
SeeAlso: #00732

03F0  ?W  index port (see #P0875)
03F1  RW  data port

(Table P0875)
Values for RZ1000 IDE controller registers:
 00h	???
	bit 7:
	bit 1:
	bit 0:
 01h	???
 02h	???
 03h	???
 04h	???
 05h	???
	bit 1:
 AAh	lock control port
----------P03F803FF--------------------------
PORT 03F8-03FF - Serial port (8250,8250A,8251,16450,16550,16550A,etc.) COM1
Range:	PORT 02E8h-02EFh (COM2), PORT 02F8h-02FFh (typical non-PS/2 COM3), and
	  PORT 03E8h-03EFh (typical non-PS/2 COM4)
Note:	chips overview:
	 8250  original PC, specified up to 56Kbd, but mostly runs
	       only 9600Bd, no scratchregister, bug: sometimes shots
	       ints without reasons
	 8250A, 16450, 16C451: ATs, most chips run up to 115KBd,
	       no bug: shots no causeless ints
	 8250B: PC,XT,AT, pseudo bug: shots one causeless int for
		compatibility with 8250, runs up to 56KBd
	 16550, 16550N, 16550V: early PS/2, FIFO bugs
	 16550A,16550AF,16550AFN,16550C,16C551,16C552: PS/2, FIFO ok
	 82510: laptops & industry, multi emulation mode
		(default=16450), special-FIFO.
	 8251: completely different synchronous SIO chip, not compatible!
SeeAlso: INT 14/AH=00h"SERIAL"

03F8  -W  serial port, transmitter holding register (THR), which contains the
	  character to be sent. Bit 0 is sent first.
		bit 7-0	  data bits when DLAB=0 (Divisor Latch Access Bit)
03F8  R-  receiver buffer register (RBR), which contains the received
	  character. Bit 0 is received first
		 bit 7-0   data bits when DLAB=0 (Divisor Latch Access Bit)
03F8  RW  divisor latch low byte (DLL) when DLAB=1 (see #P0876)
03F9  RW  divisor latch high byte (DLM) when DLAB=1 (see #P0876)
03F9  RW  interrupt enable register (IER) when DLAB=0 (see #P0877)
03FA  R-  interrupt identification register (see #P0878)
	Information about a pending interrupt is stored here. When the ID
	  register is addressed, thehighest priority interrupt is held, and
	  no other interrupts are acknowledged until the CPU services that
	  interrupt.
03FA  -W  16650 FIFO Control Register (FCR) (see #P0879)
03FB  RW  line control register (LCR) (see #P0880)
03FC  RW  modem control register (see #P0881)
03FD  R-  line status register (LSR) (see #P0882)
03FE  R-  modem status register (MSR) (see #P0883)
03FF  RW  scratch register (SCR)
	(not used for serial I/O; available to any application using 16450,
	  16550) (not present on original 8250)

(Table P0876)
Values for serial port divisor latch registers:
 Some baudrates (using standard 1.8432 Mhz clock):
       baudrate	   divisor	 DLM  DLL
	    50	   2304		  09h 00h
	    75	   1536		  06h 00h
	   110	   1047		  04h 17h
	   134,5    857		  03h 59h
	   150	    768		  03h 00h
	   300	    384		  01h 80h
	   600	    192		  00h C0h
	  1200	     96		  00h 60h
	  1800	     64		  00h 40h
	  2000	     58		  00h 3Ah
	  2400	     48		  00h 30h
	  3600	     32		  00h 20h
	  4800	     24		  00h 18h
	  7200	     16		  00h 10h
	  9600	     12		  00h 0Ch
	 19200	      6		  00h 06h
	 38400	      3		  00h 03h
	 57600	      2		  00h 02h
	115200	      1		  00h 01h
Note:	MIDI baudrate 32250Bd with 4Mhz quarz for c't MIDI interface
	  following c't 01/1991:   '14400'	  00h 08h

Bitfields for serial port interrupt enable register (IER):
Bit(s)	Description	(Table P0877)
 7-6	reserved (0)
 5	(82510) "timer"
	(other) reserved (0)
 4	(82510) "transmit machine"
	(other) reserved (0)
 3	modem-status interrupt enable
 2	receiver-line-status interrupt enable
 1	transmitter-holding-register empty interrupt enable
 0	received-data-available interrupt enable
	  (also 16550(A) timeout interrupt)
Note:	16550(A) will interrupt with a timeout if data exists in the FIFO
	  and isn't read within the time it takes to receive four bytes or if
	  no data is received within the time it takes to receive four bytes
SeeAlso: #P0878

Bitfields for serial port interrupt identification register (IIR):
Bit(s)	Description	(Table P0878)
 7-6	=00  reserved on 8250, 8251, 16450
	=01  if FIFO queues enabled but unusable (16550 only)
	=11  if FIFO queues are enabled (16550A only) (see also #P0879)
 6-5	used by 82510 for bank select (00 = default bank0)
 5-4	reserved (0)
 3-1	identify pending interrupt with the highest priority
	110	(16550,82510) timeout interrupt pending
	101	(82510) timer interrupt (see #P0877)
	100	(82510) transmit machine (see #P0877)
	011	receiver line status interrupt. priority=highest
	010	received data available register interrupt. pr.=second
	001	transmitter holding register empty interrupt. pr.=third
	000	modem status interrupt. priority=fourth
 0	=0 interrupt pending. contents of register can be used as a pointer
	  to the appropriate interrupt service routine
	=1 no interrupt pending
Notes:	interrupt pending flag uses reverse logic, 0=pending, 1=none
	interrupt will occur if any of the line status bits are set
	THRE bit is set when THRE register is emptied into the TSR
SeeAlso: #P0877

Bitfields for serial port FIFO control register (FCR):
Bit(s)	Description	(Table P0879)
 7-6	received data available interrupt trigger level (16550)
	00  1 byte
	01  4 bytes
	10  8 bytes
	11 14 bytes
 6-5	=00  (used to enable 4 byte Rx/Tx FIFOs on 82510???)
	=10 ???
 5-4	reserved (00)
 3	change RXRDY  TXRDY pins from mode 0 to mode 1
 2	clear XMIT FIFO
 1	clear RCVR FIFO
 0	enable clear XMIT and RCVR FIFO queues
 4-0	(other purpose on 82510???)
Notes:	bit 0 must be set in order to write to other FCR bits
	bit 1 when set	the RCVR FIFO is cleared and this bit is reset
	  the receiver shift register is not cleared
	bit 2 when set	the XMIT FIFO is cleared and this bit is reset
	  the transmit shift register is not cleared
	due to a hardware bug, 16550 FIFOs don't work correctly (this
	  was fixed in the 16550A)
SeeAlso: #P0878

Bitfields for serial port Line Control Register (LCR):
Bit(s)	Description	(Table P0880)
 7	=1  divisor latch access bit (DLAB)
	=0  receiver buffer, transmitter holding, or interrupt enable register
	  access
 6	set break enable. serial ouput is forced to spacing state and remains
	  there.
 5-3	PM2 PM1 PM0
	 x   x	 0 = no parity
	 0   0	 1 = odd parity
	 0   1	 1 = even parity
	 1   0	 1 = high parity (sticky)
	 1   1	 1 = low parity (sticky)
	 x   x	 1 = software parity
 2	stop bit length (STB/SBL)
	0  one stop bit
	1  2 stop bits with (word length 6, 7, 8)
	   1.5 stop bits with word length 5
 1-0	(WLS1-0, CL1-0)
	00 word length is 5 bits
	01 word length is 6 bits
	10 word length is 7 bits
	11 word length is 8 bits
SeeAlso: #P0881,#P0882,#P0883

Bitfields for serial port Modem Control Register (MCR):
Bit(s)	Description	(Table P0881)
 7-6	reserved (0)
 5	(82510 only) state of OUT0 pin
 4	loopback mode for diagnostic testing of serial port
	output of transmitter shift register is looped back to receiver
	  shift register input. In this mode, transmitted data is received
	  immediately so that the CPU can verify the transmit data/receive
	  data serial port paths.
	If OUT2 is disabled, there is no official way to generate an IRQ
	  during loopback mode.
 3	auxiliary user-designated output 2 (OUT2)
	because of external circuity OUT2 must be 1 to master-intr-enableing.
	BUG: Some Toshiba Laptops utilize this bit vice versa, newer Toshiba
	  machines allow assignment of the bit's polarity in system setup.
	82050: This bit is only effective, if the chip is being used with an
	  externally-generated clock.
 2	=1/0  auxiliary user-designated output 1 (OUT1)
	should generally be cleared!!
	Some external hardware, e.g. c't MIDI interface (and compatibles) use
	  this bit to change the 8250 input clock from 1,8432 MHz to 4Mhz
	  (enabling MIDI-conformant baudrates) and switching to
	  MIDI-compatible current loop connectors.
 1	force request-to-send active (RTS)
 0	force data-terminal-ready active (DTR)
SeeAlso: #P0880,#P0882,#P0883

Bitfields for serial port Line Status Register (LSR):
Bit(s)	Description	(Table P0882)
 7	=0  reserved
	=1  on some chips produced by UMC
 6	transmitter shift and holding registers empty
 5	transmitter holding register empty (THRE)
	Controller is ready to accept a new character to send.
 4	break interrupt. the received data input is held in the zero bit
	  state longer than the time of start bit + data bits + parity bit +
	  stop bits.
 3	framing error (FE). the stop bit that follows the last parity or data
	  bit is a zero bit
 2	parity error (PE). Character has wrong parity
 1	overrun error (OE). a character was sent to the receiver buffer
	  before the previous character in the buffer could be read. This
	  destroys the previous character.
 0	data ready. a complete incoming character has been received and sent
	  to the receiver buffer register.
SeeAlso: #P0880,#P0881,#P0883

Bitfields for serial port Modem Status Register (MSR):
Bit(s)	Description	(Table P0883)
 7	data carrier detect (-DCD)
 6	ring indicator (-RI)
 5	data set ready (-DSR)
 4	clear to send (-CTS)
 3	delta data carrier detect (DDCD)
 2	trailing edge ring indicator (TERI)
 1	delta data set ready (DDSR)
 0	delta clear to send (DCTS)
Notes:	bits 0-3 are reset when the CPU reads the MSR
	bit 4 is the Modem Control Register RTS during loopback test
	bit 5 is the Modem Control Register DTR during loopback test
	bit 6 is the Modem Control Register OUT1 during loopback test
	bit 7 is the Modem Control Register OUT2 during loopback test
SeeAlso: #P0880,#P0881,#P0882
--------!---Note-----------------------------
Note:	Adresses above 03FF generally apply to EISA and PCI machines only !
	EISA port assignments:
	    1000-1FFF	slot 1 EISA
	    2000-2FFF	slot 2 EISA
	    3000-3FFF	slot 3 EISA
	    4000-4FFF	slot 4 EISA
	    5000-5FFF	slot 5 EISA
	    6000-6FFF	slot 6 EISA
	    7000-7FFF	slot 7 EISA
----------P0401040B--------------------------
PORT 0401-040B - EISA DMA Controller
SeeAlso: PORT 0481h-048Bh"EISA",PORT 04D4h-04D6h"EISA"

0401  RW  DMA channel 0 word count byte 2 (high)
0403  RW  DMA channel 1 word count byte 2 (high)
0405  RW  DMA channel 2 word count byte 2 (high)
0407  RW  DMA channel 3 word count byte 2 (high)
040A  -W  extended DMA chaining mode register, channels 0-3 (see #P0884)
040A  R-  channel interrupt (IRQ13) status register (see #P0885)
040B  -W  DMA extended mode register for channels 0-3 (see #P0886)
	(bit settings same as PORT 04D6h)

Bitfields for EISA extended DMA chaining mode register (channels 0-3):
Bit(s)	Description	(Table P0884)
 7-5	reserved
 4	=0  generate IRQ13
	=1  generate terminal count
 3	=0  do not start chaining
	=1  programming complete
 2	=0  disable buffer chaining mode (default)
	=1  enable buffer chaining mode
 1-0	DMA channel select
SeeAlso: #P0885,#P0886,#P0893

Bitfields for EISA channel interrupt (IRQ13) status register:
Bit(s)	Description	(Table P0885)
 7-5  interrupt on channels 7-5
 4	  reserved
 3-0  interrupt on channels 3-0
SeeAlso: #P0884

Bitfields for EISA DMA extended mode register (channels 0-3):
Bit(s)	Description	(Table P0886)
 7	=0 enable stop register
 6	=0 terminal count is an output for this channel	(default)
 5-4	DMA cycle timing
	00 ISA-compatible (default)
	01 type A timing mode
	10 type B timing mode
	11 burst DMA mode
 3-2	Address mode
	00 8-bit I/O, count by bytes (default)
	01 16-bit I/O, count by words, address shifted
	10 32-bit I/O, count by bytes
	11 16-bit I/O, count by bytes
 1-0	DMA channel select
SeeAlso: #P0884,#P0894
----------P040A043F--------------------------
PORT 040A-043F - Intel 82378ZB embedded DMA controller
Range:	relocatable via Relocation Base Address register (see #01075)
SeeAlso: PORT 0401h"EISA",#01064,#01075

040A  R-  scatter/gather interrupt status (see #P0887)
040B  -W  DMA1 extended mode
0410  -W  CH0 scatter/gather command (see #P0888)
0411  -W  CH1 scatter/gather command
0412  -W  CH2 scatter/gather command
0413  -W  CH3 scatter/gather command
0414  -W  CH4 scatter/gather command
0415  -W  CH5 scatter/gather command
0416  -W  CH6 scatter/gather command
0417  -W  CH7 scatter/gather command (see #P0888)
0418  R-  CH0 scatter/gather status (see #P0889)
0419  R-  CH1 scatter/gather status
041A  R-  CH2 scatter/gather status
041B  R-  CH3 scatter/gather status
041C  R-  CH4 scatter/gather status
041D  R-  CH5 scatter/gather status
041E  R-  CH6 scatter/gather status
041F  R-  CH7 scatter/gather status (see #P0889)
0420d RW  CH0 scatter/gather descriptor table address
0424d RW  CH1 scatter/gather descriptor table address
0428d RW  CH2 scatter/gather descriptor table address
042Cd RW  CH3 scatter/gather descriptor table address
0430d RW  CH4 scatter/gather descriptor table address
0434d RW  CH5 scatter/gather descriptor table address
0438d RW  CH6 scatter/gather descriptor table address
043Cd RW  CH7 scatter/gather descriptor table address

(Table P0887)
Call Intel 82378ZB Scatter/Gather Interrupt Status Register with:
 7	channel 7 has interrupt due to S/G transfer
 ...
 0	channel 0 has interrupt due to S/G transfer
SeeAlso: #P0888,#P0889

Bitfields for Intel 82378ZB Scatter/Gather Command Register:
Bit(s)	Description	(Table P0888)
  7	select last-buffer termination type
	=0 assert IRQ13 on completion
	=1 assert EOP on completion
 6	enable bit 7 termination-type selection
 5-2	reserved (0)
 1-0	scatter-gather command
	00 none
	01 start S/G command
	10 stop S/G command
	11 reserved
SeeAlso: #P0887,#P0889,#01075

Bitfields for Intel 82378ZB Scatter/Gather Status Register:
Bit(s)	Description	(Table P0889)
 7	no next link
 6	reserved
 5	issue IRQ13 instead of EOP at end of last buffer
 4	reserved
 3	scatter/gather Base Register status
	=1 buffer link has been loaded
	=0 empty
 2	scatter/gather Current Register status
	=1 buffer link has been loaded
	=0 empty
 1	reserved
 0	scatter/gather is active
SeeAlso: #P0888
--------X-P040D040F--------------------------
PORT 040D-040F - EISA - Intel 82357

040D  R-  chip stepping level
040E  RW  test register 1
040F  RW  test register 2
----------P04610462--------------------------
PORT 0461-0462 - EISA NMI CONTROL

0461  RW  Extended NMI status/control register (see #P0890)
0462  -W  Software NMI register. writing to this register causes an NMI	if
	  NMIs are enabled
	bit 7 = 1  generates an NMI

Bitfields for EISA extended NMI status control register:
Bit(s)	Description	(Table P0890)
 7  R-	NMI pending from fail-safe (watchdog) timer
 6  R-	NMI pending from bus timeout NMI status
 5  R-	NMI pending from I/O port status
 4  R-	busmaster preemption timeout if bit 6 set
 3  RW	bus timeout NMI enable
 2  RW	fail-safe (watchdog) NMI enable
 1  RW	NMI I/O port enable
 0  RW	RSTDRV. bus reset
	=0  NORMAL bus reset operation
	=1  reset bus asserted
--------X-P04640465--------------------------
PORT 0464-0465 - EISA BUS MASTER STATUS

0464w R	  bus master status latch register (slots 1-16)
	identifies the last bus master that had control of the bus (bit N =0 if
	  slot N+1 had control last)
----------P0481048B--------------------------
PORT 0481-048B - EISA DMA page registers
Note:	these registers are also supported on many non-EISA machines, e.g. by
	  most machines using Intel PCI chipsets
SeeAlso: PORT 0401h-040Bh"EISA",PORT 04C6h-04CFh"EISA"

0481  RW  DMA channel 2 address byte 3 (high)
0482  RW  DMA channel 3 address byte 3 (high)
0483  RW  DMA channel 1 address byte 3 (high)
0487  RW  DMA channel 0 address byte 3 (high)
0489  RW  DMA channel 6 address byte 3 (high)
048A  RW  DMA channel 7 address byte 3 (high)
048B  RW  DMA channel 5 address byte 3 (high)
----------P04C604CF--------------------------
PORT 04C6-04CF - EISA DMA count registers
SeeAlso: PORT 0401h-040Bh"EISA",PORT 0481h-048Bh"EISA",PORT 04E0h-04FFh"EISA"

04C6  RW  DMA channel 5 word count byte 2 (high)
04CA  RW  DMA channel 6 word count byte 2 (high)
04CE  RW  DMA channel 7 word count byte 2 (high)
--------X-P04D004D1--------------------------
PORT 04D0-04D1 - EISA IRQ control
Note:	these registers are also supported on many non-EISA machines, e.g. by
	  most machines using Intel PCI chipsets
SeeAlso: PORT 04D4h-040Bh"EISA"

04D0  -W  IRQ 0-7 interrupt edge/level registers (see #P0891)
04D1  -W  IRQ 8-15 interrupt edge/level registers (see #P0892)

Bitfields for EISA IRQ 0-7 interrupt edge/level register:
Bit(s)	Description	(Table P0891)
 7	IRQ 7 is level sensitive
 6	IRQ 6 is level sensitive
 5	IRQ 5 is level sensitive
 4	IRQ 4 is level sensitive
 3	IRQ 3 is level sensitive
 2-0	reserved
SeeAlso: #P0892

Bitfields for EISA IRQ 8-15 interrupt edge/level register:
Bit(s)	Description	(Table P0892)
 7	IRQ 15 is level sensitive
 6	IRQ 14 is level sensitive
 5	reserved (1)
 4	IRQ 12 is level sensitive
 3	IRQ 11 is level sensitive
 2	IRQ 10 is level sensitive
 1	IRQ 9  is level sensitive
 0	reserved
SeeAlso: #P0891
----------P04D404D6--------------------------
PORT 04D4-04D6 - EISA DMA control
Note:	PORT 04D6h is also supported by the Intel 82378ZB System I/O controller
SeeAlso: PORT 0401h-040Bh"EISA",PORT 04D0h-04D1h"EISA"

04D4  R-  DMA chaining status
04D4  -W  extended DMA chaining mode register, channels 4-7 (see #P0893)
04D6  -W  DMA extended mode register for channels 4-7 (see #P0894)
	bit settings same as PORT 040Bh

Bitfields for EISA extended DMA chaining mode register (channels 4-7):
Bit(s)	Description	(Table P0893)
 7-5	reserved (0)
 4	=0  generate IRQ 13
	=1  generate terminal count
 3	=0  do not start chaining
	=1  programming complete
 2	=0  disable buffer chaining mode (default)
	=1  enable buffer chaining mode
 1-0	DMA channel select
SeeAlso: #P0884,#P0894

Bitfields for EISA DMA extended mode register (channels 4-7):
Bit(s)	Description	(Table P0894)
 7	=0  enable stop register
 6	=0  terminal count is an output for this channel (default)
 5-4	DMA cycle timing
	00 ISA-compatible (default)
	01 type A timing mode
	10 type B timing mode
	11 burst DMA mode
 3-2	Address mode
	00 8-bit I/O, count by bytes (default)
	01 16-bit I/O, count by words, address shifted
	10 32-bit I/O, count by bytes
	11 16-bit I/O, count by bytes
 1-0	DMA channel select
SeeAlso: #P0886,#P0893
----------P04E004FF--------------------------
PORT 04E0-04FF - EISA DMA stop registers
SeeAlso: PORT 0481h-048Bh"EISA"

04E0-04E2  RW	channel 0 stops if DMA transfer reaches specified address
04E4-04E6  RW	channel 1
04E8-04EA  RW	channel 2
04EC-04EE  RW	channel 3
04F4-04F6  RW	channel 5
04F8-04FA  RW	channel 6
04FC-04FE  RW	channel 7
----------P05300533--------------------------
PORT 0530-0533 - Gravis Ultra Sound Daughter Card by Advanced Gravis
Range:	dipswitch selectable from PORT 0530h-0533h, PORT 0604h-0607h,
	  PORT 0E80h-0E83h, and PORT 0F40h-0F43h
SeeAlso: PORT 0530h"Windows Sound System"

0530  RW  address select (see #P0895)
0531  RW  data (selected by PORT 0530h)
0532  RW  status
0533  RW  PIO data
----------P05300537--------------------------
PORT 0530-0537 - Windows Sound System ("WSS") (default address)
Range:	dipswitch selectable among PORT 0530h-0537h,PORT 0604h-060Bh,
	  PORT 0E80h-0E87h, and PORT 0F40h-0F47h
Notes:	the Sound Galaxy NX16 sound cards contains a Crystal CS4231, and thus
	  support the CODEC portion of the WSS on ports 0534h-0537h
	  (or 0608h-060Bh, etc.)
	the AMD InterWave chip supports a superset of the WSS CS4231 Codec,
	  though by default it is not placed at any of the addresses used by
	  the WSS
SeeAlso: PORT 032Ch"InterWave",PORT 0340h"Gravis",PORT 0530h"Vendetta"

0534  ?W  register select (index) (see #P0895)
0535  RW  data register (selected by PORT 0534h)
0536  R?  (CS4231A) status register
0537  RW  (CS4231A) PIO data register

(Table P0895)
Values for Windows Sound System CS4231 Codec register number:
 00h	Mixer: ADC volume (left)
 01h	Mixer: ADC volume (right)
 02h	Mixer: Line In volume (right) (see #P0896)
 03h	Mixer: Line In volume (left) (see #P0896)
 04h	Mixer: FM volume (right) (see #P0896)
 05h	Mixer: FM volume (left) (see #P0896)
 06h	Mixer: playback DAC volume (left)
 07h	Mixer: playback DAC volume (right)
 08h	playback data format
 09h	configuration register 1
 0Ah	external control
 0Bh	Codec status register 2
 0Ch	mode select
	bit 6: ???
 0Dh	loopback control
	(Sound Galaxy) microphone input enabled by bit 0 ???
 0Eh	playback count (high)
 0Fh	playback count (low)
 10h	configuration register 2
 11h	configuration register 3
 12h	Mixer: CD volume (right) (see #P0896)
 13h	Mixer: CD volume (left) (see #P0896)
 14h	timer (low)
 15h	timer (high)
 16h	Mixer: microphone input control (left)
 17h	Mixer: microphone input control (right)
 18h	Codec status register 3
 19h	Mixer: output attenuation (left)
 1Ah	mono input/output control
	(Sound Galaxy) SB volume (see #P0897)
 1Bh	Mixer: output attenuation (right)
 1Ch	record data format
 1Dh	playback variable frequency
 1Eh	record count (high)
 1Fh	record count (low)
 48h	(Sound Galaxy) ???
Notes:	to enable the microphone input on the Sound Galaxy, ALL of the
	  following registers must be set: 00h set to 80h, 01h set to 80h,
	  07h to 00h, 0Dh to 01h, and 48h to 4Bh
	on the Sound Galaxy NX16, only bits 0-4 of the register number are
	  fully decoded, so most registers above 1Fh are aliases of the
	  first 32 registers

Bitfields for WSS mixer volume:
Bit(s)	Description	(Table P0896)
 7	disable input source
 6-5	reserved???
 4-0	volume (00h = highest, 1Fh = lowest)
SeeAlso: #P0895,#P0897
Note:	the GW2000 GWBVOL.EXE only permits the setting of volume levels
	  08h (reported as 16) to 18h (reported as 0, and sets bit 7 as well)

Bitfields for WSS mixer volume (SoundBlaster):
Bit(s)	Description	(Table P0897)
 7	disable input source
 6-4	reserved???
 3-0	volume (00h = highest, 0Fh = lowest)
SeeAlso: #P0895,#P0896
----------P05300537--------------------------
PORT 0530-0537 - OPTi "Vendetta" Windows Sound System emulation (default addr)
SeeAlso: PORT 0530h"WSS",PORT 0F8Dh"Vendetta",PORT 0F8Eh"Vendetta"

0530  -W  (OPTi "Vendetta") WSS configuration register (see #P0898)
0530  R-  (OPTi "Vendetta") WSS version register (see #P0899)
0534  RW  (OPTi "Vendetta") codec index address register (see #P0900)
0535  RW  (OPTi "Vendetta") codec indexed data register
0536  RW  (OPTi "Vendetta") codec status register (see #P0901)
0537  R-  (OPTi "Vendetta") codec direct data register - capture mode
0537  -W  (OPTi "Vendetta") codec direct data register - playback mode

Bitfields for OPTi "Vendetta" WSS configuration register:
Bit(s)	Description	(Table P0898)
 7	reserved
 6	IRQ sense source
	0 = normal
	1 = interrupt auto-selection
 5-3	WSS IRQ
	000 = disable
	001 = IRQ7
	010-100 = IRQ9-IRQ11
	101 = IRQ5
	110-111 = reserved
 2-0	WSS DRQ
	      playback	capture
	000 = disable	disable
	001 = DRQ0	disable
	010 = DRQ1	disable
	011 = DRQ3	disable
	100 = disable	DRQ1
	101 = DRQ0	DRQ1
	110 = DRQ1	DRQ0
	111 = DRQ3	DRQ0
SeeAlso: PORT 0530-0537

Bitfields for OPTi "Vendetta" WSS version register:
Bit(s)	Description	(Table P0899)
 7	available channel
	0 = DRQ0/1/3 and IRQ7/9/10/11 available
	1 = DRQ1/3 and IRQ7/9 available
 6	IRQ sense
	0 = no interrupt
	1 = WSS interrupt active
 5-0	version (04h)
SeeAlso: PORT 0530-0537

Bitfields for OPTi "Vendetta" codec index address register:
Bit(s)	Description	(Table P0900)
 7	initialization
	1 = codec cannot respond to parallel bus cycles
 6	mode change enable
 5	transfer request
	0 = transfers enabled during interrupt
	1 = transfers disabled by interrupt
 4-0	index address (see #P0902)
	  (audio module control register 5 bit 5 must be set in order
	  to access indexes 10h-1Fh)
SeeAlso: PORT 0530-0537

Bitfields for OPTi "Vendetta" codec status register:
Bit(s)	Description	(Table P0901)
 7	PIO capture data ready (read-only)
	0 = lower byte
	1 = upper byte (or 8-bit)
 6	PIO capture data ready (read-only)
	0 = right
	1 = left (or mono)
 5	PIO capture data register data ready (read-only)
	0 = stale ADC data (do not re-read)
	1 = fresh ADC data (ready for host data read)
 4	sample ADC capture overrun/DAC playback underrun occurred (read-only)
 3	PIO playback data needed (read-only)
	0 = lower byte
	1 = upper byte (or 8-bit)
 2	PIO playback data needed (read-only)
	0 = right
	1 = left (or mono)
 1	PIO playback data register ready for data (read-only)
	0 = valid DAC data (do not overwrite)
	1 = stale DAC data (ready for host data write)
 0	interrupt enable
SeeAlso: PORT 0530-0537

(Table P0902)
Values for OPTi "Vendetta" (82C750) codec indirect registers:
 00h	MIXOUTL output control register (see #P0903)
 01h	MIXOUTR output control register (see #P0903)
 02h	CDL input control register (see #P0904)
 03h	CDR input control register (see #P0904)
 04h	FML input control register (see #P0904)
 05h	FMR input control register (see #P0904)
 06h	DACL input control register (see #P0905)
 07h	DACR input control register (see #P0905)
 08h	frequency synthesizer and playback data format register (see #P0906)
 09h	interface configuration register (see #P0907)
 0Ah	pin control register (see #P0908)
 0Bh	error status and initialization register (read-only) (see #P0909)
 0Ch	ID register (see #P0910)
 0Dh	reserved
 0Eh	playback upper base count register
	  (used for playback and capture in SB mode)
 0Fh	playback lower base count register
	  (used for playback and capture in SB mode)
 10h	AUXL input control register (see #P0904)
 11h	AUXR input control register (see #P0904)
 12h	LINEL input control register (see #P0904)
 13h	LINER input control register (see #P0904)
 14h	MICL input control register (see #P0911)
 15h	MICR input control register (see #P0912)
 16h	OUTL output control register (see #P0913)
 17h	OUTR output control register (see #P0913)
 18h-1Bh reserved
 1Ch	capture data format register (see #P0906)
 1Dh	reserved
 1Eh	capture upper base count register
 1Fh	capture lower base count register
Note:	To access expanded mode registers (10h-1Fh), audio module control
	  register 5 bit 5 must be set.
SeeAlso: #P0900

Bitfields for OPTi "Vendetta" MIXOUTL/R output control register:
Bit(s)	Description	(Table P0903)
 7-6	source select
	00 = LINE
	01 = CD
	10 = MIC
	11 = MIXER
 5	MIC +20dB gain enable
 4	reserved
 3-0	gain select for MIXOUTL/R
	0000-1111 = 0dB to +22.5dB in 1.5dB steps
SeeAlso: #P0902

Bitfields for OPTi "Vendetta" CD/FM/AUX/LINE L/R input control register:
Bit(s)	Description	(Table P0904)
 7	mute enable
 6-5	reserved
 4-1	gain select for CD/FM/AUX/LINE L/R
	0000-1111 = +12dB to -33dB in 3dB steps
 0	reserved
SeeAlso: #P0902

Bitfields for OPTi "Vendetta" DACL/R input control register:
Bit(s)	Description	(Table P0905)
 7	mute enable
 6-5	reserved
 4-0	gain select for DACL/R
	00000-11111 = 0dB to -46.5dB in 1.5dB steps
SeeAlso: #P0902

Bitfields for OPTi "Vendetta" frequency synth and playback/capture data format:
Bit(s)	Description	(Table P0906)
 7-5	audio data format
	000 = linear, 8-bit unsigned
	001 = æ-law, 8-bit companded
	010 = linear, 16-bit two's complement, little endian
	011 = A-law, 8-bit companded
	100 = reserved
	101 = ADPCM, 4-bit, IMA compatible
	110 = linear, 16-bit two's complement, big endian
	111 = reserved
	  (bit 7 forced to 0 in mode 1)
 4	0 = mono
	1 = stereo
 3-0	(playback) clock frequency divide/audio sample rate frequency
	0000 = 8.0kHz
	0001 = 5.5125kHz
	0010 = 16.0kHz
	0011 = 11.025kHz
	0100 = 27.42857kHz
	0101 = 18.9kHz
	0110 = 32.0kHz
	0111 = 22.05kHz
	1000 = reserved
	1001 = 37.8kHz
	1010 = reserved
	1011 = 44.1kHz
	1100 = 48.0kHz
	1101 = 33.075kHz
	1110 = 9.6kHz
	1111 = 6.615kHz
	(capture) reserved
Note:	the contents of these registers can be changed only if mode change bit
	  is set (see #P0900).
SeeAlso: #P0902

Bitfields for OPTi "Vendetta" interface configuration register:
Bit(s)	Description	(Table P0907)
 7	capture data transfer method (0 = DMA, 1 = PIO)
 6	playback data transfer method (0 = DMA, 1 = PIO)
 5-4	reserved
 3	autocalibration enable
 2	DMA channel mode (0 = dual, 1 = single)
 1	capture data in selected format enable
 0	playback data in selected format enable
SeeAlso: #P0902

Bitfields for OPTi "Vendetta" pin control register:
Bit(s)	Description	(Table P0908)
 7-2	reserved
 1	interrupt pin enable
	  (goes active high on reaching the number of samples in base count
	  register)
 0	reserved
SeeAlso: #P0902

Bitfields for OPTi "Vendetta" error status and initialization register:
Bit(s)	Description	(Table P0909)
 7	capture overrun
 6	playback underrun
 5	autocalibration state
	0 = in progress
	1 = not in progress
 4	current PDRQ/CDRQ status
	0 = inactive (low)
	1 = active (high)
 3-2	under/over range on right input channel
	00 = less than -1dB under range
	01 = between -1dB and 0dB under range
	10 = between 0dB and +1dB over range
	11 = greater than +1dB over range
 3-2	under/over range on left input channel
	00 = less than -1dB under range
	01 = between -1dB and 0dB under range
	10 = between 0dB and +1dB over range
	11 = greater than +1dB over range
SeeAlso: #P0902

Bitfields for OPTi "Vendetta" ID register:
Bit(s)	Description	(Table P0910)
 7-4	reserved
 3-0	codec revision ID (read-only)
SeeAlso: #P0902

Bitfields for OPTi "Vendetta" MICL input control register:
Bit(s)	Description	(Table P0911)
 7	mute enable
 6	MICR mix into OUTL enable
 5	reserved
 4-1	gain select for MICL
	0000-1111 = +12dB to -33dB in 3dB steps
 0	reserved
SeeAlso: #P0902

Bitfields for OPTi "Vendetta" MICR input control register:
Bit(s)	Description	(Table P0912)
 7	mute enable
 6	MICL mix into OUTR enable
 5	reserved
 4-1	gain select for MICR
	0000-1111 = +12dB to -33dB in 3dB steps
 0	reserved
SeeAlso: #P0902,#P0913

Bitfields for OPTi "Vendetta" OUTL/R output control register:
Bit(s)	Description	(Table P0913)
 7	mute enable
 6	reserved
 5-1	gain select for OUTL/R
	00000-11111 = 0dB to -93dB in 3dB steps
 0	reserved
SeeAlso: #P0902,#P0913
----------P0601------------------------------
PORT 0601 - Headland HL21, Acer M5105 chipsets - SYSTEM CONTROL

0601  -W  system control (see #P0914)
0601  R-  status (see #P0915)

Bitfields for Headland HL21/Acer M5105 system control register:
Bit(s)	Description	(Table P0914)
 7	=1  power LED on
 6	=1  LCD backlight off
 5	???
 4	???
 3	???
 2	=1  video chips disabled, screen blanked.
 1	???
 0	=1  will lock up your machine!
SeeAlso: #P0915

Bitfields for Headland HL21/Acer M5105 status register:
Bit(s)	Description	(Table P0915)
 7	=0  if screen enabled always these values
 6	=0
 5	=0
 4	=0
 3	=0
 2	=1  (=0 at low power)
 1	=0  power OK
 0	=0
SeeAlso: #P0914
----------P06040607--------------------------
PORT 0604-0607 - Gravis Ultra Sound Daughter Card by Advanced Gravis
Range:	dipswitch selectable from PORT 0530h-0533h, PORT 0604h-0607h,
	  PORT 0E80h-0E83h, and PORT 0F40h-0F43h
----------P0604060B--------------------------
PORT 0604-060B - Windows Sound System
Range:	PORT 0530h-0537h,PORT 0604h-060Bh,PORT 0E80h-0E87h,PORT 0F40h-0F47h
SeeAlso: PORT 0530h"Sound System"
----------P06200627--------------------------
PORT 0620-0627 - PC network (adapter 1)
0628-062F - PC network (adapter 2)
----------P063E063F--------------------------
PORT 063E-063F - WINTEL.VXD - API
Note:	the WinTel remote-control program uses these two virtualized ports
	  as an API between it main application HOST.EXE and the WINTEL.VXD
	  driver
Index:	installation check;WinTel

063E  R-  always reads 42h if WinTel.VXD is loaded (installation check)
063E  -W  simulate keystroke to current Windows VM (scan code as it would
		  be read from keyboard, including make/break in bit 7)
		  (see also INT 09)
063F  RW  watchdog/scratchpad (see #P0916)

Bitfields for WimTel watchdog/scratchpad byte:
Bit(s)	Description	(Table P0916)
 7-4	scratchpad; HOST.EXE uses as follows:
	bit 7: physical connection is active
	bit 6: sending file
	bit 5: receiving file
	bit 4: session is active
 1	retrigger watchdog (write 03h to PORT 063Fh to avoid reboot)
 0	enable watchdog (PC is rebooted if watchdog not retriggered every 20s)
----------P0678067A--------------------------
PORT 0678-067A - Intel 82091AA - ECP-mode PARALLEL PORT
Range:	PORT 0678h or PORT 0378h, depending on the base address of the parallel
	  port (0278h or 0378h)
SeeAlso: PORT 0278h,PORT 0778h,PORT 07BCh

0278  RW  (when ECR bits 7-5=011) ECP Address/RLE FIFO (see #P0917)
	(this is the same address normally used for parallel port data)
0678  RW  (when ECR bits 7-5=010) standard parallel port data FIFO (see #P0918)
0678  RW  (when ECR bits 7-5=011) ECP data FIFO (see #P0919)
0678  RW  (when ECR bits 7-5=110) test FIFO (see #P0920)
0678  RW  (when ECR bits 7-5=111) ECP configuration A (see #P0921)
0679  RW  (when ECR bits 7-5=111) ECP configuration B (see #P0922)
067A  RW  extended control register (ECR) (see #P0923)

Bitfields for ECP Address/RLE FIFO:
Bit(s)	Description	(Table P0917)
 7	address/RLE-count select
	=0 RLE count
	=1 channel address
 6-0	channel address (bit 7 set)
	RLE count, less 1 (bit 7 clear)
Notes:	when using hardware RLE decompression, the associated data is written
	  to the data FIFO (see #P0919) after the count is set here
	an RLE count of 1 (two identical bytes) will cause unnecessary
	  expansions
	the peripheral device performs the interpretation of this byte as
	  address or RLE count; writing to this port simply causes the AUTOFD#
	  line to be asserted to tell the peripheral that the byte is not data
SeeAlso: #P0923,#P0918

Bitfields for ECP Standard Parallel Port data FIFO:
Bit(s)	Description	(Table P0918)
 7-0	standard parallel port data
Notes:	data written or DMAed to this port are buffered in the FIFO and
	  transmitted to the peripheral using a standard ISA-compatible
	  hardware handshake
	PORT 027Ah bit 5 must be clear to enable the forward transfer direction
SeeAlso: #P0917,#P0918,#P0923

Bitfields for ECP data FIFO:
Bit(s)	Description	(Table P0919)
 7-0	ECP-mode data
Notes:	data written or DMAed to this port are buffered in the FIFO and
	  transmitted to the peripheral using an ECP hardware handshake;
	  PORT 027Ah bit 5 must be clear to enable the forward transfer
	  direction
	when PORT 027Ah bit 5 is set (reverse transfer), data is read from the
	  peripheral and placed in the FIFO, from which it may be read by
	  reading this port
SeeAlso: #P0917,#P0923,#P0920

Bitfields for ECP test FIFO:
Bit(s)	Description	(Table P0920)
 7-0	test FIFO data
Notes:	writes to this port write to the FIFO, reads from this port read from
	  the FIFO, without actually transferring any data out the parallel
	  port; FIFO overruns and underruns are ignored, simply reading/writing
	  over the same slots again and again
	the ECR "full" and "empty" bits always keep track of the current state
	  of the FIFO; the write threshold can be determined by filling the
	  FIFO and then reading a byte at a time until a service interrupt is
	  set in the ECR.  Similarly, the read threshold can be determined by
	  emptying the FIFO, setting the direction bit in PORT 027Ah, and
	  writing a byte at a time until a service interrupt is set.
SeeAlso: #P0917,#P0923,#P0919

Bitfields for ECP configuration A:
Bit(s)	Description	(Table P0921)
 7-4	(read-only) implementation identification
	bit 7: ISA-style interrupt
	bit 4: eight-bit implementation
 3-0	reserved
Note:	this register can only be accessed when the Extended Control
	  Register bits 7-5 are set to 111
SeeAlso: #P0923,#P0922,#P0917,#P0919,#P0920

Bitfields for ECP configuration B:
Bit(s)	Description	(Table P0922)
 7	reserved (0)
 6	IRQ status (reflects actual value driven onto either IRQ5 or IRQ7; used
	  to check for interrupt conflicts)
 5-0	reserved (0)
Notes:	this register can only be accessed when the Extended Control
	  Register bits 7-5 are set to 111
	bit 4 of the parallel control port (027Ah/037Ah) must be cleared before
	  bit 6 will show the interrupt status
SeeAlso: #P0923,#P0921

Bitfields for ECP Extended Control Register (ECR):
Bit(s)	Description	(Table P0923)
 7-5	ECP mode
	000 ISA-compatible
	001 PS/2-compatible (bidirectional port)
	010 ISA-compatible FIFO
	011 ECP
	100 reserved
	101 reserved
	110 test
	111 configuration
 4	disable ERROR interrupts
 3	enable DMA
	when bit 3 set and bit 2 clear, an interrupt is generated on the DMA
	  terminal-count condition; this bit must be cleared to reset the TC
	  interrupt
 2	disable FIFO/TerminalCount service interrupts
 1	(read-only) FIFO is full
 0	(read-only) FIFO is empty
Notes:	if the port is currently in modes 000 or 001, it may be switched into
	  any other mode; if it is in a mode other than 000 or 001, it must
	  first be switched into either mode 000 or 001 before selecting a mode
	  other than one of those two
	if currently in an extended forward mode (010-111 and direction bit
	  clear), software should wait for the FIFO to clear before switching
	  back to modes 000 or 001
	if a FIFO overrun or underrun occurs, BOTH bits 1 and 0 are set; to
	  clear the FIFO error condition, switch the port to mode 000 or 001
SeeAlso: #P0921,#P0922,#P0919
----------P06800681--------------------------
PORT 0680-0681 - Microchannel POST Diagnostic (write only)

0680  -W  Microchannel POST Diagnostic
0681  -W  secondary MCA POST diagnostic
----------P06A006A8--------------------------
PORT 06A0-06A8 - non-standard COM port addresses
Range:	selectable from 0280, 0288, 0290, 0298, 06A0, 06A8
Note:	V20-XT by German magazine c't
----------P06A806AF--------------------------
PORT 06A8-06AF - non-standard COM port addresses
Range:	selectable from 0280, 0288, 0290, 0298, 06A0, 06A8
Note:	V20-XT by German magazine c't
----------P06E206E3--------------------------
PORT 06E2-06E3 - data aquisition (adapter 1)
----------P06E8------------------------------
PORT 06E8 - S3 86C928 video controller (ELSA Winner 1000)
----------P06E806EF--------------------------
PORT 06E8-06EF - 8514/A and compatible (e.g. ATI Graphics Ultra) - HORZ DISPLYD
SeeAlso: PORT 02E8h-02EFh,PORT 0AE8h,PORT 96E8h,PORT 9AE8h

06E8w -W  CRT control: horizontal displayed
----------P0746------------------------------
PORT 0746 - Gravis Ultra Sound by Advanced Gravis - BOARD VERSION / MIXER
SeeAlso: PORT 0240h-024Fh,PORT 0340h-034Fh

0746  R-  board version (rev 3.7+)
		FFh	  Pre 3.6 boards, ICS mixer NOT present
		05h	  Rev 3.7 with ICS Mixer. Some R/L: flip problems.
		06h-09h	  Revision 3.7 and above. ICS Mixer present
		0Ah-	  UltraMax. CS4231 present, no ICS mixer
0746  -W  Mixer Control Port
----------P0778077A--------------------------
PORT 0778-077A - Intel 82091AA - ECP-mode PARALLEL PORT
Range:	PORT 0678h or PORT 0378h, depending on the base address of the parallel
	  port (0278h or 0378h)
SeeAlso: PORT 0378h,PORT 0678h,PORT 07BCh

0378  RW  (when ECR bits 7-5=011) ECP Address/RLE FIFO (see #P0917)
	(this is the same address normally used for parallel port data)
0778  RW  (when ECR bits 7-5=010) standard parallel port data FIFO (see #P0918)
0778  RW  (when ECR bits 7-5=011) ECP data FIFO (see #P0919)
0778  RW  (when ECR bits 7-5=110) test FIFO (see #P0920)
0778  RW  (when ECR bits 7-5=111) ECP configuration A (see #P0921)
0779  RW  (when ECR bits 7-5=111) ECP configuration B (see #P0922)
077A  RW  extended control register (ECR) (see #P0923)
----------P07900793--------------------------
PORT 0790-0793 - cluster (adapter 1)
----------P07BC07BE--------------------------
PORT 07BC-07BE - Intel 82091AA - ECP-mode PARALLEL PORT
SeeAlso: PORT 03BCh,PORT 0678h,PORT 0778h

03BC  RW  (when ECR bits 7-5=011) ECP Address/RLE FIFO (see #P0917)
	(this is the same address normally used for parallel port data)
07BC  RW  (when ECR bits 7-5=010) standard parallel port data FIFO (see #P0918)
07BC  RW  (when ECR bits 7-5=011) ECP data FIFO (see #P0919)
07BC  RW  (when ECR bits 7-5=110) test FIFO (see #P0920)
07BC  RW  (when ECR bits 7-5=111) ECP configuration A (see #P0921)
07BD  RW  (when ECR bits 7-5=111) ECP configuration B (see #P0922)
07BE  RW  extended control register (ECR) (see #P0923)
----------P080008FF--------------------------
PORT 0800-08FF - I/O port access registers for extended CMOS RAM or SRAM
		(256 bytes at a time)
Note:	sometimes plain text can be seen here
--------X-P080008FF--------------------------
PORT 0800-08FF - reserved for EISA system motherboard
----------P0A200A23--------------------------
PORT 0A20-0A23 - Token Ring (adapter 1)
0A24-0A27 - Token Ring (adapter 2)
----------P0A79------------------------------
PORT 0A79 - Plug-and-Play - WRITE DATA PORT
Desc:	all data written to the Plug-and-Play configuration registers is
	  written to this port, including the configuration byte which
	  indicates the I/O port from which data is to be read when reading
	  the configuration registers
SeeAlso: PORT 0279h

0A79  -W  Plug-and-Play data writes
---------------------------------------------
Ports List, part 3 of 3
Copyright (c) 1989,1990,1991,1992,1993,1994,1995,1996,1997,1998,1999 Ralf Brown
----------P0AD60AD7--------------------------
PORT 0AD6-0AD7 - Chips & Technologies PC Video (82C9001A) - CONTROL REGISTERS
Range:	Address determined by status of CS# input at RESET. If CS# input is
	  low on falling edge of RESET, then address is fixed at 0AD6-0AD7h;
	  otherwise, the programmable address is used.
Note:	register FFh is write-only and all other registers are disabled if
	  register FFh bit 0 is cleared.
SeeAlso: PORT 03D4h

0AD6  -W  index for accesses to data port (see #P0924)
0AD7  RW  data port

(Table P0924)
Values for Chips & Technologies PC Video (82C9001A) control registers:
 00h	I/O Address Register (see #P0925)
 01h	Memory Access Register (see #P0926)
 06h	Linear Memory Base Address Register (see #P0927)
 07h	Luminance Data Mask Register (enabled by register 01h bit 4)
	(0 prevents data modification during video data acquisition
	  in corresponding bit position)
 08h	Chrominance Data Mask Register (enabled by register 01h bit 4)
	(0 prevents data modification during video data acquisition
	  in corresponding bit position)
 09h	Interupt Mask/Polling Register (see #P0928)
 10h	General Purpose I/O Register 0
 11h	General Purpose I/O Register 1
 12h	General Purpose I/O Register 2
 13h	General Purpose I/O Register 3
 18h	General Purpose I/O Control Register (see #P0929)
 20h	Video Acquisition Mode Register (see #P0930)
 21h	Acquisition Window Control Register (see #P0931)
 22h	Acquisition Window X-Start Low Byte Register
	(X-Start is measured in input pixel clocks, referenced to trailing
	  edge of video Hsync)
 23h	Acquisition Window X-Start High Byte Register (two high order bits)
 24h	Acquisition Window Y-Start Low Byte Register
	(Y-Start is measured in input lines, referenced to trailing edge of
	  video Vsync + V Start Adjust (register 30h))
 25h	Acquisition Window Y-Start High Byte Register (two high order bits)
 26h	Acquisition Window X-End Low Byte Register
	(X-End is measured in input pixel clocks, referenced to trailing edge
	  of video Hsync)
 27h	Acquisition Window X-End High Byte Register (two high order bits)
 28h	Acquisition Window Y-End Low Byte Register
	(measured in input lines, referenced to trailing edge of
	  video Vsync + V Start Adjust (register 30h))
 29h	Acquisition Window Y-End High Byte Register (two high order bits)
 2Ah	Acquisition Write Address Low Register
	(points to frame memory location where video acquisition starts;
	  at end of video line reset to beginning and offset of 1024 bytes
	  is added for start address of next line)
 2Bh	Acquisition Write Address Middle Register
 2Ch	Acquisition Write Address High Register (4 high order bits)
 2Dh	Acquisition Horizontal-Scaling Register (see #P0932)
 2Eh	Acquisition Vertical-Scaling Register (see #P0933)
 2Fh	Scaling Field Adjust Register (see #P0934)
 30h	Input Video Start Adjust (see #P0935)
 38h	Scaling Control Register (see #P0936)
 40h	Display Area Control Register (see #P0937)
 41h	Display Window X-Start Low Byte Register
	(defines start of horizontal display window; measured in VGA pixel
	  clocks, referenced to trailing edge of VGA Hsync)
 42h	Display Window X-Start High Byte Register (three high order bits)
 43h	Display Window Y-Start Low Byte Register
	(defines start of vertical display window; measured in VGA lines,
	  referenced to trailing edge of VGA Vsync)
 44h	Display Window Y-Start High Byte Register (two high order bits)
 45h	Display Window X-End Low Byte Register
	(defines end of horizontal display window; measured in VGA pixel
	  clocks, referenced to trailing edge of VGA Hsync)
 46h	Display Window X-End High Byte Register (three high order bits)
 47h	Display Window Y-End Low Byte Register
	(defines start of vertical display window; measured in VGA lines,
	  referenced to trailing edge of VGA Vsync)
 48h	Display Window Y-End High Byte Register (two high order bits)
 49h	Display Window X-Panning Low Register
	(defines display buffer column address times 2, loaded during data
	  transfer cycle in VRAMs; for 4:1:1 encoding bit 0 should be set to 0)
 4Ah	Display Window Y-Panning Low Register
	  (defines display buffer row, loaded for first active display line)
 4Bh	Display Window X/Y-Panning High Register (see #P0938)
 4Ch	Shift Clock Start Register (7 bits)
	  (defines end of display blank relative to VGA Hsync trailing edge)
 4Dh	Sync Polarity/Zoom Register (see #P0939)
 4Eh	VGA Color Compare Register (see #P0940)
 4Fh	VGA Color Mask Register (see #P0941)
 50h	Display Window Interlace Control (see #P0942)
 FFh	Version/Global Enable Register (see #P0943)

Bitfields for Chips & Technologies PC Video (82C9001A) I/O Address Register:
Bit(s)	Description	(Table P0925)
 7-1	I/O address bits 7-1
	(These bits are compared with address inputs (A7-1) to detect
	  valid I/O address. If CS# is low on RESET, this register is
	  initialized to D6h. If CS# is high on RESET, this register is
	  loaded with value present on data inputs (D7-1) during first
	  I/O on the chip (IOWR# = 0 and CS# = 0).)
 0	reserved
SeeAlso: #P0924,#P0926,#P0927

Bitfields for Chips & Technologies PC Video (82C9001A) Memory Access Register:
Bit(s)	Description	(Table P0926)
 7-5	reserved
 4	VRAM write mask enable (enables registers 07h and 08h)
 3-0	reserved
SeeAlso: #P0924,#P0925,#P0927,#P0928

Bitfields for Chips & Technologies PC Video (82C9001A) Linear Memory Base:
Bit(s)	Description	(Table P0927)
 7-5	reserved
 4	reserved (1)
 3-0	linear memory space starting address (in 1MB units)
SeeAlso: #P0924,#P0925

Bitfields for Chips & Technologies PC Video (82C9001A) Interupt Mask/Polling:
Bit(s)	Description	(Table P0928)
 7-6	reserved
 5	VGA Hsync status
 4	VGA Vsync status
 3	video field status
	0 = even
	1 = odd
 2	video Vsync status
 1	video odd Vsync interrupt enable
 0	video even Vsync interrupt enable
SeeAlso: #P0924,#P0221

Bitfields for Chips & Technologies PC Video (82C9001A) General Purpose I/O:
Bit(s)	Description	(Table P0929)
 7	general purpose I/O 3
	0 = output decode of register 13h on GPIO3
	1 = reserved
 6	general purpose I/O 2
	0 = output decode of register 12h on GPIO2
	1 = reserved
 5	general purpose I/O 1
	0 = output "PLLHREF" on GPIO1
	1 = output decode of register 11h on GPIO1
 4	general purpose I/O 0
	0 = output decode of register 10h on GPIO0
	1 = reserved
 3	reserved
 2	I2C bus read back
	  (status of I2CI pin when I2CK pin goes from 0 to 1)
 1	I2C bus data (refer to I2C.LST for more details on the I2C bus)
 0	I2C bus clock
SeeAlso: #P0924

Bitfields for Chips & Technologies PC Video (82C9001A) Video Acquisition Mode:
Bit(s)	Description	(Table P0930)
 7	video input is non-interlace
 6	reserved
 5	video input Vsync polarity is active high
 4	video input Hsync polarity is active high
 3	video input even/odd acquire
	0 = even (first) field
	1 = odd (second) field
 2	video acquire field/frame
	0 = frame
	1 = field (interlaced mode only)
 1	video acquisition single/continuous
	0 = continuous
	1 = single (bit 0 cleared at the end)
 0	video acquisition start/stop
	0 = stop (allows CPU access to frame buffer)
	1 = start
SeeAlso: #P0924

Bitfields for Chips & Technologies PC Video (82C9001A) Window Control:
Bit(s)	Description	(Table P0931)
 7	invert field polarity
 6	select external field
	0 = internal field (field detected 1 XCLK after trailing edge of
	  XVSYNC input bit)
	1 = field bit input through XFLD pin and reclocked by XCLK before
	  XFLD use (XFLD input transition after trailing edge of XVSYNC; 
	  0 on XFLD = even field, 1 on XFLD = odd field)
 5	multiplexing ratio for luminance and chrominance input data
	  (active if bit 4 = 0)
	0 = 4:1:1 / 2:1:1
	1 = 4:2:2
 4	video input data multiplexing
	0 = multiplexed (YUV)
	1 = non-multiplexed (RGB)
 3	video input vertical scaling enable
 2	video input horizontal scaling enable
 1	video capture
	0 = inside cropping window
	1 = outside cropping window
 0	video input cropping enable
SeeAlso: #P0924,#P0935,#P0937

Bitfields for Chips & Technologies PC Video (82C9001A) Horizontal Scaling:
Bit(s)	Description	(Table P0932)
 7-6	reserved
 5-0	number of pixels written per 64 input pixels
	(valid values are 1-63; enabled by register 21h bit 2)
SeeAlso: #P0924,#P0933,#P0934

Bitfields for Chips & Technologies PC Video (82C9001A) Vertical Scaling:
Bit(s)	Description	(Table P0933)
 7	reserved
 6-0	number of pixels written per 64 input pixels
	(valid values are 1-63; enabled by register 21h bit 3)
SeeAlso: #P0924,#P0932,#P0934

Bitfields for Chips & Technologies PC Video (82C9001A) Scaling Field Adjust:
Bit(s)	Description	(Table P0934)
 7	reserved
 6-0	modify scaling value for odd field during acquisition
	(diagnostic register, set to same value as register 2Eh for normal
	  operation)
SeeAlso: #P0924,#P0932,#P0936

Bitfields for Chips & Technologies PC Video (82C9001A) Input Video Start:
Bit(s)	Description	(Table P0935)
 7-6	reserved
 5-0	number of scan lines from trailing edge of video Vsync to start of
	  active video frame
	(should always be programmed with non-zero value)
SeeAlso: #P0924,#P0931

Bitfields for Chips & Technologies PC Video (82C9001A) Scaling Control:
Bit(s)	Description	(Table P0936)
 7	fast write enable
 6-5	reserved (0 for normal operation)
 4	Y-max enable
	(prevents wrap around of memory Y-address; should be enabled for
	  PAL video data)
 3	X-max enable (prevents wrap around of memory X-address)
 2	Y-over-write mode
	(should be set to 1 when vertical scaling less than 1/2 to reduce
	  motion artifacts)
	0 = normal scaling
	1 = modified scaling
 1-0	chrominance multiplex adjust bits
	(adjust to maintain luminance/chrominance alignment)
SeeAlso: #P0924,#P0934

Bitfields for Chips & Technologies PC Video (82C9001A) Display Area Control:
Bit(s)	Description	(Table P0937)
 7-6	skew between VGA data input and multiplexer control output
	00 = 2 VGA clock delay
	01 = 3 VGA clock delay
	10 = 4 VGA clock delay
	11 = 5 VGA clock delay
 5	both X-Y window and color key area (function 3)
	(does not exist if bit 0 = 0 or bit 1 = 0)
	0 = display VGA
	1 = display frame buffer data
 4	color key only area (function 2)
	(does not exist if bit 1 = 0)
	0 = display VGA
	1 = display frame buffer data
 3	X-Y window only area (function 1)
	(does not exist if bit 0 = 0)
	0 = display VGA
	1 = display frame buffer data
 2	non-color key or X-Y window area (function 0)
	0 = display VGA
	1 = display frame buffer data
 1	overlay window using color keying enable
 0	overlay window using X-Y window enable
SeeAlso: #P0924,#P0931

Bitfields for Chips & Technologies PC Video (82C9001A) X/Y-Panning High:
Bit(s)	Description	(Table P0938)
 7-5	reserved
 4	high bit of row offset (register 4Ah)
 3-1	reserved
 0	high bit of column offset (register 49h)
SeeAlso: #P0924

Bitfields for Chips & Technologies PC Video (82C9001A) Sync Polarity/Zoom:
Bit(s)	Description	(Table P0939)
 7-6	reserved
 5	VGA Vsync polarity is active high
 4	VGA Hsync polarity is active high
 3-2	vertical zoom
	00 = no zoom
	01 = 2x
	10 = 4x
	11 = 8x
 1-0	horizontal zoom (same values as vertical zoom)
SeeAlso: #P0924

Bitfields for Chips & Technologies PC Video (82C9001A) VGA Color Compare:
Bit(s)	Description	(Table P0940)
 7-0	defines values VGA data must have for color match
	0 = VGA data must be 0
	1 = VGA data must be 1
SeeAlso: #P0924,#P0941

Bitfields for Chips & Technologies PC Video (82C9001A) VGA Color Mask Register:
Bit(s)	Description	(Table P0941)
 7-0	defines bit position where VGA and color value must match
	0 = VGA data must match color value
	1 = don't care
SeeAlso: #P0924,#P0940

Bitfields for Chips & Technologies PC Video (82C9001A) Interlace Control:
Bit(s)	Description	(Table P0942)
 7-5	reserved
 4	replicate odd/even field (if bit 3 = 1)
	0 = odd
	1 = even
 3	replicate field
	0 = do not replicate
	1 = replicate even/odd (depending on bit 4)
 2	invert display window field signal polarity (if bit 0 = 1)
	0 = do not modify
	1 = invert
 1	select external display window field signal (if bit 0 = 1)
	0 = internal
	1 = VFLD input
 0	display window is interlaced
SeeAlso: #P0924

Bitfields for Chips & Technologies PC Video (82C9001A) Version/Global Enable:
Bit(s)	Description	(Table P0943)
 7-4	PC Video version number
 3	reserved
 2	IOWR# delay (write-only)
	0 = IOWR# input delayed inside chip by 2 XCLK cycles
	1 = IOWR# input not delayed
 1	enable memory (write-only)
 0	PC Video global enable (write-only)
	0 = index register and register FFh are write only and all other
	  registers are disabled
	1 = all registers are read/write
SeeAlso: #P0924
----------P0AE20AE3--------------------------
PORT 0AE2-0AE3 - cluster (adapter 2)
----------P0AE8------------------------------
PORT 0AE8 - S3 86C928 video controller (ELSA Winner 1000)
----------P0AE80AEF--------------------------
PORT 0AE8-0AEF - 8514/A and compatible (e.g. ATI Graphics Ultra) - HSYNC START

0AE8w -W  CRT control: horizontal sync start
----------P0B900B93--------------------------
PORT 0B90-0B93 - cluster (adapter 2)
----------P0C00------------------------------
PORT 0C00 - EISA??? - PAGE REGISTER

0C00  RW  page register to write to SRAM or I/O
--------X-P0C000CFF--------------------------
PORT 0C00-0CFF - reserved for EISA system motherboard
----------P0C7C------------------------------
PORT 0C7C		bit 7-4 (Compaq)
--------X-P0C800C83--------------------------
PORT 0C80-0C83 - EISA system board ID registers

0C80  R-  bit 7: unused (0)
	  bits 6-2: manufacturer ID, first compressed ASCII char
	  bits 1-0: manufacturer ID, second compressed ASCII char (high)
0C81  R-  bits 7-5: manufacturer ID, second compressed ASCII char (low)
	  bits 4-0: manufacturer ID, third compressed ASCII char
0C82  R-  reserved for manufacturer's use
0C83  R-  bits 7-3: reserved for manufacturer's use
	  bits 2-0: EISA bus version
--------X-P0CF80CFF--------------------------
PORT 0CF8-0CFF - PCI Configuration Mechanism 1 - Configuration Registers
SeeAlso: PORT 0CF8h"Mechanism 2"

0CF8d -W  configuration address port (see #P0944)
0CFCd RW  configuration data port (when PORT 0CF8h bit 31 is set)

Bitfields for PCI configuration address port:
Bit(s)	Description	(Table P0944)
 1-0	reserved (00)
 7-2	configuration register number (see #00878)
 10-8	function
 15-11	device number
 23-16	bus number
 30-24	reserved (0)
 31	enable configuration space mapping
Note:	configuration registers are considered DWORDs, so the number in bits
	  7-2 is the configuration space address shifted right two bits
SeeAlso: #P0945
--------X-P0CF80CFA--------------------------
PORT 0CF8-0CFA - PCI Configuration Mechanism 2 - Configuration Registers
Notes:	this configuration mechanism is deprecated as of PCI version 2.1;
	  only mechanism 1 should be used for new systems
	to access the configuration space, write the target bus number to
	  the Forward Register, then write to the Configuration Space
	  Enable register, and finally read or write the appropriate I/O
	  port(s) in the range C000h to CFFFh (where Cxrrh accesses location
	  'rr' in physical device 'x's configuration data)
	the Intel "Saturn" and "Neptune" chipsets use configuration mechanism 2
SeeAlso: PORT 0CF8h"Mechanism 1",PORT C000h"PCI Configuration",PORT 0CFBh

0CF8  RW  Configuration Space Enable (CSE) (see #P0945)
0CFA  RW  Forward Register (selects target bus number)

Bitfields for PCI Configuration Space Enable:
Bit(s)	Description	(Table P0945)
 0	Special Cycle Enable (SCE)
 3-1	target function number (PCI logical device within physical device)
 7-4	key (non-zero to allow configuration)
SeeAlso: #P0944
----------P0CF9------------------------------
PORT 0CF9 - Intel chipsets - TURBO/RESET CONTROL REGISTER
Notes:	this port can only be accessed via 8-bit IN or OUT instructions by
	  the CPU
	supported by the Intel "Saturn" and "Neptune" (82434NX) chipsets,
	  the Intel 82454KX/GX (450GX chipset), Intel 82420EX chipset, etc.
SeeAlso: PORT C051h,#01055,#01239

0CF9  RW  reboot system, optionally selecting de-turbo mode (see #P0946)

Bitfields for Intel 82420EX turbo/reset control register:
Bit(s)	Description	(Table P0946)
 7-4	reserved (0)
 3	(450KX/GX only) enable CPU BIST on reset
 2	reset CPU
 1	reset mode
	0 soft reset
	1 hard reset
 0	deturbo mode
Note:	when resetting the CPU, two writes are required: the first sets the
	  state of bit 1 while keeping bit 2 cleared, and the second sets
	  bit 2; the reset occurs on bit 2's transition from 0 to 1.
SeeAlso: PORT C051h
----------P0CFB------------------------------
PORT 0CFB - Intel 82434NX (Neptune) - PCI MECHANISM CONTROL REGISTER
Note:	not present on the 82434LX (Mercury), which supports only mechanism #2
SeeAlso: PORT 0CF8h

0CFB  RW  specify which PCI access mechanism is to be enabled

Bitfields for Intel 82434NX PCI mechanism control register:
Bit(s)	Description	(Table P0947)
 7-1	reserved
 0	PCI Configuration Access Mechanism Select
	=0 use PCI configuration access mechanism #2 (0CF8/0CFA) (default)
	=1 use PCI configuration access mechanism #1 (0CF8/0CFC)
--------s-P0E800E83--------------------------
PORT 0E80-0E83 - Gravis Ultra Sound Daughter Card by Advanced Gravis
Range:	dipswitch selectable from PORT 0530h-0533h, PORT 0604h-0607h,
	  PORT 0E80h-0E83h, and PORT 0F40h-0F43h
--------s-P0E800E87--------------------------
PORT 0E80-0E87 - Windows Sound System
Range:	PORT 0530h-0537h,PORT 0604h-060Bh,PORT 0E80h-0E87h,PORT 0F40h-0F47h
SeeAlso: PORT 0530h"Sound System"
--------V-P0EE8------------------------------
PORT 0EE8 - S3 86C928 video controller (ELSA Winner 1000)
--------V-P0EE80EEF--------------------------
PORT 0EE8-0EEF - 8514/A and compatible (e.g. ATI Graphics Ultra) - HSYNC WIDTH

0EE8w -W  CRT control: horizontal sync width
--------s-P0F400F43--------------------------
PORT 0F40-0F43 - Gravis Ultra Sound Daughter Card by Advanced Gravis
Range:	dipswitch selectable from PORT 0530h-0533h, PORT 0604h-0607h,
	  PORT 0E80h-0E83h, and PORT 0F40h-0F43h
--------s-P0F400F47--------------------------
PORT 0F40-0F47 - Windows Sound System
Range:	PORT 0530h-0537h,PORT 0604h-060Bh,PORT 0E80h-0E87h,PORT 0F40h-0F47h
SeeAlso: PORT 0530h"Sound System"
--------s-P0F8D------------------------------
PORT 0F8D - OPTi 82C750 (Vendetta) - AUDIO MODULE BASE ADDRESS REGISTER
SeeAlso: PORT 0F8Eh,PORT 0530h"Vendetta"

0F8D  RW  "MCBase" base register (see #P0948)

Bitfields for OPTi "Vendetta" (82C750) audio module base register:
Bit(s)	Description	(Table P0948)
 7	index/data port access protection disable
 6-5	reserved
 4-0	index/data port address bits 8-4
	  (bits 15-9 = 0000111; bits 3-0 = 1110 for index port, data port +1)
SeeAlso: #P0949
----------P0F8E0F8F--------------------------
PORT 0F8E-0F8F - OPTi "Vendetta" (82C750) CHIPSET - Audio Module Data Registers
Range:	The I/O address range is selectable using port 0F8Dh from among
	  0ExE-0ExF and 0FxE-0FxF
SeeAlso: PORT 0F8Dh,PORT 0530h"Vendetta"

0F8E  RW  "MCIdx" index register (see #P0949)
0F8F  RW  "MCData" data register

(Table P0949)
Values for OPTi "Vendetta" (82C750) Audio Module configuration registers:
 00h	disable
 01h	base/type configuration register (see #P0950)
 02h	reserved
 03h	Sound Blaster/Windows Sound System configuration register (see #P0951)
 04h	user programmable general purpose register (see #P0952)
 05h	option register (see #P0953)
 06h	MIDI interface register (write-only) (see #P0954)
 07h	semaphore software register
 08h	reserved
 09h	test control register 1 (see #P0955)
 0Ah	test control register 2 (see #P0956)
 0Bh	status register (read-only) (see #P0957)
 0Ch	test register (see #P0958)
 0Dh	PNP status register (read-only) (see #P0959)
 0Eh	PNP card select number register (read-only)
 0Fh	PNP read port address register (read-only)
 10h	volume control register (see #P0960)
 11h	reserved (serial EEPROM)
 12h	CONFIG status register (see #P0961)
 13h	FM control register (see #P0962)
 14h	reserved (GPIO control)
 15h	serial audio control register 0 (see #P0963)
 16h	serial audio control register 1 (see #P0964)
 17h	reserved

Bitfields for OPTi "Vendetta" Audio Module base/type configuration register:
Bit(s)	Description	(Table P0950)
 7	Sound Blaster base I/O address
	0 = 220h
	1 = 240h
 6	reserved
 5-4	Windows Sound System base I/O address
	00 = 530h
	01 = E80h
	10 = F40h
	11 = 640h
 3-1	reserved
 0	game port enable
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module SB/WSS configuration register:
Bit(s)	Description	(Table P0951)
 7	reserved
 6	reserved (0 for normal WSS operation)
 5-3	digital audio processor IRQ
	000 = disable
	001 = IRQ7
	010-100 = IRQ9-IRQ11
	101 = IRQ5
	110-111 = reserved
 2-0	digital audio processor DMA
	000 = disable
	001-010 = QRQ0-DRQ1
	011 = DRQ3
	100 = disable, DRQ1 (if dual channel DMA mode)
	101 = DRQ0, DRQ1 (if dual channel DMA mode)
	110 = DRQ1, DRQ0 (if dual channel DMA mode)
	111 = DRQ3, DRQ0 (if dual channel DMA mode)
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module user programmable general purpose:
Bit(s)	Description	(Table P0952)
 7-6	playback FIFO flow
	00 = empty
	01 = full-2
	10 = full-4
	11 = not full
 5-4	OPL select
	00 = OPL2
	01 = OPL3
	10 = OPL4
	11 = OPL5
 3	D/A controller zero
	0 = hold
	1 = clear
 2	audio enable
 1-0	Sound Blaster version
	00 = 2.1
	01 = 1.5
	10 = 3.2
	11 = 4.4
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module option register:
Bit(s)	Description	(Table P0953)
 7-6	reserved
 5	codec expanded mode enable
	  (must be set to access expanded mode codec indirect registers
	  10h-1Fh)
 4	Sound Blaster ADPCM enable
 3	Sound Blaster command FIFO enable
 2	Sound Blaster Pro mixer voice volume emulation volume effect enable
 1	DMA watchdog timer enable
 0	reserved
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module MIDI interface register:
Bit(s)	Description	(Table P0954)
 7	MPU-401 enable
 6-5	MPU-401 base address
	00 = 330h
	01 = 320h
	10 = 310h
	11 = 300h
 4-3	MPU-401 IRQ
	00 = IRQ9
	01 = IRQ10
	10 = IRQ5
	11 = IRQ7
 2	reserved
 1	Windows Sound System mode enable
 0	Sound Blaster mode enable
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module test control register 1:
Bit(s)	Description	(Table P0955)
 7	digital power-down
 6	analog power-down
 5-2	reserved
 1	software reset enable
 0	reserved
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module test control register 2:
Bit(s)	Description	(Table P0956)
 7	playback reset
 6	capture reset
 3	PNP test
 2-0	reserved
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module status register:
Bit(s)	Description	(Table P0957)
 7	playback DMA pending
 6	capture DMA pending
 5	MPU interrupt pending
 4	reserved
 3	capture interrupt pending
 2	playback interrupt pending
 1	playback FIFO empty
 0	capture FIFO empty
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module test register:
Bit(s)	Description	(Table P0958)
 7-5	reserved
 4	digital test output high/low byte (write-only)
 3-0	digital test output select (write-only)
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module PNP status register:
Bit(s)	Description	(Table P0959)
 7	CSN not 0, active high
	1 = CSN assigned by PNP configuration manager
 6-5	reserved
 4	audio module logical device enable
 3	1 = audio module PNP logic in CONFIG mode
 2	1 = audio module PNP logic in ISOLATE mode
 1	1 = audio module PNP logic in SLEEP mode
 0	1 = audio module PNP logic in WAIT4KEY mode
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module volume control register:
Bit(s)	Description	(Table P0960)
 7-4	reserved
 3	master volume mute
 2-0	reserved
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module CONFIG status register:
Bit(s)	Description	(Table P0961)
 7	reserved
 6	ASIO enable
 5-4	reserved
 3-0	chip revision ID (read-only)
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module FM control register:
Bit(s)	Description	(Table P0962)
 7-3	reserved
 2	mega bass enable
 1	enhanced FM feature OPTi mode enable
 0	external FM enable
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module serial audio control register 0:
Bit(s)	Description	(Table P0963)
 7-6	FDAC clock controller
	00 = reserved
	01 = internal FM
	10 = reserved
	11 = external serial audio
 5-2	reserved
 1	FDAC data
	0 = internal FM
	1 = external serial audio
 0	reserved
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module serial audio control register 1:
Bit(s)	Description	(Table P0964)
 7	ASIO reset
 6	ASIO test
 5-4	reserved
 3	SCLK polarity
	0 = reverse
	1 = no change
 2	FSYNC polarity
	0 = reverse
	1 = no change
 1-0	reserved
SeeAlso: #P0949
----------P0xx00xxF--------------------------
PORT 0xx0-0xxF - Intel 82595TX - ISA/PCMCIA Ethernet Controller
Range:	at any multiple of 16 in first 1024 I/O addresses

+000  RW  command register (see #P0965)
--- I/O bank 0 ---
+001  RW  status register (see #P0966)
+002  RW  id register (see #P0967)
+003  RW  mask register (see #P0968)
+004  RW  RCV CAR/BAR low
+005  RW  RCV CAR/BAR high
+006  RW  RCV STOP REG low
+007  RW  RCV STOP REG high
+008  RW  RCV copy treshold REG
+009  RW  reserved
+00A  RW  XMT CAR/BAR low
+00B  RW  XMT CAR/BAR high
+00C  RW  host address reg/32-bit I/O (byte 0) low
+00D  RW  host address reg/32-bit I/O (byte 1) high
+00E  RW  local memory/32-bit I/O (byte 2) IO port low
+00F  RW  local memory/32-bit I/O (byte 3) IO port high
--- I/O bank 1 ---
+001  RW  bank 1 register 1 (see #P0969)
+002  RW  int select register (see #P0970)
+003  RW  I/O mapping register (see #P0971)
+004  RW  reserved
+005  RW  reserved
+006  RW  reserved
+007  RW  RCV BOF treshold reg
+008  RW  RCV lower limit reg high byte
+009  RW  RCV upper limit reg high byte
+00A  RW  XMT lower limit reg high byte
+00B  RW  XMT upper limit reg high byte
+00C  RW  FLASH control register (see #P0972)
+00D  RW  bank 1 register 13 (see #P0973)
+00E  RW  reserved
+00F  RW  reserved
--- I/O bank 2 ---
+001  RW  bank 2 register 1 (see #P0974)
+002  RW  bank 2 register 2 (see #P0975)
+003  RW  bank 2 register 3 (see #P0976)
+004  RW  individual address register 0
+005  RW  individual address register 1
+006  RW  individual address register 2
+007  RW  individual address register 3
+008  RW  individual address register 4
+009  RW  individual address register 5
+00A  RW  bank 2 register 10 (see #P0977)
+00B  RW  RCV NO resource counter
+00C  RW  IAPROM IO port
+00D  RW  reserved
+00E  RW  reserved
+00F  RW  reserved
------

Bitfields for Intel 82595TX command register:
Bit(s)	Description	(Table P0965)
 7-6	bank pointer (if switch bank command written; ignored for other
	  commands)
	00 = bank 0
	01 = bank 1
	10 = bank 2
 5	command (other than transmit) aborted (read-only; should be written 0)
 4-0	(write) command OP code
	00h = switch bank/nop
	03h = MC-setup
	04h = transmit
	05h = TDR
	06h = dump
	07h = diagnose
	08h = RCV enable
	0Ah = RCV disable
	0Bh = RCV stop
	0Dh = abort
	0Eh = reset
	14h = XMT no CRC/SA
	15h = cont XMT test
	16h = set tristate
	17h = reset tristate
	18h = power down
	1Ch = resume XMT list
	1Eh = sel reset
	(read) execution event (MC done, init done, TDR done, DIAG done)
	  (if bank 0 register 1 bit 3 = 1)
SeeAlso: #P0966,#P0968

Bitfields for Intel 82595TX status register:
Bit(s)	Description	(Table P0966)
 7-6	RCV states
 5-4	EXEC states
 3	EXEC INT
 2	TX INT
 1	RX INT
 0	RX STP INT
SeeAlso: #P0965,#P0967,#P0968

Bitfields for Intel 82595TX id register:
Bit(s)	Description	(Table P0967)
 7-6	counter
 5	reserved (1)
 4	auto enable
 3-2	reserved (01)
 1-0	reserved (0)
SeeAlso: #P0965,#P0966,#P0968

Bitfields for Intel 82595TX mask register:
Bit(s)	Description	(Table P0968)
 7-6	reserved
 5	cur/base
 4	32IO/HAR
 3	EXEC mask
 2	TX mask
 1	RX mask
 0	RX STP mask
SeeAlso: #P0965,#P0966,#P0969

Bitfields for Intel 82595TX bank 1 register 1:
Bit(s)	Description	(Table P0969)
 7	tri-st INT
 6	alt RDY tm
 5-2	reserved
 1	host bus wd
 0	reserved
SeeAlso: #P0965,#P0967,#P0970

Bitfields for Intel 82595TX int select register:
Bit(s)	Description	(Table P0970)
 7	FL/BT detect
 6-4	boot EPROM/FLASH decode window
 3	reserved
 2-0	INT select

Bitfields for Intel 82595TX I/O mapping register:
Bit(s)	Description	(Table P0971)
 7-6	reserved
 5-0	I/O mapping window

Bitfields for Intel 82595TX FLASH control register:
Bit(s)	Description	(Table P0972)
 7-6	FLASH page select high
 5-4	FLASH write enable
 3-0	FLASH page select

Bitfields for Intel 82595TX bank 1 register 13:
Bit(s)	Description	(Table P0973)
 7-3	reserved
 2	SMOUT out en
 1	AL RDY test
 0	AL RDY PAS/FL

Bitfields for Intel 82595TX bank 2 register 1:
Bit(s)	Description	(Table P0974)
 7	disc bad fr
 6	TX chn ErStp
 5	TX chn int md
 4	PCMCIA/ISA
 3-1	reserved
 0	TX con proc en

Bitfields for Intel 82595TX bank 2 register 2:
Bit(s)	Description	(Table P0975)
 7-6	loopback
 5	multi IA
 4	no SA ins
 3	length enable
 2	RX CRC InMem
 1	BC DIS
 0	PRMSC mode

Bitfields for Intel 82595TX bank 2 register 3:
Bit(s)	Description	(Table P0976)
 7	test 1
 6	test 2
 5	BNC/TPE
 4	APORT
 3	jabber disable
 2	TPE/AUI
 1	pol/corr
 0	lnk in disable

Bitfields for Intel 82595TX bank 2 register 10:
Bit(s)	Description	(Table P0977)
 7-5	stepping
 4	trnoff enable
 3	EEDO
 2	EEDI
 1	EECS
 0	EESK
--------X-P100010FF--------------------------
PORT 1000-10FF - available for EISA slot 1
----------P12E812EF--------------------------
PORT 12E8-12EF - 8514/A and compatible (e.g. ATI Graphics Ultra) - VERT TOTAL

12E8w -W  CRT control: vertical total
--------V-P12EE------------------------------
PORT 12EE - ATI Mach32 - CONFIGURATION STATUS 0
SeeAlso: PORT 16EEh"Mach32",PORT 42EEh"Mach32",PORT 52EEh"Mach32"
----------P13901393--------------------------
PORT 1390-1393 - cluster (adapter 3)
----------P13C6------------------------------
PORT 13C6 - Compaq - ???
Note:	this port is read by the Compaq MS-DOS 4.0/5.0 CHARSET utility

13C6  R?  Compaq video status??? (see #P0978)

Bitfields for Compaq video status???:
Bit(s)	Description	(Table P0978)
 7	???
 6	flag
 5-3	???
 2-0	status of display???
--------X-P140014FF--------------------------
PORT 1400-14FF - available for EISA slot 1
----------P16E816EF--------------------------
PORT 16E8-16EF - 8514/A and compatible (e.g. ATI Graphics Ultra) - VERT DISPLYD

16E8w -W  CRT control: vertical displayed
--------V-P16EE------------------------------
PORT 16EE - ATI Mach32 - CONFIGURATION STATUS 1
SeeAlso: PORT 12EEh"Mach32",PORT 42EEh"Mach32",PORT 52EEh"Mach32"
--------X-P180018FF--------------------------
PORT 1800-18FF - available for EISA slot 1
----------P1AE81AEF--------------------------
PORT 1AE8-1AEF - 8514/A and compatible (e.g. ATI Graphics Ultra) - VSYNC START

1AE8w -W  CRT control: vertical sync start
--------X-P1C001CFF--------------------------
PORT 1C00-1CFF - available for EISA slot 1
--------d-P1C001CBF--------------------------
PORT 1C00-1CBF -  Adaptec AIC-777x EISA SCSI controller in EISA slot 1
Notes:	Adaptec AIC-777x SCSI controllers have on-board PhaseEngine SCSI
	  sequence processor which executes its instructions from the 2-Kbyte
	  sequencer RAM; it treats all of the CPU-addressable registers as its
	  data memory
	AIC-777x SCSI controllers have special on-board RAM and queue registers
	  for queueing the requests sent from the drivers and BIOS to the
	  PhaseEngine processor
	Adaptec AHA-284x is a VLB SCSI controller based on AIC-7770; it has
	  a serial EEPROM (93C46) for storing various configuration settings
SeeAlso: PORT 0340h-035Fh"Adaptec AHA-152x",PORT xxxxh"Adaptec AIC-78xx"

+000  RW  SCSI sequence control register (SCSISEQ) (see #P0600)
+001  RW  SCSI transfer control register 0 (SXFRCTL0) (see #P0979)
+002  RW  SCSI transfer control register 1 (SXFRCTL1) (see #P0980)
+003  R-  SCSI control signal read  register (SCSISIGI) (see #P0603)
+003  -W  SCSI control signal write register (SCSISIGO) (see #P0604)
+004  RW  SCSI rate control register (SCSIRATE) (see #P0981)
+005  RW  SCSI ID register (SCSIID) (see #P0982)
+006  RW  SCSI latched data low register (SCSIDATL)
	  read/write causes -ACK to pulse
+007  RW  (Wide SCSI) SCSI latched data high register (SCSIDATH)
	  read/write causes -ACK to pulse
+008  RW  SCSI transfer count register (STCNT) (3 bytes long)
+00B  R-  SCSI status register 0 (SSTAT0) (see #P0607)
+00B  -W  clear SCSI interrupt register 0 (CLRSINT0) (see #P0983)
+00C  R-  SCSI status register 1 (SSTAT1) (see #P0609)
+00C  -W  clear SCSI interrupt register 1 (CLRSINT1) (see #P0610)
+00D  R-  SCSI status register 2 (SSTAT2) (see #P0984)
+00E  R-  SCSI status register 3 (SSTAT3) (see #P0612)
+00F  RW  SCSI test control register (SCSITEST) (see #P0985)
+010  RW  SCSI interrupt mode register 0 (SIMODE0) (see #P0616)
+011  RW  SCSI interrupt mode register 1 (SIMODE1) (see #P0617)
+012  RW  SCSI data bus low register (SCSIBUSL)
+013  RW  (Wide SCSI) SCSI data bus high register (SCSIBUSH)
+014d R-  SCSI/host address register (SHADDR)
+018  RW  selection timeout timer  register (SELTIMER) (see #P0986)
+019  RW  selection/reselection ID register (SELID) (see #P0987)
+01F  RW  SCSI block control register (SBLKCTL) (see #P0988)
+020  RW  scratch RAM (64 bytes) (see #P1002)
+060  RW  sequencer control  register (SEQCTL)	(see #P0989)
+061  RW  sequencer RAM data register (SEQRAM)
+062w RW  sequencer address  register (SEQADDR) (see #P0990)
+064  RW  accumulator  register (ACCUM)
+065  RW  source index register (SINDEX)
+066  RW  destination index register (DINDEX)
+069  R-  all ones register (ALLONES)
	  always reads as FFh
+06A  R-  all zeros register (ALLZEROS)
	  always reads as 00h
+06B  R-  flags register (FLAGS) (see #P0991)
	  PhaseEngine processor's flags
+06C  R-  source indirect register (SINDIR)
+06D  -W  destination indirect register (DINDIR)
+06E  RW  function 1 register (FUNCTION1)
+06F  R-  "STACK"
+084  RW  board control register (BCTL) (see #P0992)
+085  RW  bus on/off time register (BUSTIME) (see #P0993)
+086  RW  bus speed register (BUSSPD) (see #P0994)
+087  RW  host control register (HCNTRL) (see #P0995)
+088d RW  host address register (HADDR)
+08C  RW  host counter register (HCNT) (3 bytes long)
+090  RW  sequence control block (SCB) pointer register (SCBPTR)
+091  RW  interrupt status register (INTSTAT) (see #P0996)
+092  R-  hard error register (ERROR) (see #P0997)
+092  -W  clear interrupt status register (CLRINT) (see #P0998)
+093  RW  DMA FIFO control register (DFCNTRL)  (see #P0999)
+094  R-  DMA FIFO status  register (DFSTATUS) (see #P1000)
+099  RW  DMA FIFO data register (DFDAT)
+09A  RW  SCB auto-increment register (SCBCNT) (see #P1001)
+09B  RW  queue in FIFO register (QINFIFO)
	  write places the value into the FIFO, read removes
+09C  R-  queue in count register (QINCNT)
	  number of the SCBs in the queue in
+09D  R-  queue out FIFO register (QOUTFIFO)
	  read removes the value from the FIFO
+09E  R-  queue out count register (QOUTCNT)
	  number of the SCBs in the queue out
+0A0  RW  SCB array (32 bytes) (see #P1003)
+0C0  RW  (AHA-284x) serial EEPROM control register (SEECTL) (see #P1005)
+0C1  RW  (AHA-284x) "STATUS" (see #P1006)
Notes:	the SCSI latched data registers are used to transfer data on the SCSI
	  bus during automatic or manual PIO mode
	in a twin channel configuration the separate register set with the
	  addresses 00h-1Eh exists for each channel
	the SCSI/host address register (SHADDR) holds the host address for the
	  byte about to be transfered on the SCSI bus; it is counted up in the
	  same manner as SCSI transfer count register (STCNT) is counted down
	  and should always be used to determine the address of the last byte
	  transfered since the host address register (HADDR) can be skewed by
	  read ahead
	the source/destination index registers (SINDEX/DINDEX) are used by the
	  PhaseEngine processor to indirectly address the data memory (i.e. the
	  CPU-addressable registers); the data byte addressed can be accessed
	  through the source/destination indirect registers (SINDIR/DINDIR)
	  respectively; the source index register (SINDEX) is auto-incremented
	  on each read from the source indirect register (SINDIR), while the
	  destination index register (DINDEX) is auto-incremented on each write
	  to the destination indirect register (DINDIR)
	the function 1 register (FUNCTION1) is used to convert the SCSI target
	  number to the corresponding bit mask; first, bits 6-4 are written
	  with a number N (other bits seems to be "don't care"), then the
	  register is read back, giving the bit mask having bit N set and all
	  other bits cleared
	the host address register (HADDR) and the host counter register (HCNT)
	  are used for the DMA transfers from/to the host memory
	the SCB pointer register (SCBPTR) selects the 32-byte area of the SCB
	  RAM to be mapped at addresses A0h-BFh
	the queue in/out FIFO registers (QINFIO/QOUTFIFO) hold the queue of
	  the SCB pointer register's (SCBPTR) values for addressing the SCBs
	  sent by CPU to the PhaseEngine processor and returned to CPU (when
	  the associated SCSI command completes) respectively; CPU selects
	  the SCB RAM area via the SCB pointer register (SCBPTR), downloads
	  prepared SCB to addresses A0h-BFh (this requeires the PhaseEngine
	  processor to be paused), then places the SCB pointer value to the
	  queue in FIFO by writing it to the respective register, from which
	  the SCB pointers can be read (and removed) in the FIFO order; the
	  PhaseEngine processor places the SCB pointer of the completed CCB
	  to the queue out FIFO by writing the respective register, and CPU
	  can remove it from the FIFO by reading the register

Bitfields for SCSI transfer control register 0 (SXFRCTL0):
Bit(s)	Description	(Table P0979)
 7	DMA FIFO on? (DFON)
 6	"DFPEXP"
 5	(Ultra SCSI) Ultra SCSI enable (ULTRAEN)
 4	clear SCSI transfer counter (CLRSTCNT)
 3	SCSI PIO enable (SPIOEN)
 2	SCAM enable (SCAMEN)
 1	clear channel (CLRCHN)
 0	reserved
SeeAlso: #P0607,#P0618,#P0620,#P0980,#P0984

Bitfields for SCSI transfer control register 1 (SXFRCTL1):
Bit(s)	Description	(Table P0980)
 7	bit bucket (BITBUCKET)
 6	SCSI counter wrap enable (SWRAPEN)
 5	enable SCSI parity check (ENSPCHK)
 4-3	selection time-out select (STIMESEL)
	00 256 ms
	01 128 ms
	10 64  ms
	11 32  ms
 2	enable selection timer (ENSTIMER)
 1	active negation enable (ACTNEGEN)
 0	SCSI terminator power enable? (STPWEN)
SeeAlso: #P0600,#P0979,#P0986

Bitfields for SCSI rate control register (SCSIRATE):
Bit(s)	Description	(Table P0981)
 7	(Wide SCSI) wide transfer control (WIDEXFER)
 6-4	synchronous transfer rate (SXFR)
 3-0	synchronous offset (SOFS)
SeeAlso: #P0605,#P0984

Bitfields for SCSI ID register (SCSIID):
Bit(s)	Description	(Table P0982)
 7-4	target ID (TID)
 3-0	our ID (OID)
SeeAlso: #P0606,#P0987,#P1012

Bitfields for clear SCSI interrupt register 0 (CLRSINT0):
Bit(s)	Description	(Table P0983)
 7	reserved?
 6	clear selection out done (CLRSELDO)
 5	clear selection in  done (CLRSELDI)
 4	clear selection in progress (CLRSELINGO)
 3	clear SCSI counter wrap (CLRSWRAP)
 2	reserved
 1	clear SCSI PIO ready (CLRSPIORDY)
 0	reserved
SeeAlso: #P0600,#P0601,#P0607,#P0608,#P0616

Bitfields for SCSI status register 2 (SSTAT2):
Bit(s)	Description	(Table P0984)
 7	"OVERRUN"
 6-5	reserved
 4-0	SCSI FIFO count? (SFCNT)
SeeAlso: #P0979,#P0981

Bitfields for SCSI test control register (SCSITEST):
Bit(s)	Description	(Table P0985)
 7-3	reserved
 2	"RQAKCNT"
 1	"CNTRTEST"
 0	"CMODE"
SeeAlso: #P0988

Bitfields for selection timeout timer register (SELTIMER):
Bit(s)	Description	(Table P0986)
 7-6	reserved
 5	"STAGE6"
 4	"STAGE5"
 3	"STAGE4"
 2	"STAGE3"
 1	"STAGE2"
 0	"STAGE1"
SeeAlso: #P0980

Bitfields for selection/reselection ID register (SELID):
Bit(s)	Description	(Table P0987)
 7-4	selecting device ID (SELID)
 3	one bit (ONEBIT)
 2-0	reserved
Note:	bit 3 is set when the selecting/reselecting device did not set its own
	  ID on the SCSI bus
SeeAlso: #P0600,#P0607,#P0982


Bitfields for SCSI block control register (SBLKCTL):
Bit(s)	Description	(Table P0988)
 7-6	reserved
 5	auto-flush disable (AUTOFLUSHDIS)
 4	reserved
 3	select bus (SELBUS)
	=0 select bus A
	=1 select bus B (SELBUSB)
 2	reserved
 1	"SELWIDE"
 0	reserved
Notes:	bit 1 allows for the coexistence of 8-bit and 16-bit devices on a Wide
	  SCSI bus
	in a twin channel configuration addresses 00h-1Eh are gated to the
	  appropriate channel based on the value of bit 3
	bit 5 is read only on the AIC-7770 revisions prior to E

Bitfields for sequencer control register (SEQCTL):
Bit(s)	Description	(Table P0989)
 7	parity error disable (PERRORDIS)
 6	pause disable (PAUSEDIS)
 5	"FAILDIS"
 4	fast mode (FASTMODE)
 3	break address interrupt enable (BRKADRINTEN)
 2	"STEP"
 1	sequencer reset (SEQRESET)
 0	load sequencer RAM (LOADRAM)
Notes:	setting bit 1 causes the sequencer to be paused; the sequencer address
	  register is reset to 0
	bit 7 should be reset while loading the sequencer RAM; after loading
	  is complete, bit 0 should be cleared before changing the sequencer
	  address register (SEQADDR) to avoid sequencer RAM parity errors
SeeAlso: #P0990,#P0996,#P0997,#P0998,#P1014

Bitfields for sequencer address register (SEQADDR):
Bit(s)	Description	(Table P0990)
 15-9	reserved
 8-0	sequencer RAM address
Notes:	bits 8-0 contain the address of a DWORD in the sequencer RAM; it points
	  to the next instruction to be execute or load into RAM
	setting bit 1 in the sequencer control register (SEQCTL) resets this
	  address to 0
	when the PhaseEngine processor is paused, the sequencer address can be
	  altered and a sequencer program can be loaded by writing it, byte by
	  byte, to the sequencer RAM data register (SEQRAM); the address is
	  auto-incremented after the high BYTE of each DWORD is loaded
SeeAlso: #P0989,#P1014

Bitfields for flags register (FLAGS):
Bit(s)	Description	(Table P0991)
 7-2	reserved
 1	zero  flag (ZERO)
 0	carry flag (CARRY)
SeeAlso: #P1014

Bitfields for board control register (BCTL):
Bit(s)	Description	(Table P0992)
 7-4	reserved
 3	"ACE"
 2-1	reserved
 0	enable board (ENABLE)
Note:	bit 3 is somehow related to the support for the external processors

Bitfields for bus on/off time register (BUSTIME):
Bit(s)	Description	(Table P0993)
 7-4	bus off time (BOFF)
	in 4 BCLK cycle units?
 3-0	bus on	time (BON)
SeeAlso: #P0994,#P1002

Bitfields for bus speed register (BUSSPD):
Bit(s)	Description	(Table P0994)
 7-6	DMA FIFO threshold (DFTHRSH)
	11 100?
 5-3	"STBOFF"
 2-0	"STBON"
SeeAlso: #P0993,#P0999,#P1000,#P1002

Bitfields for host control register (HCNTRL):
Bit(s)	Description	(Table P0995)
 7	reserved
 6	power down (POWRDN)
 5	reserved
 4	software interrupt (SWINT)
 3	IRQ mode select (IRQMS)
	=0 level-sensitive
	=1 edge-triggered
 2	pause sequencer (PAUSE)
 1	interrupt enable (INTEN)
 0	chip reset (CHIPRST)
Notes:	bit 0 is self-clearing (though on some AIC-7771 based boards it stucks
	  set, and must be manually cleared)
	set bit 2 to pause the sequencer, then poll the register until this bit
	  reads as 1 indicating that the sequencer has actually stopped; the
	  sequencer can disable pausing for critical sections through bit 6 of
	  the sequencer control register (SEQCTL)
SeeAlso: #P0989,#P1014

Bitfields for interrupt status register (INTSTAT):
Bit(s)	Description	(Table P0996)
 7-4	sequencer status
	0000 unknown SCSI bus phase (BAD_PHASE)
	0001 sending MESSAGE REJECT (SEND_REJECT)
	0010 no IDENTIFY after reconnect (NO_IDENT)
	0011 no command match for reconnect (NO_MATCH)
	0100 SYNCRONOUS DATA TRANSFER REQUEST (SDTR) message received (SDTR_MSG)
	0101 WIDE DATA TRANSFER REQUEST (WDTR) message received (WDTR_MSG)
	0110 MESSAGE REJECT received (REJECT_MSG)
	0111 bad status from target (BAD_STATUS)
	1000 residual byte count non-zero (RESIDUAL)
	1001 sent ABORT TAG message (ABORT_TAG)
	1010 awaiting message
	1011 immediate command completed (IMMEDDONE)
	1100 message buffer busy (MSG_BUFFER_BUSY)
	1101 MESSAGE IN phase mismatch (MSGIN_PHASEMIS)
	1110 data overrun (DATA_OVERRUN)
 3	break address interrupt (BRKADRINT)
 2	SCSI interrupt (SCSIINT)
 1	command complete interrupt (CMDCMPLT)
 0	sequencer interrupt (SEQINT)
Notes:	the PhaseEngine processor can set bit 0 to interrupt the CPU requesting
	  some service from it; an interrupt reason is passed in bits 7-4
	the PhaseEngine processor sets bit 1 after placing a completed SCB into
	  the queue out FIFO
	setting bit 0 pauses the PhaseEngine processor; it needs unpausing via
	  resetting bit 2 of the host control register (HCNTRL)
SeeAlso: #P0986,#P0993,#P0995,#P1014

Bitfields for hard error register (ERROR):
Bit(s)	Description	(Table P0997)
 7-4	reserved
 3	sequencer RAM parity error (PARERR)
 2	illegal opcode in sequencer program (ILLOPCODE)
 1	illegal sequencer address referenced (ILLSADDR)
 0	illegal host access (ILLHADDR)
Note:	usually a full board reset is required after detecting a hard error
SeeAlso: #P1014

Bitfields for clear interrupt status register (CLRINT):
Bit(s)	Description	(Table P0998)
 7-4	reserved
 3	clear break address interrupt (CLRBRKADRINT)
 2	clear SCSI interrupt (CLRSCSIINT)
 1	clear command complete interrupt (CLRCMDINT)
 0	clear sequencer interrupt (CLRSEQINT)
SeeAlso: #P0986,#P0991,#P1014

Bitfields for DMA FIFO control register (DFCNTRL):
Bit(s)	Description	(Table P0999)
 7	reserved
 6	"WIDEODD"
 5	SCSI enable (SCSIEN)
 4	SCSI DMA enable? (SDMAEN)
 3	host DMA enable? (HDMAEN)
 2	"DIRECTION"
	=0 SCSI to host
	=1 host to SCSI
 1	FIFO flush (FIFOFLUSH)
 0	FIFO reset (FIFORESET)
Notes:	this register allows the PhaseEngine processor to control DMA transfers
	  from/to host memory
	bits 3 and 4 clear automatically when host and SCSI DMA is complete
	  respectively
SeeAlso: #P0994,#P1000

Bitfields for DMA FIFO status register (DFSTATUS):
Bit(s)	Description	(Table P1000)
 7-6	reserved
 5	"DWORDEMP"
 4	"MREQPEND"
 3	host DMA done (HDONE)
 2	DMA FIFO threshold? (DFTHRESH)
 1	FIFO full  (FIFOFULL)
 0	FIFO empty (FIFOEMP)
SeeAlso: #P0994,#P0999

Bitfields for SCB auto-increment register (SCBCNT):
Bit(s)	Description	(Table P1001)
 7	SCB auto-increment (SCBAUTO)
 6-5	reserved
 4-0	SCB counter (SCBCNT)
Note:	this register allows CPU to quickly upload/download the SCBs to/from
	  the SCB RAM; if bit 7 is set any reference to addresses A0h-BFh post-
	  increments bits 4-0 of this register containing the offset into the
	  SCB array which is to be accessed next; on the AHA-284x only 8-bit
	  transfers can be used
SeeAlso: #P1003

Format of the scratch RAM:
Offset	Size	Description	(Table P1002)
 00h 16 BYTEs	target scratch (TARG_SCRATCH) (see #9025)
 10h	WORD	channel A Ultra SCSI enable (ULTRA_ENB_A)
		bit N if set means Ultra SCSI transfers are enabled for the
		  target ID N
 10h	BYTE	rejected byte (REJBYTE)
 11h	BYTE	channel B Ultra SCSI enable (ULTRA_ENB_B)
		bit N if set means Ultra SCSI transfers are enabled for the
		  target ID N
 11h	BYTE	rejected byte extended (REJBYTE_EXT)
 11h	BYTE	rejected byte (REJBYTE)
 12h	BYTE	channel A disable disconnect (DISC_DSB_A)
 13h	BYTE	channel B disable disconnect (DISC_DSB_B)
 14h	BYTE	length of pending message (MSG_LEN)
 15h  8 BYTEs	outgoing message (MSG0-MSG7)
 15h	BYTE	pending	 message flag (MSG_FLAGS)
 16h	BYTE	length of pending message (MSG_LEN)
 17h  ? BYTEs	outgoing message body (MSG_START)
 1Dh	BYTE	parameters for DMA logic (DMAPARAMS) (see #P0999)
 1Dh	BYTE	last phase (LASTPHASE)
 1Eh	BYTE	"SEQ_FLAGS"
		bit 7: "RESELECTED"
		bit 6: "IDENTIFY_SEEN"
		bit 5: "TAGGED_SCB"
		bit 4: data phase seen (DPHASE)
		bit 3: reserved
		bit 2: page SCBs (PAGESCBS)
		bit 1: "WIDE_BUS"
		bit 0: "TWIN_BUS"
 1Eh	BYTE	"ARG_1"
		bit 0: "MAXOFFSET"
 1Fh	BYTE	saved target/channel/LUN (SAVED_TCL)
		bits 7-4: target ID
		bit 3: channel (0=A, 1=B)
		bits 2-0: LUN
 1Fh	BYTE	"RETURN_1"
		00h do nothing
		10h SCB paged in (SCB_PAGEDIN)
		20h send MESSAGE REJECT message (SEND_REJ)
		40h send REQUEST SENSE	command (SEND_SENSE)
		60h send SYNCHRONOUS DATA TRANSFER REQUEST message (SEND_SDTR)
		80h send WIDE DATA TRANSFER REQUEST message (SEND_WDTR)
 20h	BYTE	scatter/gather count (SG_COUNT)
 20h	BYTE	"SIGSTATE"
 21h	DWORD	scatter/gather next segment pointer (SG_NEXT)
 21h	BYTE	parameters for DMA logic (DMAPARAMS) (see #P0999)
 22h	BYTE	scatter/gather count (SG_COUNT)
 23h	DWORD	scatter/gather next segment pointer (SG_NEXT)
 25h	BYTE	waiting SCB list head (WAITING_SCBH)
 26h	BYTE	saved link pointer (SAVED_LINKPTR)
 27h	BYTE	saved SCB pointer (SAVED_SCBPTR)
 27h	BYTE	SCB count (SCBCOUNT)
		number of SCBs supported in hardware
 28h	BYTE	last phase (LASTPHASE) (see #9003)
		bit 7: -C/D input (CDI)
		bit 6: -I/O input (IOI)
		bit 5: -MSG input (MSGI)
		bits 4-0: reserved
 28h	BYTE	negative SCB count (COMP_SCBCOUNT)
 29h	BYTE	extended message length (MSGIN_EXT_LEN)
 29h	BYTE	queue count mask (QCNTMASK)
		works around a bug in AIC-7850
 2Ah	BYTE	extended message opcode (MSGIN_EXT_OPCODE)
 2Ah	BYTE	"FLAGS"
		bit 7: "RESELECTED"
		bit 6: IDENTIFY message seen (IDENTIFY_SEEN)
		bit 5: "SELECTED"
		bit 4: data phase seen (DPHASE)
		bit 3: reserved
		bit 2: page SCBs (PAGESCBS)
		bit 1: wide bus	 (WIDE_BUS)
		bit 0: twin bus	 (TWIN_BUS)
 2Bh  3	BYTEs	extended message tail bytes (MSGIN_EXT_BYTES)
 2Bh	BYTE	saved target/channel/LUN (SAVED_TCL)
		bits 7-4: target ID
		bit 3: channel (0=A, 1=B)
		bits 2-0: LUN
 2Ch	WORD	channel A active targets (ACTIVE_A)
		bit N is set if there's untagged SCSI command currently active
		  on the target ID N
 2Ch	BYTE	"ARG_1" or "RETURN_1"
 2Dh	BYTE	channel B active targets (ACTIVE_B)
		bit N is set if there's untagged SCSI command currently active
		  on the target ID N
 2Dh	BYTE	"ARG_2"
 2Eh	BYTE	disconnected SCB list head (DISCONNECTED_SCBH)
 2Eh	BYTE	waiting SCB list head (WAITING_SCBH)
 2Eh	BYTE	signal state (SIGSTATE)
 2Fh	BYTE	free SCB list head (FREE_SCBH)
		disconnected SCB list head (DISCONNECTED_SCBH)
 2Fh	BYTE	"NEEDSDTR"
		bit N if set means that the synchronous data transfer needs to
		  be negotiated with the target ID N
 30h	DWORD	"HSCB_ADDR"
 30h	BYTE	saved link pointer (SAVED_LINKPTR)
 31h	BYTE	saved SCB  pointer (SAVED_SCBPTR)
 32h	WORD	channel A Ultra enable (ULTRA_ENB)
		bit N if set means Ultra SCSI transfers are enabled for the
		  target ID N
 33h	BYTE	channel B Ultra enable (ULTRA_ENB_B)
		bit N if set means Ultra SCSI transfers are enabled for the
		  target ID N
 34h	BYTE	"CUR_SCBID"
 35h	BYTE	"CMDOUTCNT"
		count of commands placed in the out FIFO
 36h	BYTE	SCB count (SCBCOUNT)
		number of SCBs supported in hardware
 36h	BYTE	"ARG_1" or "RETURN_1"
		bit 7: "SEND_MSG"
		bit 6: "SEND_SENSE"
		bit 5: "SEND_REJ"
		bits 4-0: reserved
 37h	WORD	channel A active targets (ACTIVE_A)
		bit N is set if there's untagged SCSI command currently active
		  on the target ID N
 39h	BYTE	reserved
 3Ah	WORD	SCSI configuration (SCSICONF)
		bits 15-12: reserved?
		bits 11-8: (Wide SCSI) our ID (see #P0982)
		bit 7: (AIC-777x) enable SCSI low byte termination (see #P1011)
		bit 6: enable SCSI bus reset at power up (RESET_SCSI)
			 (see #P1011)
		bit 5: enable SCSI parity check (ENSPCHK) (see #P0980)
		bits 4-3: selection time-out select (STIMESEL) (see #P0980)
		bits 2-0: our ID (see #P0982)
 3Bh	BYTE	channel B SCSI configuration
		see bits 7-0 above
 3Ch	BYTE	"INTDEF"
		bits 7-4: reserved?
		bits 3-0: IRQ number (IRQ9..IRQ12, IRQ14, and IRQ15 are valid)
 3Dh	BYTE	host configuration (HOSTCONF)
		bits 7-6: DMA FIFO threshold (DFTHRSH) (see #9038)
		bits 5-2: bus off time (BOFF) (see #9037)
		bits 1-0: reserved?
 3Eh	BYTE	reserved
 3Fh	BYTE	(AIC-7771) BIOS control (BIOSCTRL)
		bits 5-4: BIOS mode (BIOSMODE)
			  11 BIOS disabled (BIOSDISABLED)
		bit 3: channel B is primary (CHANNEL_B_PRIMARY)
Notes:	the scratch RAM is used for passing information between the driver and
	  BIOS and the code running on the PhaseEngine processor; it serves as
	  a working memory for the PhaseEngine processor as well
	location definitions overlap due to various sources giving different
	  scratch RAM layouts
	the PhaseEngine processor uses "ARG_1" and "ARG_2" to pass parameters
	  to the drivers and BIOS during sequencer interrupts; "RETURN_1" is used
	  to return results from the drivers and BIOS to the PhaseEngine code
	the PhaseEngine processor uses SCB pointer register's (SCBPTR) values
	  to link SCB in the lists, with value FFh indicating the end of list
SeeAlso: #9047,#9048

Format of the SCB array:
Offset	Size	Description	(Table P1003)
 00h	BYTE	"SCB_CONTROL"
		bit 7: need WDTR message (NEEDWDTR) or
		       "MK_MESSAGE"
		bit 6: disconnect enable (DISCENB)
		bit 5: tagging enable (TAG_ENB)
		bit 4: need SDTR message (NEEDSDTR) or
		       "MUST_DMAUP_SCB"
		bit 3: "ABORT_SCB"
		bit 2: "DISCONNECTED"
		bits 1-0: command tag type (SCB_TAG_TYPE)
 01h	BYTE	target/channel/LUN (SCB_TCL)
		bits 7-4: target ID
		bit 3: channel (0=A, 1=B)
		bits 2-0: LUN
 02h	BYTE	target status (SCB_TARGET_STATUS)
		SCSI status byte
 03h	BYTE	scatter/gather count (SCB_SGCOUNT)
 04h	DWORD	scatter/gather pointer (SCB_SGPTR)
 08h	BYTE	residual scatter/gather count (SCB_RESID_SGCNT)
 09h  3 BYTEs	residual data count (SCB_RESID_DCNT)
 0Ch	DWORD	data pointer (SCB_DATAPTR)
 10h  3 BYTEs	data count (SCB_DATACNT)
 13h	BYTE	next linked SCB index (SCB_LINKED_NEXT)
 14h	DWORD	command pointer (SCB_CMDPTR)
 18h	BYTE	command length (SCB_CMDLEN)
 19h	BYTE	command tag (SCB_TAG)
 1Ah	BYTE	next SCB index (SCB_NEXT)
 1Bh	BYTE	previous SCB index (SCB_PREV)
 1Ch  2	WORDs	busy targets (SCB_BUSYTARGETS)
		bit N is set if there's untagged SCSI command currently active
		  on the target ID N
SeeAlso: #P1004,#P1014

Format of the scatter/gather segment:
Offset	Size	Description	(Table P1004)
 00h	DWORD	physical address
 04h	DWORD	length
SeeAlso: #P1003,#P1014

Bitfields for AHA-284x serial EEPROM control register (SEECTL):
Bit(s)	Description	(Table P1005)
 7-3	reserved
 2	chip select (CS)
 1	clock (CK)
 0	data out (DO)
Notes:	93C46 serial EEPROM chips have 1024 bits organized into 64 16-bit
	  words and use 6 bits to address each word
	only the first 32 words of serial EEPROM are used by the Adaptec BIOS
	bits 2-0 are connected to the chip select, clock, and data out pins of
	  the serial EEPROM respectively
	bit 1 must be pulled high and then low for a minimum of 750 and 250 ns
	  to provide clocking for the EEPROM chip
	bit 1 going from low to high causes the EEPROM chip to sample the data
	  out pin and initiates the next bit to be sent through the data in pin
	bit 2 must be set for a minimum of 1 mcs with the bit 1 goig high and
	  then low for the EEPROM chip to be selected; then the instruction can
	  be sent to the EEPROM chip
	instruction can be terminated by taking the EEPROM chip select pin low,
	  with the bit 1 going high and low
SeeAlso: #P1006,#P1007,#P1008

Bitfields for AHA-284x "STATUS" register:
Bit(s)	Description	(Table P1006)
 7	EEPROM timer fired? (EEPROM_TF)
 6-5	"BIOS_SEL"
 4-1	"ADSEL"
 0	data in (DI)
Notes:	bit 0 is connected to the data in pin of the serial EEPROM; it can be
	  read after the clock pin goes from high to low
	bit 7 is cleared after a read from the serial EEPROM control register
	  (SEECTL) and goes high 800 ns later
SeeAlso: #P1005,#P1007,#P1008

(Table P1007)
Values for the 93C46 serial EEPROM instructions:
Opcode	   Function  Parameter	Description
0000xxxxb  EWDS	     -		disable all programming instructions
0001xxxxb  WRAL	     D15..D0	write to all registers
0010xxxxb  ERAL	     -		erase all registers
0011xxxxb  EWEN	     -		write enable
				must precede all programming modes
01AAAAAAb  WRITE     D15..D0	write register with address A5..A0
10AAAAAAb  READ	     -		read registers starting with address A5..A0
11AAAAAAb  ERASE     -		erase register with address A5..A0
Notes:	while the chip select pin remains high an instuction and the optional
	  parameter word can be clocked in MSB first, beginning with the start
	  bit of 1
	16-bit parameter and data words are transferred MSB first, beginning
	  with the start bit of 0
SeeAlso: #P1005,#P1006

Format of the AHA-284x serial EEPROM:
Address	Size	Description	(Table P1008)
 00h  16 WORDs	SCSI ID configuration (see #P1009)
 10h	WORD	BIOS control (see #P1011)
 11h	WORD	host adapter control (see #P1012)
 12h	WORD	bus release time / host adapter ID (see #P1013)
 13h	WORD	maximum targets (see #P1014)
 14h  11 WORDs	reserved
 1Fh	WORD	checksum
SeeAlso: #P1005,#P1006

Bitfields for the serial EEPROM SCSI ID configuration word:
Bit(s)	Description	(Table P1009)
 15-11	reserved
 10	report even if not found (CFRNFOUND)
 9	include in BIOS scan (CFINCBIOS)
 8	send START UNIT SCSI command (CFSTART)
 7-6	reserved
 5	(Wide SCSI) wide bus device (CFWIDEB)
 4	enable disconnection (CFDISC)
 3	enable synchronous transfer (CFSYNCH)
 2-0	synchronous transfer rate (CFXFER)
SeeAlso: #P0605,#P1008

Bitfields for the serial EEPROM BIOS control word:
Bit(s)	Description	(Table P1011)
 15-6	reserved
 5	extended translation (CFEXTEND)
 4	support more than 2 drives (CFSM2DRV)
 3	reserved
 2	BIOS enabled (CFBIOSEN)
 1	support removable drives for boot only (CFSUPREMB)
 0	support all removable drives (CFSUPREM)
SeeAlso: #P1008

Bitfields for the serial EEPROM host adapter control word:
Bit(s)	Description	(Table P1011)
 15-7	reserved
 6	reset SCSI bus at IC initialization (CFRESETB)
 5	SCSI low byte termination (CFSTERM)
	=0 disable
	=1 enable
 4	SCSI parity (CFSPARITY)
	=0 disable
	=1 enable
 3-2	FIFO threshold (CFFIFO)
 1-0	selection timeout (CFSELTO)
SeeAlso: #P0600,#P0980,#P0994,#P1008

Bitfields for the serial EEPROM bus release time / host adapter ID word:
Bit(s)	Description	(Table P1012)
 15-8	bus release time (CFBRTIME)
 7-4	reserved
 3-0	host adapter SCSI ID (CFSCSIID)
SeeAlso: #P0982,#P0989,#P1007

Bitfields for the serial EEPROM maximum targets word:
Bit(s)	Description	(Table P1013)
 15-8	reserved
 7-0	maximum targets (CFMAXTARG)
SeeAlso: #P1007

Bitfields for the PhaseEngine SCSI sequence processor instruction:
Bit(s)	Description	(Table P1014)
 31-29	reserved (0)
 28-25	opcode
	0000 OR	 dest,imm[,src] [RET]
	     MVI dest,imm [RET]
	0001 AND dest,imm[,src] [RET]
	     MOV dest,src [RET]
	     CLR dest [RET]
	     NOP [RET]
	     RET
	0010 XOR dest,imm[,src] [RET]
	     NOT dest [RET]
	0011 ADD dest,imm[,src] [RET]
	     INC dest[,src] [RET]
	     DEC dest[,src] [RET]
	     CLC [dest[,imm]] [RET]
	     STC dest [RET]
	0100 ADC dest,imm[,src] [RET]
	0101 SHL/SHR/ROL/ROR dest,[src,]imm [RET]
	1000 OR	 src,imm JMP addr
	     MOV src JMP addr
	     MVI imm JMP addr
	     JMP addr
	1001 OR	 src,imm JC addr
	     MOV src JC addr
	     MVI imm JC addr
	     JC addr
	1010 OR	 src,imm JNC addr
	     MOV src JNC addr
	     MVI imm JNC addr
	     JNC addr
	1011 OR	 src,imm CALL addr
	     MOV src CALL addr
	     MVI imm CALL addr
	     CALL addr
	1100 CMP  src,imm JNE addr
	1101 TEST src,imm JNZ addr
	1110 CMP  src,imm JE  addr
	1111 TEST src,imm JZ  addr
	others reserved
 24-16	(jump instructions) instruction address
 24	(non-jump instructions) return flag
 23-16	(non-jump instructions) destination register address
 15-8	source register address
 7-0	(shift instructions) shift control (see #P1015)
	(other instructions) immediate data
	if 0 accumulator register (ACCUM) is used instead
Notes:	the jump instructions with the OR/MOV/MVI prefixes implicitly use the
	  source index register (SINDEX) as destination
SeeAlso: #P0989,#P0990,#P0991,#P0995,#P0996,#P0997,#9042

Bitfields for the PhaseEngine shift control:
Bit(s)	Description	(Table P1015)
 7	clear all bits?
 6-4	number of bits to shift the AND mask (FFh)
 3	=0 shift the AND mask left
	=1 shift the AND mask right
 2-0	number of bits to rotate the source left
Notes:	the 8-bit source seems to be rotated left and then AND'ed with the mask
	  (FFh) which is shifted left or right prior to AND'ing in order to
	  perform all kinds of the shift/rotate instructions
	bit 7 is set (and bits 6-4 equal 7) if the shift count is greater than
	  7 specified for the SHL/SHR instructions
----------P1C65------------------------------
PORT 1C65 - Compaq Contura Aero
SeeAlso: PORT 2065h

1C65  R?  bit 6: operating on battery power
--------X-P1C801C8F--------------------------
PORT 1C80-1C8F - VESA XGA Video in EISA slot 1

1C80-1C83  RW	EISA Video ID
1C84  RW	EISA Video expansion board control (see #P1016)
1C85  RW	EISA Setup control
1C88  RW	EISA Video Programmable Option Select 0
1C89-1C8F  RW	EISA Video Programmable Option Select 1-7
--------X-P1C801C83--------------------------
PORT 1C80-1C83 - EISA board product ID (board in slot 1)

1C80  R?  bit 7: unused (0)
	  bits 6-2: manufacturer ID, first compressed ASCII char
	  bits 1-0: manufacturer ID, second compressed ASCII char (high)
1C81  R?  bits 7-5: manufacturer ID, second compressed ASCII char (low)
	  bits 4-0: manufacturer ID, third compressed ASCII char
1C82  R?  bits 7-4: first hex digit of product type
	  bits 3-0: second hex digit of product type
1C83  R?  bits 7-4: third hex digit of product type
	  bits 3-0: product revision number (hex digit)
--------X-P1C84------------------------------
PORT 1C84 - EISA CONFIGURATION FLAGS (board in slot 1)

1C84  RW  configuration flags (see #P1016)

Bitfields for EISA Add-in Card configuration flags:
Bit(s)	Description	(Table P1016)
 0	enable
 1	IOCHKERR (read-only) card is generating CHCHK#, causing an NMI
 2	IOCHKRST reset card
 7-3	card-specific
--------X-P1C85------------------------------
PORT 1C85 - EISA SETUP CONTROL (board in slot 1)
--------V-P1C85------------------------------
PORT 1C85 - Compaq Qvision EISA - Virtual Controller ID
--------X-P1C881C8F--------------------------
PORT 1C88-1C8F - EISA PROGRAMMABLE OPTION SELECT (board in slot 1)
--------V-P1EE81EEF--------------------------
PORT 1EE8-1EEF - 8514/A and compatible (e.g. ATI Graphics Ultra) - VSYNC WIDTH

1EE8w -W  CRT control: vertical sync width
--------V-P1EEC------------------------------
PORT 1EEC - Mach64 - ???

1EEC  RW  display power and other controls
	bits 3-2: DPMS power mode
		00 normal
		01 standby
		10 suspend
		11 off
--------X-P200020FF--------------------------
PORT 2000-20FF - available for EISA slot 2
----------P2065------------------------------
PORT 2065 - Compaq Contura Aero
SeeAlso: PORT 1C65h"Compaq",PORT 2465h"Compaq"

2065  -W  ??? (84h seen)
--------V-P2100------------------------------
PORT 2100 - XGA Video Operating Mode Register
Note:	this port is for the first XGA in the system; 2110-2170 are used for
	  the second through eighth XGAs
--------V-P2101------------------------------
PORT 2101 - XGA Video Aperture Control
Note:	this port is for the first XGA in the system; 2111-2171 are used for
	  the second through eighth XGAs
--------V-P21022103--------------------------
PORT 2102-2103 - XGA ???
Note:	this port is for the first XGA in the system; 211x-217x are used for
	  the second through eighth XGAs
--------V-P2104------------------------------
PORT 2104 - XGA Video Interrupt Enable
Note:	this port is for the first XGA in the system; 211x-217x are used for
	  the second through eighth XGAs
--------V-P2105------------------------------
PORT 2105 - XGA Video Interrupt Status
Note:	this port is for the first XGA in the system; 211x-217x are used for
	  the second through eighth XGAs
--------V-P2106------------------------------
PORT 2106 - XGA Video Virtual Memory Control
Note:	this port is for the first XGA in the system; 211x-217x are used for
	  the second through eighth XGAs
--------V-P2107------------------------------
PORT 2107 - XGA Video Virtual Memory Interrupt Status
Note:	this port is for the first XGA in the system; 211x-217x are used for
	  the second through eighth XGAs
--------V-P2108------------------------------
PORT 2108 - XGA Video Aperture Index
Note:	this port is for the first XGA in the system; 211x-217x are used for
	  the second through eighth XGAs
--------V-P2109------------------------------
PORT 2109 - XGA Video Memory Access Mode
Note:	this port is for the first XGA in the system; 211x-217x are used for
	  the second through eighth XGAs
--------V-P210A------------------------------
PORT 210A - XGA Video Index for Data
Note:	this port is for the first XGA in the system; 211x-217x are used for
	  the second through eighth XGAs
--------V-P210B------------------------------
PORT 210B - XGA Video Data (byte)
Note:	this port is for the first XGA in the system; 211x-217x are used for
	  the second through eighth XGAs
--------V-P210C210F--------------------------
PORT 210C-210F - XGA Video Data (word/dword)
Note:	this port is for the first XGA in the system; 211x-217x are used for
	  the second through eighth XGAs

210C  RW  byte data
210Cw RW  word data
210Cd RW  dword data
--------V-P2110211F--------------------------
PORT 2110-211F - IBM XGA (eXtended Graphics Adapter  8514/A) (second installed)
Notes:	see individual 210x entries above
	c't says default instance number is 6, i.e. addresses 216x
--------V-P2120212F--------------------------
PORT 2120-212F - IBM XGA (eXtended Graphics Adapter  8514/A) (third installed)
Notes:	see individual 210x entries above
	c't says default instance number is 6, i.e. addresses 216x
--------V-P2130213F--------------------------
PORT 2130-213F - IBM XGA (eXtended Graphics Adapter  8514/A) (fourth installed)
Notes:	see individual 210x entries above
	c't says default instance number is 6, i.e. addresses 216x
--------V-P2140214F--------------------------
PORT 2140-214F - IBM XGA (eXtended Graphics Adapter  8514/A) (fifth installed)
Notes:	see individual 210x entries above
	c't says default instance number is 6, i.e. addresses 216x
--------V-P2150215F--------------------------
PORT 2150-215F - IBM XGA (eXtended Graphics Adapter  8514/A) (sixth installed)
Notes:	see individual 210x entries above
	c't says default instance number is 6, i.e. addresses 216x
--------V-P2160216F--------------------------
PORT 2160-216F - IBM XGA (eXtended Graphics Adapter 8514/A) (seventh installed)
Notes:	see individual 210x entries above
	c't says default instance number is 6, i.e. addresses 216x
--------V-P2170217F--------------------------
PORT 2170-217F - IBM XGA (eXtended Graphics Adapter 8514/A) (eighth installed)
Notes:	see individual 210x entries above
	c't says default instance number is 6, i.e. addresses 216x
--------V-P217A217B--------------------------
PORT 217A-217B - ET4000/W32 CRTC-B/Sprite
Note:	Alternative addresses may depend on adapter manufacturer,
	  Tseng claims 21xA with x=three address bits, selected by IOD2..0
	  during power up reset.

21xA  RW  ET4000/W32(i) CRTC-B/Sprite index register
	bit7-0: index
21xB  RW  ET4000/W32(i) CRTC-B/Sprite data register (see #P1017)

(Table P1017)
Values for ET4000/W32(i) CRTC-B/Sprite data register index:
 E0h	CRTC-B / Sprite Horizontal Pixel Position, Low
	   bit7-0: horizontal pixel position bit7-0
 E1h	CRTC-B / Sprite Horizontal Pixel Position, High
	   bit7-4: reserved
	   bit3-0: horizontal pixel position bit11-8
 E2h	CRTC-B Width Low / Sprite Horizontal Preset
	   bit7-0: width of CRTC-B bit7-0
	   bit5-0: horizontal preset for sprite
 E3h	CRTC-B Width High / Sprite Horizontal Preset
	   bit7-4: reserved
	   bit3-0: width of CRTC-B bit11-8
 E4h	CRTC-B / Sprite Vertical Pixel Position, Low
	   bit7-0: vertical pixel position bit7-0
 E5h	CRTC-B / Sprite Vertical Pixel Position, High
	   bit7-4: reserved
	   bit3-0: vertical pixel position bit11-8
 E6h	CRTC-B Height Low / Sprite Vertical Preset
	   bit7-0: height of CRTC-B bit7-0
	   bit5-0: vertical preset for sprite
 E7h	CRTC-B Height High / Sprite Vertical Preset
	   bit7-4: reserved
	   bit3-0: height of CRTC-B bit11-8
 E8h	CRTC-B / Sprite Starting Address Low
	   pointer to CRTC-B / sprite image in display memory.
	   (maximum size of sprites 64x64x4=1KB with 4 colors:
	    00b=color-0, 01b=color-255, 10b=transparent, 11b=reserved)
	   bit7-0: startaddress bit7-0
 E9h	CRTC-B / Sprite Starting Address Middle
	   bit7-0: startaddress bit15-8
 EAh	CRTC-B / Sprite Starting Address High
	   bit7-4: reserved
	   bit3-0: startaddress bit19-16
 EBh	CRTC-B / Sprite Row Offset Low
	   bit7-0: offset bit7-0
 ECh	CRTC-B / Sprite Row Offset High
	   bit7-4: revision ID (any ET4000/W32)
		    0000b=W32	     0100b-1111b reserved
		    0001b=W32i
		    0010b=W32p
		    0011b=W32i, new
	   bit3-0: offset bit11-8
 EDh	CRTC-B Pixel Panning
	   bit7-3: reserved
	   bit2-0: CRTC-B pixel panning
 EEh	CRTC-B Color-Depth-Register / Hardware-Zoom
	   bit7-4: reserved (concerning databook ET4000/W32)
	   bit7-6: vertical zoom (undocumented)
		   (original ET4000/W32 ok, doesn't work properly
		    with some ET4000/W32i)
		    00b=zoomx1	   10b=zoomx3
		    01b=zoomx2	   11b=zoomx4
	   bit5-4: horizontal zoom (undocumented)
		   (original ET4000/W32 ok, doesn't work properly
		    with some ET4000/W32i)
		    00b=zoomx1	   10b=zoomx3
		    01b=zoomx2	   11b=zoomx4
	   bit3-0: bit/pixel
		    0000b=1	   0011b=8
		    0001b=2	   0100b=16
		    0010b=4
 EFh	CRTC-B / Sprite Control
	   bit7-2: reserved
	   bit1	 : 1=2nd CRTC-B image overlays main CRTC-A image
		   0=CRTC-B image at pin SP1/0
	   bit0	 : 1=enable CRTC-B
		   0=enable sprite (see F7h)
 F7h	Image Port Control
	   bit7	 : 1=CRTC-B or sprite active
		   0=CRTC-B and sprite not active
	   bit6-0: reserved
----------P22E822EF--------------------------
PORT 22E8-22EF - 8514/A and compatible (e.g. ATI Graphics Ultra) - DISPLAY CTRL

22E8w -W  CRT control: display control
----------P23902393--------------------------
PORT 2390-2393 - cluster (adapter 4)
--------V-P23C023CF--------------------------
PORT 23C0-23CF - Compaq QVision - BitBLT engine
--------X-P240024FF--------------------------
PORT 2400-24FF - available for EISA slot 2
----------P2465------------------------------
PORT 2465 - Compaq Contura Aero
SeeAlso: PORT 1C65h"Compaq",PORT 2065h"Compaq"

2465  R-  current battery power level
		(166 fully-charged, 130 = LowBat1)
----------P27C6------------------------------
PORT 27C6 - Compaq LTE Lite - LCD TIMEOUT

27C6  RW  LCD timeout in minutes
--------X-P280028FF--------------------------
PORT 2800-28FF - available for EISA slot 2
--------V-P28E9------------------------------
PORT 28E9 - 8514/A - WD Escape Functions
--------d-P2C002CBF--------------------------
PORT 2C00-2CBF -  Adaptec AIC-777x EISA SCSI controller in EISA slot 2
SeeAlso: PORT 0340h-035Fh"Adaptec AHA-154x",PORT xxxxh"Adaptec AIC-78xx"
--------V-P2C802C8F--------------------------
PORT 2C80-2C8F - VESA XGA Video in EISA slot 2
SeeAlso: PORT 1C80h-1C83h,PORT 1C88h-1C8Fh
--------X-P2C802C83--------------------------
PORT 2C80-2C83 - EISA board product ID (board in slot 2)
SeeAlso: PORT 1C80h-1C83h
--------X-P2C84------------------------------
PORT 2C84 - EISA CONFIGURATION FLAGS (board in slot 2)

2C84  RW  configuration flags (see #P1016)
--------X-P300030FF--------------------------
PORT 3000-30FF - available for EISA slot 3
--------S-P32203227--------------------------
PORT 3220-3227 - serial port 3, description same as 03F8
--------S-P3228322F--------------------------
PORT 3228-322F - serial port 4, description same as 03F8
--------V-P33C033CF--------------------------
PORT 33C0-33CF - Compaq QVision - BitBLT engine
--------X-P340034FF--------------------------
PORT 3400-34FF - available for EISA slot 3
--------d-P35103513--------------------------
PORT 3510-3513 - ESDI primary harddisk controller
Range:	PORT 3510h-3513h (primary) or PORT 3518h-351Bh (secondary)
SeeAlso: PORT 3518h,PORT 01F0h-01F7h

3510w R-  status word
3510w -W  command word
3512  R-  basic status
3512  -W  basic control
3513  R-  interrupt status
3513  -W  attention
--------d-P3518351B--------------------------
PORT 3518-351B - ESDI secondary harddisk controller
Range:	PORT 3510h-3513h (primary) or PORT 3518h-351Bh (secondary)
SeeAlso: PORT 3510h,PORT 01F0h-01F7h

3518w R-  status word
3518w -W  command word
351A  R-  basis status
351A  -W  basic control
351B  R-  interrupt status
351B  -W  attention
--------d-P3540354F--------------------------
PORT 3540-354F - IBM SCSI (Small Computer System Interface) adapter
--------d-P3550355F--------------------------
PORT 3550-355F - IBM SCSI (Small Computer System Interface) adapter
--------d-P3560356F--------------------------
PORT 3560-356F - IBM SCSI (Small Computer System Interface) adapter
--------d-P3570357F--------------------------
PORT 3570-357F - IBM SCSI (Small Computer System Interface) adapter
--------V-P36EE------------------------------
PORT 36EE - ATI Mach8/Mach32 - FIFO OPTION
SeeAlso: PORT 6AEEh,PORT 6EEEh,PORT 72EEh,PORT 76EEh,PORT 7AEEh,PORT 8EEEh

36EE  -W  FIFO option
		bit 0: generate wait states if FIFO >= half full
			(0=only when FIFO full)
		bit 1: force 8-bit host data I/O
--------X-P380038FF--------------------------
PORT 3800-38FF - available for EISA slot 3
--------X-P3C003CFF--------------------------
PORT 3C00-3CFF - available for EISA slot 3
--------d-P3C003CBF--------------------------
PORT 3C00-3CBF -  Adaptec AIC-777x EISA SCSI controller in EISA slot 3
SeeAlso: PORT 0340h-035Fh"Adaptec AHA-154x",PORT xxxxh"Adaptec AIC-78xx"
--------V-P3C803C8F--------------------------
PORT 3C80-3C8F - VESA XGA Video in EISA slot 3

3C80-3C83  RW	EISA Video ID
3C84  RW	EISA Video expansion board control
3C85  RW	EISA Setup control
3C88  RW	EISA Video Programmable Option Select 0
3C89-3C8F  RW	EISA Video Programmable Option Select 1-7

SeeAlso: PORT 1C80h-1C8Fh"XGA",PORT 2C80h-2C8Fh"XGA",PORT 7C80h-7C8Fh"XGA"
--------X-P3C803C83--------------------------
PORT 3C80-3C83 - EISA board product ID (board in slot 3)
SeeAlso: PORT 1C80h-1C83h
--------X-P3C84------------------------------
PORT 3C84 - EISA CONFIGURATION FLAGS (board in slot 3)

3C84  RW  configuration flags (see #P1016)
--------X-P400040FF--------------------------
PORT 4000-40FF - available for EISA slot 4
----------P42204227--------------------------
PORT 4220-4227 - serial port, description same as 03F8
----------P4228422F--------------------------
PORT 4228-422F - serial port, description same as 03F8
----------P42E042EF--------------------------
PORT 42E0-42EF - GPIB (General Purpose Interface Bus, IEEE 488 interface)

42E1  RW  GPIB (adapter 2)
--------V-P42E8------------------------------
PORT 42E8 - 8514/A and hardware-compatible video cards
Note:	supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set

42E8w R-  Misc. control: Subsystem Status (see #P1018)
42E8w -W  Misc. control: Subsystem Control (see #P1019)

Bitfields for 8514/A Subsystem Status register:
Bit(s)	Description	(Table P1018)
 15-8	(8514/A) reserved
 13	(S3) ???
 12-8	(S3) ???
 7	pixel length (0 = four bits, 1 = eight bits)
 6-4	reserved
 3	FIFO empty (interrupt generated if enabled)
 2	FIFO overflow (interrupt generated if enabled)
 1	Graphics Engine busy (interrupt generated if enabled)
 0	vertical sync (interrupt generated if enabled)
SeeAlso: #P1019

Bitfields for 8514/A Subsystem Control Register:
Bit(s)	Description	(Table P1019)
 15-14	GP_RESET
      W	00 no change
	01 normal operation
	10 reset graphics processor and FIFO
	11 reserved
 13-12	reserved
 11   W	enable interrupt when graphics processor idle
 10   W	enable interrupt on invalid I/O (FIFO overlow)
 9    W	enable interrupt if inside scissors region
 8    W	enable vertical blanking interval interrupt
 6-4 R	monitor ID (8514/A)
 7-4	reserved (S3)
 3	acknowledge idle interrupt (and clear)
 2	acknowledge invalid I/O interrupt (and clear)
 1	acknowledge inside-scissors interrupt (and clear)
 0	acknowledge vertical blanking interrupt (and clear)
SeeAlso: #P1018
--------V-P42EC------------------------------
PORT 42EC - ATI Mach64 - ???
SeeAlso: PORT 42EDh"Mach64"

42EC  RW  ???
	bits 1-0: ???
--------V-P42ED------------------------------
PORT 42ED - ATI Mach64 - ???
SeeAlso: PORT 42ECh"Mach64",PORT 42EFh

42ED  R?  ???
--------V-P42EE42EF--------------------------
PORT 42EE-42EF - ATI Mach32 - MEMORY BOUNDARY REGISTER
SeeAlso: PORT 5EEEh"Mach32"

42EEw RW  memory boundary
	bits 3-0: VGA/8514 boundary in 256K units (VGA only below, 8514 above)
	bit 4: partition enable: VGA and 8514 drawing engines may only write
	      within their respective partitions
	bits 15-5: reserved
--------V-P42EF------------------------------
PORT 42EF - ATI Mach64 - ???
SeeAlso: PORT 42EDh"Mach64"

42EF  R?  ???
--------X-P440044FF--------------------------
PORT 4400-44FF - available for EISA slot 4
----------P4F15------------------------------
PORT 4F15 - Tseng Labs ET6000 - Read EDID through Display Data Channel
--------V-P46E8------------------------------
PORT 46E8 - VGA - VIDEO ADAPTER ENABLE
Note:	IBM uses this port for adapter-card VGAs only, and PORT 03C3h for
	  motherboard VGA only (see 03C3 for details)
SeeAlso: PORT 03C3h,PORT 46E8h"8514/A",#P0748

46E8  rW  Misc. control: enable flags / select ROM page (8514/A) (see #P1020)

Bitfields for VGA miscellaneous control register:
Bit(s)	Description	(Table P1020)
 7-5	unused or vendor-specific
 4	setup for POS registers (MCA)
 3	enable video I/O ports and video buffer
 2-0	unused or vendor-specific
--------V-P46E8------------------------------
PORT 46E8 - 8514/A and compatible (e.g. ATI Graphics Ultra) - ROM PAGE SELECT
Note:	this register is readable on the C&T 82c480 chipset
SeeAlso: PORT 46E8h"VGA"

46E8w -W  ROM page select (see #P1021)

Bitfields for 8514/A ROM page select register:
Bit(s)	Description	(Table P1021)
 2-0	select which 4K page of 32K ROM to map at segment C700h
 3	enable VGA
 4	select VGA setup mode
 15-5	reserved (0)
--------V-P46EE------------------------------
PORT 46EE - ATI Mach32 - ???

46EEw RW  ???
--------V-P46EF------------------------------
PORT 46EF - ATI Mach64 - ???
Note:	the Mach64 BIOS reads the value of this port and multiplies it by 100
SeeAlso: PORT 66ECh"Mach64"
--------X-P480048FF--------------------------
PORT 4800-48FF - available for EISA slot 4
--------V-P4AE84AE9--------------------------
PORT 4AE8-4AE9 - 8514/A and compatible - CRT CONTROL
Notes:	supported by ATI Mach8 and Mach32 chipsets
	supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: #P0749

4AE8w -W  CRT control: Advanced function control (see also #P1022)
	(02h = VGA mode, 03h = 480-line mode, 07h = 768-line mode)

Bitfields for S3 8514/A-compatible Advanced Function Control register:
Bit(s)	Description	(Table P1022)
 15-7	reserved
 6	(928 only) enable Write Posting
 5	(928+) enable memory-mapped I/O
 4	(928+) enable linear addressing (see also #P0741)
 3	reserved
 2	(911-928) screen size (1 = 800x600 or 1024x768, 0=640x480)
	(Trio32/Trio64) enhanced modes pixel length (0 = 8+ bpp, 1 = 4 bpp)
 1	reserved (1)
 0	enable enhanced functions
Note:	bit 4 is ORed with CR58 bit 4; bit 5 is ORed with CR53 bit 4
--------V-P4AEE------------------------------
PORT 4AEE - ATI Mach32 - ???

4AEEw RW  ???
--------X-P4C004CFF--------------------------
PORT 4C00-4CFF - available for EISA slot 4
--------d-P4C004CBF--------------------------
PORT 4C00-4CBF -  Adaptec AIC-777x EISA SCSI controller in EISA slot 4
SeeAlso: PORT 0340h-035Fh"Adaptec AHA-154x",PORT xxxxh"Adaptec AIC-78xx"
--------X-P4C804C83--------------------------
PORT 4C80-4C83	EISA board product ID (board in slot 4)
SeeAlso: PORT 1C80h-1C83h
--------V-P4C804C8F--------------------------
PORT 4C80-4C8F - VESA XGA Video in EISA slot 4 (see 3C80-3C8F)
SeeAlso: PORT 1C80h-1C8Fh,PORT 6C80h-6C8Fh
--------X-P4C84------------------------------
PORT 4C84 - EISA CONFIGURATION FLAGS (board in slot 4)

4C84  RW  configuration flags (see #P1016)
--------X-P500050FF--------------------------
PORT 5000-50FF - available for EISA slot 5
--------S-P52205227--------------------------
PORT 5220-5227 - serial port, description same as 03F8
--------S-P5228522F--------------------------
PORT 5228-522F - serial port, description same as 03F8
--------V-P52E852E9--------------------------
PORT 52E8-52E9 - C&T 82c480 - EXTENDED CONFIGURATION REGISTER 0
Note:	the 82c480 is an 8514/A-compatible video chipset
SeeAlso: PORT 56E8h"C&T",PORT 5AE8h"C&T",PORT 5EE8h"C&T"

52E8w RW  Extended Configuration Register 0
--------V-P52EE52EF--------------------------
PORT 52EE-52EF - ATI Mach32 - SCRATCH REGISTER 0 (USED FOR ROM LOCATION)
Note:	ATI video BIOS sets this port according to the segment address of the
	  BIOS if >= C000h, as ((seg-C000h) shr 7)
SeeAlso: PORT 56EEh"Mach32"

52EEw RW  scratch register 0: Video ROM address
--------X-P540054FF--------------------------
PORT 5400-54FF - available for EISA slot 5
--------V-P56E856E9--------------------------
PORT 56E8-56E9 - C&T 82c480 - EXTENDED CONFIGURATION REGISTER 1
Note:	the 82c480 is an 8514/A-compatible video chipset
SeeAlso: PORT 52E8h"C&T",PORT 5AE8h"C&T",PORT 5EE8h"C&T"

56E8w RW  Extended Configuration Register 1
--------V-P56EE56EF--------------------------
PORT 56EE-56EF - ATI Mach32 - SCRATCH REGISTER 1
SeeAlso: PORT 52EEh"Mach32"

56EEw RW  scratchpad
--------X-P580058FF--------------------------
PORT 5800-58FF - available for EISA slot 5
--------V-P5AE85AE9--------------------------
PORT 5AE8-5AE9 - C&T 82c480 - EXTENDED CONFIGURATION REGISTER 2
Note:	the 82c480 is an 8514/A-compatible video chipset
SeeAlso: PORT 52E8h"C&T",PORT 56E8h"C&T",PORT 5EE8h"C&T"

5AE8w RW  Extended Configuration Register 2
--------V-P5AEE------------------------------
PORT 5AEE - ATI Mach32 - ???

5AEE  RW  ???
--------X-P5C005CFF--------------------------
PORT 5C00-5CFF - available for EISA slot 5
--------d-P5C005CBF--------------------------
PORT 5C00-5CBF -  Adaptec AIC-777x EISA SCSI controller in EISA slot 5
SeeAlso: PORT 0340h-035Fh"Adaptec AHA-154x",PORT xxxxh"Adaptec AIC-78xx"
--------V-P5C805C8F--------------------------
PORT 5C80-5C8F - VESA XGA Video in EISA slot 5
SeeAlso: PORT 2C80h-2C8Fh,PORT 4C80h-4C8Fh,PORT 6C80h-6C8Fh

5C80d RW  EISA Video ID
5C84  RW  EISA Video expansion board control
5C85  RW  EISA Setup control
5C88  RW  EISA Video Programmable Option Select 0
5C89  RW  EISA Video Programmable Option Select 1
5C8A  RW  EISA Video Programmable Option Select 2
5C8B  RW  EISA Video Programmable Option Select 3
5C8C  RW  EISA Video Programmable Option Select 4
5C8D  RW  EISA Video Programmable Option Select 5
5C8E  RW  EISA Video Programmable Option Select 6
5C8F  RW  EISA Video Programmable Option Select 7
--------X-P5C805C83--------------------------
PORT 5C80-5C83	EISA board product ID (board in slot 5)
SeeAlso: PORT 1C80h-1C83h
--------X-P5C84------------------------------
PORT 5C84 - EISA CONFIGURATION FLAGS (board in slot 5)

5C84  RW  configuration flags (see #P1016)
--------V-P5EE85EE9--------------------------
PORT 5EE8-5EE9 - C&T 82c480 - EXTENDED CONFIGURATION REGISTER 3
Note:	the 82c480 is an 8514/A-compatible video chipset
SeeAlso: PORT 52E8h"C&T",PORT 56E8h"C&T",PORT 5AE8h"C&T"

5EE8w RW  Extended Configuration Register 3
----------P5EEE------------------------------
PORT 5EEE - ATI Mach32 - MEMORY APERTURE CONFIGURATION REGISTER
SeeAlso: PORT 42EEh"Mach32"

5EEEw RW  Memory Aperture Configuration (see #P1023)

Bitfields for ATI Mach32 Memory Aperture Configuration Register:
Bit(s)	Description	(Table P1023)
 1-0	direct memory interface mapping
	00 disabled
	01 1M aperture (not on PCI)
	10 4M aperture
	11 reserved
 3-2	1M page select (not on PCI)
	00 page 0
	01 page 1
	10 page 2
	11 page 3
 11-8	(ISA) memory aperture location, 0-15 MB
 13-8	(EISA) memory aperture location, 0-63 MB
 14-8	(VLB) memory aperture location, 0-127 MB [*]
 15-4	(PCI) memory aperture location, 0-4095 MB
 13-8	(MCA 16-bit) memory aperture location, 0-63 MB
 14-8	(MCA 32-bit) memory aperture location, 0-127 MB
Note:	[*] if PORT 16EEh bit 3 is set and PORT FAEEh is non-zero, bits 15-4
	  are used to specify an address from 0-4095 MB
--------X-P600060FF--------------------------
PORT 6000-60FF - available for EISA slot 6
----------P62E062EF--------------------------
PORT 62E0-62EF - GPIB (General Purpose Interface Bus, IEEE 488 interface)

62E1  RW  GPIB (adapter 3)
--------V-P63C063CF--------------------------
PORT 63C0-63CF - Compaq QVision - BitBLT engine
--------X-P640064FF--------------------------
PORT 6400-64FF - available for EISA slot 6
--------V-P66EC------------------------------
PORT 66EC - ATI Mach64 - ???
SeeAlso: PORT 6AECh"Mach64"
--------X-P680068FF--------------------------
PORT 6800-68FF - available for EISA slot 6
--------V-P6AEC6AED--------------------------
PORT 6AEC-6AED - ATI Mach64 - ???
SeeAlso: PORT 66ECh"Mach64"
--------V-P6AEE------------------------------
PORT 6AEE - ATI Mach8/Mach32 - MAXIMUM WAIT STATES
SeeAlso: PORT 36EEh,PORT 6EEEh,PORT 76EEh,PORT 7AEEh,PORT 8EEEh

6AEE  RW  maximum wait states (see #P1024)

Bitfields for ATI Mach8/Mach32 wait state configuration:
Bit(s)	Description	(Table P1024)
 10	leave alone ("PASSTHROUGH_OVERRIDE")
 9	enable for 16-bit I/O
 8	0=horizontal degree-mode line draws
--------X-P6C006CFF--------------------------
PORT 6C00-6CFF - available for EISA slot 6
--------d-P6C006CBF--------------------------
PORT 6C00-6CBF -  Adaptec AIC-777x EISA SCSI controller in EISA slot 6
SeeAlso: PORT 0340h-035Fh"Adaptec AHA-154x",PORT xxxxh"Adaptec AIC-78xx"
--------X-P6C806C83--------------------------
PORT 6C80-6C83 - EISA board product ID (board in slot 6)
SeeAlso: PORT 1C80h-1C83h
--------V-P6C806C8F--------------------------
PORT 6C80-6C8F - VESA XGA Video in EISA slot 1
SeeAlso: PORT 1C80h-1C8Fh"XGA",PORT 2C80h-2C8Fh"XGA",PORT 5C80h-5C8Fh"XGA"

6C80d RW  EISA Video ID (see PORT 1C80h-1C83h)
6C84  RW  EISA Video expansion board control
6C85  RW  EISA Setup control
6C88  RW  EISA Video Programmable Option Select 0
6C89  RW  EISA Video Programmable Option Select 1
6C8A  RW  EISA Video Programmable Option Select 2
6C8B  RW  EISA Video Programmable Option Select 3
6C8C  RW  EISA Video Programmable Option Select 4
6C8D  RW  EISA Video Programmable Option Select 5
6C8E  RW  EISA Video Programmable Option Select 6
6C8F  RW  EISA Video Programmable Option Select 7
--------X-P6C84------------------------------
PORT 6C84 - EISA CONFIGURATION FLAGS (board in slot 6)

6C84  RW  configuration flags (see #P1016)
--------V-P6EEC------------------------------
PORT 6EEC - ATI Mach64 - ???
SeeAlso: PORT 6AECh"Mach64"
--------V-P6EEE------------------------------
PORT 6EEE - ATI Mach8/Mach32 - ENGINE VIDEO BUFFER OFFSET LOW
SeeAlso: PORT 72EEh

6AEEw -W  low 16 bits of video buffer starting offset
--------X-P700070FF--------------------------
PORT 7000-70FF - available for EISA slot 7
--------V-P72EC------------------------------
PORT 72EC - ATI Mach64 - ???
SeeAlso: PORT 66ECh"Mach64",PORT 72EFh"Mach64"
--------V-P72EE------------------------------
PORT 72EE - ATI Mach8/Mach32 - ENGINE VIDEO BUFFER OFFSET HIGH
SeeAlso: PORT 6EEEh

72EE  -W  high bits of video buffer starting offset
		bits 1-0 for Mach-8
		bits 3-0 for Mach-32
--------V-P72EE------------------------------
PORT 72EE - ATI Mach8/Mach32 - BOUNDS ACCUMULATOR (LEFT)
SeeAlso: PORT 76EEh"BOUNDS",PORT 7AEEh"BOUNDS",PORT 7EEEh"BOUNDS"

72EEw R-  left edge of bounding box for points written via Line Draw register
--------V-P72EF------------------------------
PORT 72EF - ATI Mach64 - ???
SeeAlso: PORT 66ECh"Mach64",PORT 72ECh"Mach64"
--------X-P740074FF--------------------------
PORT 7400-74FF - available for EISA slot 7
--------V-P76EE------------------------------
PORT 76EE - ATI Mach8/Mach32 - ENGINE DISPLAY PITCH
SeeAlso: PORT 6AEEh,PORT 7AEEh

76EE  -W  display pitch
--------V-P76EE------------------------------
PORT 76EE - ATI Mach8/Mach32 - BOUNDS ACCUMULATOR (TOP)
SeeAlso: PORT 72EEh"BOUNDS",PORT 7AEEh"BOUNDS",PORT 7EEEh"BOUNDS"

76EEw R-  top edge of bounding box for points written via Line Draw register
--------X-P780078FF--------------------------
PORT 7800-78FF - available for EISA slot 7
--------V-P7AEE------------------------------
PORT 7AEE - ATI Mach8/Mach32 - EXTENDED GRAPHICS ENGINE CONGIFURATION
SeeAlso: PORT 8EEEh

7AEEw -W  extended graphics engine configuration (see #P1025)

Bitfields for Mach8/Mach32 extended graphics engine configuration:
Bit(s)	Description	(Table P1025)
 15	drawing pixel size to be written next (68800-6 only)
 14	enable 8-bit DAC (Mach-32 only)
 13-12	DAC address inputs RS(3:2) control (Mach-32 only)
 11	display pixel size to be written next (68800-6 only)
 10	24-bit color order (Mach-32 only)
	0 = RGB
	1 = BGR
 9	24-bit color configuration: pixels use 4 bytes instead of three
 8	DAC processes four pixels in parallel (Mach-32 only)
 7-6	16-bits-per-color word format (Mach-32 only)
	00 RGB(5,5,5)
	01 RGB(5,6,5)
	10 RGB(6,5,5)
	11 RGB(6,6,4)
 5-4	number of bits per pixel (Mach-32 only)
	00 four
	01 eight
	10 sixteen
	11 twenty-four
 3	report monitor alias instead of actual monitor
 2-0	alternate monitor ID (alias)
--------V-P7AEE------------------------------
PORT 7AEE - ATI Mach8/Mach32 - BOUNDS ACCUMULATOR (RIGHT)
SeeAlso: PORT 72EEh"BOUNDS",PORT 76EEh"BOUNDS",PORT 7EEEh"BOUNDS"

7AEEw R-  right edge of bounding box for points written via Line Draw register
--------X-P7C007CFF--------------------------
PORT 7C00-7CFF - available for EISA slot 7
--------d-P7C007CBF--------------------------
PORT 7C00-7CBF -  Adaptec AIC-777x EISA SCSI controller in EISA slot 7
SeeAlso: PORT 0340h-035Fh"Adaptec AHA-154x",PORT xxxxh"Adaptec AIC-78xx"
--------X-P7C807C83--------------------------
PORT 7C80-7C83 - EISA board product ID (board in slot 7)
SeeAlso: PORT 1C80h-1C83h
--------V-P7C807C8F--------------------------
PORT 7C80-7C8F - VESA XGA Video in EISA slot 7
SeeAlso: PORT 1C80h-1C8Fh,PORT 6C80h-6C8Fh

7C80-7C83  RW	EISA Video ID
7C84  RW	EISA Video expansion board control
7C85  RW	EISA Setup control
7C88  RW	EISA Video Programmable Option Select 0
7C89-7C8F  RW	EISA Video Programmable Option Select 1-7
--------X-P7C84------------------------------
PORT 7C84 - EISA CONFIGURATION FLAGS (board in slot 7)

7C84  RW  configuration flags (see #P1016)
--------V-P7EEE------------------------------
PORT 7EEE - ATI Mach8/Mach32 - BOUNDS ACCUMULATOR (RIGHT)
SeeAlso: PORT 72EEh"BOUNDS",PORT 76EEh"BOUNDS",PORT 7AEEh"BOUNDS"

7EEEw R-  right edge of bounding box for points written via Line Draw register
--------X-P800080FF--------------------------
PORT 8000-80FF - available for EISA slot 8
----------P82E082EF--------------------------
PORT 82E0-82EF - GPIB (General Purpose Interface Bus, IEEE 488 interface)

82E1  RW  GPIB (adapter 4)
--------V-P82E882E9--------------------------
PORT 82E8-82E9 - 8514/A and compatible - CURRENT Y POSITION
Notes:	supported by ATI Mach8 and Mach32 chipsets
	supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT 86E8h,PORT 82EAh

82E8w -W  drawing control: current Y position
--------V-P82EA82EB--------------------------
PORT 82EA-82EB - S3 Trio64 - CURRENT Y POSITION 2
SeeAlso: PORT 82E8h

82EAw	  drawing control: current Y position 2
--------S-P82F882FF--------------------------
PORT 82F8-82FF - serial port, description same as 03F8
--------V-P83C083CF--------------------------
PORT 83C0-83CF - Compaq QVision - Line Draw Engine
--------V-P83C4------------------------------
PORT 83C4 - Compaq Qvision EISA - Virtual Controller Select
--------V-P83C683C9--------------------------
PORT 83C6-83C9 - Compaq Qvision EISA - DAC color registers
SeeAlso: PORT 03C6h
--------V-P83C683C9--------------------------
PORT 83C6-83C9 - Chips&Technologies 64200 (Wingine) - DAC color registers
SeeAlso: PORT 03C6h

83C6  RW  color palette pixel mask
83C7  R-  color palette state
83C7  -W  color palette read-mode index
83C8  RW  color palette write-mode index
83C9  RW  color palette data (three bytes)
----------P83D09FD3--------------------------
PORT 83D0-9FD3 - Chips&Techs 64310 - 32-BIT EXTENSION REGS - BitBLT
Notes:	All ports are word or dword accessible.
	These registers are also accessible in the upper 2 MB of the 4 MB
	  linear memory frame buffer (address specified in PCI configuration
	  registers).
SeeAlso: PORT 03D6h"Chips",PORT A3D0h"Chips"

83D0d RW  "DR00"  BitBlt offset register (see #P1026)
87D0d RW  "DR01"  BitBlt pattern ROP register (see #P1027)
8BD0d RW  "DR02"  BitBlt background color register (see #P1028)
8FD0d RW  "DR03"  BitBlt foreground color register (see #P1029)
93D0d RW  "DR04"  BitBlt control register (see #P1030)
97D0d RW  "DR05"  BitBlt source register (see #P1031)
9BD0d RW  "DR06"  BitBlt destination register (see #P1032)
9FD0d RW  "DR07"  BitBlt command register (see #P1033)

Bitfields for Chips&Technologies 64310 "DR00" BitBlt offset register:
Bit(s)	Description	(Table P1026)
 31-28	reserved (0)
 27-16	destination offset
 15-12	reserved (0)
 11-0	source offset

Bitfields for Chips&Technologies 64310 "DR01" BitBlt pattern ROP register:
Bit(s)	Description	(Table P1027)
 31-21	reserved (0)
 20-0	pattern pointer (must be pattern size aligned)
Note:	Do not read this register while BitBlt is active.

Bitfields for Chips&Technologies 64310 "DR02" BitBlt background color register:
Bit(s)	Description	(Table P1028)
 31-16	reserved (contents of bits 15-0 on read)
 15-0	background color for opaque mono-color expansions
	(all bits must be used; use same data in bits 15-8 and 7-0 for 8BPP)

Bitfields for Chips&Technologies 64310 "DR03" BitBlt foreground color register:
Bit(s)	Description	(Table P1029)
 31-16	reserved (contents of bits 15-0 on read)
 15-0	foreground color for mono-color expansions/color for solid paint
	  operations
	(all bits must be used; use same data in bits 15-8 and 7-0 for 8BPP)

Bitfields for Chips&Technologies 64310 "DR04" BitBlt control register:
Bit(s)	Description	(Table P1030)
 31-28	reserved (0)
 27-24	buffer status (number of dwords that can be written to the chip)
 23-21	reserved (0)
 20	BitBlt status (read-only)
	0 = idle
	1 = active (do not write BitBlt registers)
 19	0 = bitmap pattern
	1 = solid pattern (brush)
 18-16	pattern starting row
 15-14	BitBlt source (destination always video frame buffer)
	00 = video frame buffer
	01 = system memory
	1x = reserved
 13	background for monochrome pattern and font expansion
	0 = opaque (color in DR02)
	1 = transparent (unchanged)
 12	pattern depth
	0 = color
	1 = monochrome
 11	source depth
	0 = color
	1 = monochrome (font expansion only if bit 9 = 1)
 10	source data
	0 = selected by bit 14
	1 = foreground color reg (DR03)
 9	X direction (use when source and destination areas overlap)
	0 = decrement (right to left)
	1 = increment (left to right)
 8	Y direction (use when source and destination areas overlap)
	0 = decrement (bottom to top)
	1 = increment (top to bottom)
 7-0	raster operation (as defined by Windows)
SeeAlso: #P1031,#P1033

Bitfields for Chips&Technologies 64310 "DR05" BitBlt source register:
Bit(s)	Description	(Table P1031)
 31-21	reserved (0)
 20-0	source block address (must be byte aligned)
Note:	Do not read this register while BitBlt is active.
SeeAlso: #P1030,#P1032

Bitfields for Chips&Technologies 64310 "DR06" BitBlt destination register:
Bit(s)	Description	(Table P1032)
 31-21	reserved (0)
 20-0	destination block address (must be byte aligned)
Note:	Do not read this register while BitBlt is active.
SeeAlso: #P1031,#P1033

Bitfields for Chips&Technologies 64310 "DR07" BitBlt command register:
Bit(s)	Description	(Table P1033)
 31-28	reserved (0)
 27-16	lines per block
 15-12	reserved (0)
 11-0	bytes per line
SeeAlso: #P1031,#P1032
--------S-P83F883FF--------------------------
PORT 83F8-83FF - serial port, description same as 03F8
--------X-P840084FF--------------------------
PORT 8400-84FF - available for EISA slot 8
--------V-P86E886E9--------------------------
PORT 86E8-86E9 - 8514/A and compatible - CURRENT X POSITION
Desc:	define the column at which the first pixel of a line, rectangle, etc.
	  will be drawn; (Trio64) define the column at which the first of two
	  edges for a polygon or trapezoid will begin
Notes:	supported by ATI Mach8 and Mach32 chipsets
	supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT 82E8h,PORT 8AE8h,86EAh

86E8w -W  drawing control: current X position (bits 11-0)
--------V-P86EA86EB--------------------------
PORT 86EA-86EB - S3 Trio64 - CURRENT X POSITION 2
Desc:	define the column at which the second of two edges for a polygon or
	  trapezoid will begin
SeeAlso: PORT 86E8h

86EAw RW  drawing control: current X position 2 (bits 11-0)
--------X-P880088FF--------------------------
PORT 8800-88FF - available for EISA slot 8
--------V-P8AE88AE9--------------------------
PORT 8AE8-8AE9 - 8514/A and compatible - DESTINATION Y POSITION
Desc:	define the top row of the destination for a BLT, the axial step
	  constant for a line, or the ending row of a line segment in a
	  polyline; (Trio64) define the ending row of the first edge drawn
	  for a polygon or trapezoid
Notes:	supported by ATI Mach8 and Mach32 chipsets
	supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT 82E8h,PORT 86E8h

8AE8w -W  drawing control: destination Y position / axial step constant
	  (see #P1034)
Note:	this port may be read on S3 chipsets

Bitfields for 8514/A destination Y position / axial step constant register:
Bit(s)	Description	(Table P1034)
 11-0	destination Y position
 13-0	axial step constant for line drawing
 15-14	reserved
--------V-P8AEA8AEB--------------------------
PORT 8AEA-8AEB - S3 Trio64 - DESTINATION Y COORD 2 / AXIAL STEP CONSTANT 2
Desc:	define the row at which the second of two edges for a polygon or
	  trapezoid will end, or the axial step constant for the second of
	  two edges for a Bresenham trapezoid
SeeAlso: PORT 8AE8h

8AEAw RW  drawing control: destination Y position 2 / axial step constant 2
	  (see #P1034)
--------X-P8C008CFF--------------------------
PORT 8C00-8CFF - available for EISA slot 8
--------X-P8C808C83--------------------------
PORT 8C80-8C83 - EISA board product ID (board in slot 8)
SeeAlso: PORT 1C80h-1C83h
--------X-P8C84------------------------------
PORT 8C84 - EISA CONFIGURATION FLAGS (board in slot 8)

8C84  RW  configuration flags (see #P1016)
--------V-P8EE88EE9--------------------------
PORT 8EE8-8EE9 - 8514/A and compatible - DESTINATION X POSITION
Desc:	define the left column of the destination for a BLT, the diagonal step
	  constant for a line, or the ending column of a line segment in a
	  polyline; (Trio64) define the ending column of the first edge drawn
	  for a polygon or trapezoid
Notes:	supported by ATI Mach8 and Mach32 chipsets
	supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT DAEEh"Mach32",PORT 8EEAh

8EE8w -W  drawing control: destination X position / axial step constant
	  (see #P1034)
--------V-P8EEA8EEB--------------------------
PORT 8EEA-8EEB - S3 Trio64 - DESTINATION X COORD 2 / AXIAL STEP CONSTANT 2
Desc:	define the column at which the second of two edges for a polygon or
	  trapezoid will end, or the axial step constant for the second of
	  two edges for a Bresenham trapezoid
SeeAlso: PORT 8EE8h

8EEAw RW  drawing control: destination X position 2 / diagonal step constant 2
	  (see #P1034)
--------V-P8EEE------------------------------
PORT 8EEE - ATI Mach32 - READ EXTENDED GRAPHICS CONFIGURATION
SeeAlso: PORT 72EEh

8EEE  R-  read extended graphics configuration (see #P1025)
--------X-P900090FF--------------------------
PORT 9000-90FF - available for EISA slot 9
--------V-P92E892E9--------------------------
PORT 92E8-92E9 - 8514/A and compatible - BRESENHAM ERROR TERM
Desc:	specify the initial error term for drawing a line using the Bresenham
	  algorithm
Notes:	supported by ATI Mach8 and Mach32 chipsets
	supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
	the error term is 2*min(|dx|,|dy|) - max(|dx|,|dy|) - 1 [startX < endX]
	or 2*min(|dx|,|dy|) - max(|dx|,|dy|) [startX >= endX]
SeeAlso: PORT 92EAh

92E8w -W  drawing control: Bresenham error term (bits 13-0)
--------V-P92EA92EB--------------------------
PORT 92EA-92EB - S3 Trio64 - LINE ERROR TERM 2
Desc:	specify the initial error term for the second edge of a Bresenham
	  trapezoid
SeeAlso: PORT 92E8h

92EAw RW  drawing control: Bresenham error term 2 (bits 13-0)
--------X-P940094FF--------------------------
PORT 9400-94FF - available for EISA slot 9
--------V-P96E896E9--------------------------
PORT 96E8-96E9 - 8514/A and compatible - MAJOR AXIS PIXEL COUNT
Desc:	specify the pixel length of the longest axis of a line, or the width
	  of a rectangle, BLT, or image transfer; (Trio64) specify the major
	  axis length of the first edge of a Bresenham trapezoid
Notes:	supported by ATI Mach8 and Mach32 chipsets
	supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
	the value programmed into this register is one less than the desired
	  width or major-axis length
SeeAlso: PORT 96EAh

96E8w R-  enter WD Enhanced Mode
96E8w -W  drawing control: major axis pixel count (bits 11-0)
--------V-P96EA96EB--------------------------
PORT 96EA-96EB - S3 Trio64 - MAJOR AXIS PIXEL COUNT 2
Desc:	specify the major axis length of the second edge for a Bresenham
	  trapezoid
Note:	the value programmed into this register is one less than the desired
	  width or major-axis length
SeeAlso: PORT 96E8h

96EAw RW  drawing control: major axis pixel count 2 (bits 11-0)
--------X-P980098FF--------------------------
PORT 9800-98FF - available for EISA slot 9
--------V-P9AE89AE9--------------------------
PORT 9AE8-9AE9 - 8514/A and compatible - GRAPHICS PROCESSOR STATUS / COMMAND
Notes:	supported by ATI Mach8 and Mach32 chipsets
	supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT 9AEAh

9AE8w R-  drawing control: graphic processor status (see #P1035)
9AE8w -W  drawing control: command register (see #P1036)

Bitfields for 8514/A graphic processor status:
Bit(s)	Description	(Table P1035)
 15-10	(8514/A) reserved
 15	(S3 Trio64 only) queue status flags 9
 14-11	(S3 Trio64 only) queue status flags 10-13
 10	(S3 Trio64 only) all FIFO slots are empty
 9	hardware busy
 8	(8514/A) data ready
	(S3 Trio64) reserved
 7	queue status flag 1
 6-0	queue status flags 2-8 (0=empty, 1=filled)
	(each bit represents a position in queue)
Note:	queue status flag N is cleared whenever at least N slots are available
	  in the FIFO; at any given time, the CPU may write only as many values
	  to the FIFO as there are slots available
SeeAlso: #P1036

Bitfields for 8514/A command register :
Bit(s)	Description	(Table P1036)
 15-13	command (see #P1037)
 12	byte sequence (0=high byte first, 1=low byte first)
 11-10	(8514/A) reserved
 11	(S3 Trio) high bit of command (see #P1037)
 10	(S3 Trio) enable 32-bit write access
 9	enable 16-bit write access (16BIT)
 8	0=use 8514/A data, 1=pixel data trans reg (PCDATA) (see PORT E2E8h)
 7	0=draw vector above, 1=draw vector below (INC_Y)
 6	0=x is maj. axis, 1=y is maj. axis (YMAJAXIS)
 5	0=draw vector left, 1=draw vector right (INC_X)
	(bits 7-5 are the drawing direction in 45-degree increments
	  counterclockwise from the X axis when bit 3 is set)
 4	0=move only, 1=draw and move (DRAW)
 3	0=Bresenham line, 1=direct vector (LINETYPE)
 2	0=draw last pixel, 1=don't draw last pixel (LASTPIX)
 1	0=single pixel, 1=4pixel (PLANAR)
 0	0=read data, 1=write data (RD/WR) (must be 1 on S3 Trio)
SeeAlso: #P1035,#P1038

(Table P1037)
Values for 8514/A command:
 000	no operation (used to force synchronization with graphics processor,
	  or to set up short stroke vector drawing without writing any pixels)
 001	draw vector
 010	fast rectangle fill
 011	(8514/A) rectangle fill vertical #1
	(S3 Trio64) polygon fill solid
 100	(8514/A) rectangle fill vertical #2 (4 pixels)
	(S3 Trio64) 4-point trapezoid fill solid
 101	(8514/A) draw vector, 1 pixel/scanline
	(S3 Trio64) Bresenham trapezoid fill solid
 110	copy rectangle
 111	(8514/A) reserved
	(S3 Trio64) patterned BLT
---S3 Trio64---
 1001	polyline / 2-point line
 1011	polygon fill pattern
 1100	4-point trapezoid fill pattern
 1101	Bresenham trapezoid fill pattern
SeeAlso: #P1036
--------V-P9AEA9AEB--------------------------
PORT 9AEA-9AEB - S3 Trio64 - DRAWING COMMAND 2
Desc:	specify the drawing direction for the second edge of a Bresenham
	  trapezoid
SeeAlso: PORT 9AE8h

9AEAw -W  drawing command 2 (see #P1038)

Bitfields for S3 Trio64 Drawing Command 2 register:
Bit(s)	Description	(Table P1038)
 15-8	reserved
 7-5	drawing direction
	 7	0=draw vector above, 1=draw vector below (INC_Y)
	 6	0=x is maj. axis, 1=y is maj. axis (YMAJAXIS)
	 5	0=draw vector left, 1=draw vector right (INC_X)
 4-0	reserved
SeeAlso: #P1036
--------V-P9AEE------------------------------
PORT 9AEE - ATI Mach8/Mach32 - LINEDRAW INDEX REGISTER
SeeAlso: PORT FEEEh

9AEE  -W  linedraw index register (specifies interpretation of PORT FEEEh)
	  (see #P1039)

(Table P1039)
Values for ATI Mach8/Mach32 Linedraw Index Register:
 00h	set current X
 01h	set current Y
 02h	set Line End X
 03h	set Line End Y, draw line, and reset register to 02h
 04h	set current X (perform moves instead of draws)
 05h	set current Y and reset register to 04h
--------X-P9C009CFF--------------------------
PORT 9C00-9CFF - available for EISA slot 9
--------X-P9C809C83--------------------------
PORT 9C80-9C83 - EISA board product ID (board in slot 9)
SeeAlso: PORT 1C80h-1C83h
--------X-P9C84------------------------------
PORT 9C84 - EISA CONFIGURATION FLAGS (board in slot 9)

9C84  RW  configuration flags (see #P1016)
--------V-P9EE89EE9--------------------------
PORT 9EE8-9EE9 - 8514/A and compatible - SHORT STROKE VECTORS
Desc:	specify two short-stroke vectors to be drawn one after the other
Notes:	supported by ATI Mach8 and Mach32 chipsets
	supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
	bit 12 of the command register (see PORT 9AE8h,#P1036) specifies which
	  vector is drawn first

9EE8w -W  short line vector transfer (see #P1040)

Bitfields for 8514/A short-stroke vector:
Bit(s)	Description	(Table P1040)
 15-13	second vector: drawing direction
 12	second vector: draw/move
 11-0	second vector: length in pixels (less 1)
 7-5	first vector: drawing direction
	000  zero degrees = right
	001  45 degress = up and right
	010  90 degrees = up
	...
	111 315 degrees = down and right
 4	first vector: draw/move (=0 move only, =1 draw and move)
 3-0	first vector: length in pixels (less 1)
--------S-PA220------------------------------
PORT A220 - soundblaster support in AMI Hi-Flex BIOS  ????
----------PA2E0A2EF--------------------------
PORT A2E0-A2EF - GPIB (General Purpose Interface Bus, IEEE 488 interface)

A2E1  RW  GPIB (adapter 5)
--------V-PA2E8A2EB--------------------------
PORT A2E8-A2EB - 8514/A and compatible - BACKGROUND COLOR
Notes:	supported by ATI Mach8 and Mach32 chipsets
	supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT A6E8h

A2E8w -W  drawing control: background color
A2E8d RW  (S3) drawing control: 32bpp background color
--------V-PA2EEA2EF--------------------------
PORT A2EE-A2EF - ATI Mach8/Mach32 - LINE DRAW OPTIONS
SeeAlso: PORT 8EEEh,PORT CEEEh

A2EEw RW  line drawing options (see #P1041)

Bitfields for ATI Mach8/Mach32 line drawing options:
Bit(s)	Description	(Table P1041)
 10-9	clipping mode
	00 disable clip exception
	01 stroked plain lines
	10 polygon boundary lines
	11 patterned lines
 8	reset all Bounds Accumulator registers
 7-5	OCTANT: direction for BitBlts or lines
 3	direction specification
	0 = Bresenham/Octant
		bit 7: increment Y
		bit 6: Y is major axis instead of X
		bit 5: increment X
	1 = line-length and degrees
		OCTANT field species N*45 degrees
 2	do NOT draw last pixel of a line
 1	polyline draw
----------PA3D0BFD3--------------------------
PORT A3D0-BFD3 - Chips&Techs 64310 - 32-BIT EXTENSION REGS - CURSOR CONTROL
Notes:	All ports are word or dword accessible.
	These registers are also accessible in the upper 2 MB of the 4 MB
	  linear memory frame buffer (address specified in PCI configuration
	  registers).
SeeAlso: PORT 03D6h"Chips",PORT 83D0h"Chips"

A3D0d RW  "DR08"  cursor control register (see #P1042)
A7D0d RW  "DR09"  cursor color register (see #P1043)
ABD0d --  "DR0A"  reserved
AFD0d RW  "DR0B"  cursor position register (see #P1044)
B3D0d RW  "DR0C"  cursor base address (see #P1045)
B7D0d --  "DR0D"  reserved
BBD0d --  "DR0E"  reserved
BFD0d --  "DR0F"  reserved

Bitfields for Chips&Technologies 64310 "DR08" cursor control register:
Bit(s)	Description	(Table P1042)
 31-8	reserved (0)
 7-6	test (must be 0)
 5	upper left corner (ULC) select
	(all x, y positioning is relative to selected ULC)
	0 = active display (BLANK#) (cursor can be positioned in overscan
	  area)
	1 = display enable (cursor cannot be positioned to overscan area)
 4-2	reserved (must be 0)
 1-0	hardware cursor enable
	00 = disable
	01 = 32x32 cursor enable
	10 = 64x64 cursor enable
	11 = illegal/reserved

Bitfields for Chips&Technologies 64310 "DR09" cursor color register:
Bit(s)	Description	(Table P1043)
 31-27	cursor color 1 red
 26-21	cursor color 1 green
 20-16	cursor color 1 blue
 15-11	cursor color 0 red
 10-5	cursor color 0 green
 4-0	cursor color 0 blue
SeeAlso: #P1044,#P1045

Bitfields for Chips&Technologies 64310 "DR0B" cursor position register:
Bit(s)	Description	(Table P1044)
 31	Y sign
 30-27	reserved (0)
 26-16	cursor position Y offset from ULC (DR08 bit 5)
 15	X sign
 14-11	reserved (0) (ignored)
 10-0	cursor position X offset from ULC (DR08 bit 5)
SeeAlso: #P1043,#P1045

Bitfields for Chips&Technologies 64310 "DR0C" cursor base address:
Bit(s)	Description	(Table P1045)
 31-21	reserved (0)
 20-10	base address for cursor data in display memory
	(cursor data must be at 1K boundary in off-screen memory)
 9-0	reserved (0)
SeeAlso: #P1043,#P1044
--------V-PA6E8A6EB--------------------------
PORT A6E8-A6EB - 8514/A and compatible - FOREGROUND COLOR
Notes:	supported by ATI Mach8 and Mach32 chipsets
	supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT A2E8h,PORT AAE8h,PORT AEE8h

A6E8w -W  drawing control: foreground color
A6E8d RW  (S3) drawing control: foreground color for 32bpp modes
--------V-PAAE8AAEB--------------------------
PORT AAE8-AAEB - 8514/A and compatible - WRITE MASK
Desc:	specify which bit planes are updates when a pixel is written
Notes:	supported by ATI Mach8 and Mach32 chipsets
	supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT A6E8h,PORT AEE8h

AAE8w -W  drawing control: write mask
AAE8d RW  (S3) drawing control: write mask for 32bpp modes
--------V-PAEE8AEEB--------------------------
PORT AEE8-AEEB - 8514/A and compatible - READ MASK
Desc:	specify which bit planes are used as a data source
Notes:	supported by ATI Mach8 and Mach32 chipsets
	supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT AAE8h,PORT B2E8h

AEE8w -W  drawing control: read mask
AEE8d RW  (S3) drawing control: read mask for 32bpp modes
--------V-PAFFF------------------------------
PORT AFFF - VIDEO REGISTER

AFFF  RW  plane 0-3 system latch (video register)
--------S-PB220B227--------------------------
PORT B220-B227 - serial port, description same as 03F8
--------S-PB228B22F--------------------------
PORT B228-B22F - serial port, description same as 03F8
--------V-PB2E8B2EB--------------------------
PORT B2E8-B2EB - 8514/A and compatible - COLOR COMPARE
Notes:	supported by ATI Graphics Ultra
	supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT B6E8h,PORT BAE8h,PORT BEE8h

B2E8w -W  drawing control: color compare
B2E8d RW  (S3) drawing control: color compare for 32bpp modes
--------V-PB2EE------------------------------
PORT B2EE - ATI Mach32 - ???

B2EEw RW  ???
--------V-PB6E8B6E9--------------------------
PORT B6E8-B6E9 - 8514/A and compatible - BACKGROUND MIX
Notes:	supported by ATI Mach8 and Mach32 chipsets
	supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT BAE8h,PORT BEE8h,PORT B2E8h

B6E8w -W  drawing control: background mix (see #P1046)
Note:	this register may be read on S3 chipsets
--------V-PB6EE------------------------------
PORT B6EE - ATI Mach32 - ???

B6EEw RW  ???
--------V-PBAE8BAE9--------------------------
PORT BAE8-BAE9 - 8514/A and compatible - FOREGROUND MIX
Notes:	supported by ATI Mach8 and Mach32 chipsets
	supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
SeeAlso: PORT B6E8h

BAE8w -W  drawing control: foreground mix (see #P1046)
Note:	this register may be read on S3 chipsets

Bitfields for 8514/A color mix register:
Bit(s)	Description	(Table P1046)
 15-7	reserved
 6-5	color source
	00 background color
	01 foreground color
	10 CPU data
	11 display memory
 4	reserved
 3-0	mix type
	0000 negate current color
	0001 logical zero
	0010 logical one
	0011 leave unchanged
	0100 negate new color
	0101 current XOR new
	0110 negate (current XOR new)
	0111 new color
	1000 (NOT current) OR (NOT new)
	1001 current OR (NOT new)
	1010 (NOT current) OR new
	1011 current OR new
	1100 current AND new
	1101 (NOT current) AND new
	1110 current AND (NOT new)
	1111 (NOT current) AND (NOT new)
--------V-PBAEE------------------------------
PORT BAEE - ATI Mach32 - ???

BAEEw RW  ???
--------V-PBEE8BEE9--------------------------
PORT BEE8-BEE9 - 8514/A and compatible - MULTIFUNCTION CONTROL
Notes:	supported by ATI Mach8 and Mach32 chipsets
	supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set
	writes to the registers accessed via this port are pipelined; a NOP
	  command (see PORT 9AE8h) is required to ensure correct read-back
	  immediately after a write

BEE8w -W  drawing control: multi-function control (see #P1048)
BEE8w R-  (S3) value of register specified by current value of multi-function
	  read select register (index 0Fh bits 3-0) (see #P1048)

(Table P1047)
Values for index into 8514/A multi-function drawing control registers:
 00h RW minor axis pixel count
 01h RW top scissors
 02h RW left scissors
 03h RW bottom scissors
 04h RW right scissors
 05h -W memory control register
 08h -W fixed pattern low
 09h -W fixed pattern high
 0Ah RW data manipulation control
---S3 chipsets---
 0Dh RW (S3 864/964) miscellaneous 2
 0Eh RW (S3 801+) miscellaneous
 0Fh -W (S3 801/805/928) read register select (see #P1049)
SeeAlso: #P1048

Bitfields for 8514/A Multi-Function Control registers:
Bit(s)	Description	(Table P1048)
 15-12	register index (see #P1047)
---register 00h: minor axis pixel count---
 11-0	rectangle height - 1
---register 01h: top scissors---
 11-0	top edge of clipping box
---register 02h: left scissors---
 11-0	left edge of clipping box
---register 03h: bottom scissors---
 11-0	bottom edge of clipping box
---register 04h: right scissors---
 11-0	right edge of clipping box
---register 05h: memory control---
 ???
---register 08h: fixed pattern low---
 11-8	(S3 Trio32/64) reserved
 7-6	mix register
	00 always select Foreground Mix register
	01 reserved
	10 mix register selected by CPU data
	11 mix register selected by display memory value
 5-0	(S3 Trio32/64) reserved
---register 09h: fixed pattern high---
 ???
---register 0Ah: data manipulation control---
 ???
---register 0Dh: miscellaneous 2---
 11-7	reserved
 6-4	source base address
	000 in first meg of display memory
	001 in second meg
	010 in third meg
	011 in fourth meg
 3	reserved
 2-0	destination base address (settings as for bits 6-4)
---register 0Eh: miscellaneous---
 11-10	reserved (0)
 9	select 32-bit command registers; disable byte and word writes to regs
	(see PORT A2E8h,PORT A6E8h,PORT AAE8h,PORT B2E8h)
 8	enable color comparison
 7	don't update bitmap if source color differs from Color Compare register
	  (see PORT B2E8h)
 6	slow Graphics Engine read/modify/write cycle (adds one wait state)
 5	clipping direction
	=0 draw only inside clip rectangle
	=1 draw only outside clip rectangle
 4	select upper 16 bits of 32-bit registers in 32 bpp graphics mode
 3-2	source base address, bits 21-20
 1-0	destination base address, bits 21-20
	Note:	these base addresses are ignored if the corresponding base
		  address in register 0Dh is nonzero
---register 0Fh: multifunction read select---
 11-4	reserved
 3-0	(S3)	read select (see #P1049)
 2-0	(8514/A) read select (see #P1049)

(Table P1049)
Values for S3 multifunction read select register:
 00h	PORT BEE8h register 00h
 01h	PORT BEE8h register 01h
 02h	PORT BEE8h register 02h
 03h	PORT BEE8h register 03h
 04h	PORT BEE8h register 04h
 05h	PORT BEE8h register 0Ah
 06h	PORT BEE8h register 0Eh
 07h	PORT 9AE8h (bits 11-0 only)
---S3 864/964 only---
 08h	PORT 42E8h (bits 11-0 only)
 09h	PORT 46E8h
 0Ah	PORT BEE8h register 0Dh
SeeAlso: #P1047,#P1048
--------X-PC000CFFF--------------------------
PORT C000-CFFF - PCI Configuration Mechanism 2 - CONFIGURATION SPACE
Note:	to access the configuration space, write the target bus number to
	  PORT 0CFAh, then write to the Configuration Space Enable register
	  (PORT 0CF8h), and finally read or write the appropriate I/O
	  port(s) in the range C000h to CFFFh (where Cxrrh accesses location
	  'rr' in physical device 'x's configuration data)
SeeAlso: PORT 0CF8h"Mechanism 2",PORT 0CFAh"Mechanism 2"
SeeAlso: #00878 at INT 1A/AX=B10Ah
--------d-PC100C1FF--------------------------
PORT C100-C1FF - Intel Pentium mboard - PCTech RZ1000 EIDE controller
Desc:	the PCI configuration registers for the EIDE controller are visible
	  on these ports when the PCI configuration space has been opened via
	  ports 0CF8h and 0CFAh
SeeAlso: PORT 03F0h"RZ1000",PORT 0CF8h,#00878 at INT 1A/AX=B10Ah
----------PC200C204--------------------------
PORT C200-C204 - Intel Pentium mboard ("Neptune" chipset)
Desc:	the PCI configuration registers for the motherboard chipset are visible
	  on these ports when the PCI configuration space has been opened via
	  ports 0CF8h and 0CFAh
SeeAlso: #00878 at INT 1A/AX=B10Ah
--------S-PC220C227--------------------------
PORT C220-C227 - serial port, description same as 03F8
--------S-PC228C22F--------------------------
PORT C228-C22F - serial port, description same as 03F8
----------PC244------------------------------
PORT C244 - Intel Pentium mboard ("Neptune" chipset)
----------PC2E0C2EF--------------------------
PORT C2E0-C2EF - GPIB (General Purpose Interface Bus, IEEE 488 interface)

C2E1  RW  GPIB (adapter 6)
--------V-PC2EE------------------------------
PORT C2EE - ATI Mach32 - ???

C2EEw RW  ???
--------V-PC6EE------------------------------
PORT C6EE - ATI Mach32 - SHORT-STROKE VECTOR

C6EEw -W  short-stroke vector
--------V-PCAEE------------------------------
PORT CAEE - ATI Mach32 - ???

CAEEw RW  ???
----------PCEEE------------------------------
PORT CEEE - ATI Mach8/Mach32 - DATAPATH CONFIGURATION
SeeAlso: PORT 8EEEh

CEEEw -W  datapath configuration (see #P1050)

Bitfields for ATI Mach8/Mach32 datapath configuration:
Bit(s)	Description	(Table P1050)
 15-13	foreground color source
	000 background color reg
	001 foreground color reg
	010 pixel transfer reg
	011 VRAM BitBlt source
	101 color pattern shift register
 12	least-significant byte first
 9	data width is 16 bits instead of 8 bits
 8-7	background color source
	00 background color reg
	01 foreground color reg
	10 pixel transfer reg
	11 VRAM BitBlt source
 6-5	monochrome data source
	00 always one
	01 mono pattern register
	10 pixel transfer register
	11 VRAM BitBlt source
 4	enable drawing
 2	read color data instead of monochrome data
 1	enable polygon fill BitBlt
 0	write data to drawing trajectory instead of reading from trajectory
--------S-PD220D227--------------------------
PORT D220-D227 - serial port, description same as 03F8
SeeAlso: PORT 03F8h,PORT D228h
--------S-PD228D22F--------------------------
PORT D228-D22F - serial port, description same as 03F8
SeeAlso: PORT 03F8h,PORT D220h
--------V-PD2EE------------------------------
PORT D2EE - ATI Mach32 - ???

D2EEw RW  ???
--------V-PDAEEDAEF--------------------------
PORT DAEE-DAEF - ATI Mach8/Mach32 - SCISSORS REGION (LEFT)
SeeAlso: PORT 8EE8h,PORT DEEEh"SCISSORS",PORT E2EEh"SCISSORS"
SeeAlso: PORT E6EEh"SCISSORS"

DAEEw -W  left edge of "scissors" drawing area (bits 11-0)
--------V-PDEEEDEEF--------------------------
PORT DEEE-DEEF - ATI Mach8/Mach32 - SCISSORS REGION (TOP)
SeeAlso: PORT DAEEh"SCISSORS",PORT E2EEh"SCISSORS",PORT E6EEh"SCISSORS"

DEEEw -W  top edge of "scissors" drawing area (bits 11-0)
----------PE2E0E2EF--------------------------
PORT E2E0-E2EF - GPIB (General Purpose Interface Bus, IEEE 488 interface)

E2E1  RW  GPIB (adapter 7)
--------V-PE2E8E2E9--------------------------
PORT E2E8-E2E9 - 8514/A and compatible - PIXEL DATA TRANSFER
Desc:	all graphics data to be processed by the Graphics Engine is sent
	  through this port
Notes:	supported by ATI Graphics Ultra
	supported by S3 chipsets when PORT 03D4h register 40h bit 0 is set

E2E8w -W  drawing control: pixel data transfer
E2EAw rW  drawing control: pixel data transfer (S3 801+) for 32-bit transfers
--------V-PE2EEE2EF--------------------------
PORT E2EE-E2EF - ATI Mach8/Mach32 - SCISSORS REGION (BOTTOM)
SeeAlso: PORT DAEEh"SCISSORS",PORT DEEEh"SCISSORS",PORT E6EEh"SCISSORS"

E2EEw -W  bottom edge of "scissors" drawing area (bits 11-0)
--------V-PE6EEE6EF--------------------------
PORT E6EE-E6EF - ATI Mach8/Mach32 - SCISSORS REGION (RIGHT)
SeeAlso: PORT DAEEh"SCISSORS",PORT DEEEh"SCISSORS",PORT E2EEh"SCISSORS"

E6EEw -W  right edge of "scissors" drawing area (bits 11-0)
--------V-PEAE8EAEB--------------------------
PORT EAE8-EAEB - S3 Trio64 - PATTERN
Desc:	define the position of the top-left corner of an 8x8 pixel pattern
	  stored in off-screen memory which is to be used for patterned fill
	  commands (trapezoid, polygon, etc.)

EAE8w RW  pattern Y coordinate (bits 11-0)
EAEAw RW  pattern X coordinate (bits 11-0)
--------V-PFAEE------------------------------
PORT FAEE - ATI Mach32 - CHIP IDENTIFICATION REGISTER
SeeAlso: PORT 56EEh"Mach32",PORT 5EEEh"Mach32"
--------V-PFEEEFEEF--------------------------
PORT FEEE-FEEF - ATI Mach8/Mach32 - DIRECT LINE DRAW REGISTER
SeeAlso: PORT 9AEEh

FEEEw -W  direct line-draw register
--------d-Pxxxx------------------------------
PORT xxxx - Future Domain TMC-3260 PCI SCSI adapter
Range:	anywhere on 8 byte boundary???
Note:	Future Domain TMC-3260 PCI SCSI adapter is based upon Future Domain
	  TMC-36C70 SCSI controller which is a PCI version of the TMC-18C30
	  ISA SCSI controller
SeeAlso: PORT 0140h-014Fh"Future Domain TMC-16x0"
--------d-Pxxxx------------------------------
PORT xxxx - AMD Am53C974A PC-SCSI II SCSI adapter
Range:	anywhere, on a 128-port boundary
SeeAlso: #00925

+000  R-  current transfer count register (low)
+000  -W  start transfer count register (low)
+004  R-  current transfer count register (middle)
+004  -W  start transfer count register (middle)
+008  RW  SCSI FIFO register
+00C  RW  SCSI command register
+010  R-  SCSI status register
+010  -W  destination ID
+014  R-  interrupt status
+014  -W  SCSI timeout
+018  R-  internal state
+018  -W  synchronous transfer period
+01C  R-  current FIFO/internal state
+01C  -W  synchronous offset
+020  RW  control register 1
+024  -W  clock factor
+028  -W  reserved
+02C  RW  control register 2
+030  RW  control register 3
+034  RW  control register 4
+038  R-  current transfer count register (high) / ID code
+038  -W  start current transfer count (high)
+03C	  reserved
+040  RW  DMA command
+044d RW  DMA starting transfer count (bits 23-0)
+048d RW  DMA starting physical address
+04C  R	  DMA working byte counter
+050d R	  DMA working address counter
+054  R	  DMA status register
+058d RW  DMA starting memory descriptor list address
+05Cd R	  DMA working memory descriptor list counter
+070d Rw  SCSI bus and control (bits 25-24 and 21-0)
Notes:	the SCSI registers are mapped on DWORD boundaries, even though for most
	  only the least-significant byte is used
	see "Am53C974A PCscsi(tm) II Technical Manual, Revision 1.0"
	  (file 19113A.PDF) for further details, as well as (file 19084A.PDF)
--------d-Pxxxx------------------------------
PORT xxxx - Adaptec AHA-2920 PCI SCSI adapter
Range:	anywhere on 8 byte boundary???
Note:	Adaptec AHA-2920 PCI SCSI adapter is based upon Future Domain TMC-36C70
	  SCSI controller which is a PCI version of Future Domain TMC-18C30 ISA
	  SCSI controller
SeeAlso: PORT 0140h-014Fh"Future Domain TMC-16x0"
--------d-Pxxxx------------------------------
PORT xxxx -  Adaptec AIC-78xx PCI SCSI controller
Range:	anywhere on 256-byte boundary
Note:	Adaptec AIC-78xx SCSI controllers are basically compatible with the
	  AIC-777x SCSI controllers
SeeAlso: PORT 0340h-035Fh"Adaptec AHA-152x",PORT 1C00h-1CBFh"Adaptec AIC-777x"

+000  RW  SCSI sequence control register (SCSISEQ) (see #P0600)
+001  RW  SCSI transfer control register 0 (SXFRCTL0) (see #P0979)
+002  RW  SCSI transfer control register 1 (SXFRCTL1) (see #P0980)
+003  R-  SCSI control signal read  register (SCSISIGI) (see #P0603)
+003  -W  SCSI control signal write register (SCSISIGO) (see #P0604)
+004  RW  SCSI rate control register (SCSIRATE) (see #P0981)
+005  RW  SCSI ID register (SCSIID) (see #P0982)
+006  RW  SCSI latched data low register (SCSIDATL)
	  read/write causes -ACK to pulse
+007  RW  (Wide SCSI) SCSI latched data high register (SCSIDATH)
	  read/write causes -ACK to pulse
+008  RW  SCSI transfer count register (STCNT) (3 bytes long)
+00B  R-  SCSI status register 0 (SSTAT0) (see #P0607)
+00B  -W  clear SCSI interrupt register 0 (CLRSINT0) (see #P0983)
+00C  R-  SCSI status register 1 (SSTAT1) (see #P0609)
+00C  -W  clear SCSI interrupt register 1 (CLRSINT1) (see #P0610)
+00D  R-  SCSI status register 2 (SSTAT2) (see #P0984)
+00E  R-  SCSI status register 3 (SSTAT3) (see #P0612)
+00F  RW  SCSI test control register (SCSITEST) (see #P0985)
+010  RW  SCSI interrupt mode register 0 (SIMODE0) (see #P0616)
+011  RW  SCSI interrupt mode register 1 (SIMODE1) (see #P0617)
+012  RW  SCSI data bus low register (SCSIBUSL)
+013  RW  (Wide SCSI) SCSI data bus high register (SCSIBUSH)
+014d R-  SCSI/host address register (SHADDR)
+018  RW  selection timeout timer  register (SELTIMER) (see #P0986)
+019  RW  selection/reselection ID register (SELID)  (see #P0987)
+01D  ??  (AIC-7870) board control register (BRDCTL) (see #P1051)
+01E  RW  (AIC-787x/788x) serial EEPROM control register (SEECTL) (see #P1052)
+01F  RW  SCSI block control register (SBLKCTL) (see #P1053)
+020  RW  scratch RAM (64 bytes) (see #P1002)
+060  RW  sequencer control  register (SEQCTL)	(see #P0989)
+061  RW  sequencer RAM data register (SEQRAM)
+062w RW  sequencer address  register (SEQADDR) (see #P0990)
+064  RW  accumulator  register (ACCUM)
+065  RW  source index register (SINDEX)
+066  RW  destination index register (DINDEX)
+069  R-  all ones register (ALLONES)
	  always reads as FFh
+06A  R-  all zeros register (ALLZEROS)
	  always reads as 00h
+06B  R-  flags register (FLAGS) (see #P0991)
	  PhaseEngine processor's flags
+06C  R-  source indirect register (SINDIR)
+06D  -W  destination indirect register (DINDIR)
+06E  RW  function 1 register (FUNCTION1)
+06F  R-  "STACK"
+084  RW  DSCommand register (DSCOMMAND) (see #P1054)
+085  RW  bus on/off time register (BUSTIME) (see #P0993)
+086  RW  (AIC-7870) "DSPCISTATUS"
+087  RW  host control register (HCNTRL) (see #P0995)
+088d RW  host address register (HADDR)
+08C  RW  host counter register (HCNT) (3 bytes long)
+090  RW  sequence control block (SCB) pointer register (SCBPTR)
+091  RW  interrupt status register (INTSTAT) (see #P0996)
+092  R-  hard error register (ERROR) (see #P0997)
+092  -W  clear interrupt status register (CLRINT) (see #P0998)
+093  RW  DMA FIFO control register (DFCNTRL)  (see #P0999)
+094  R-  DMA FIFO status  register (DFSTATUS) (see #P1000)
+099  RW  DMA FIFO data register (DFDAT)
+09A  RW  SCB auto-increment register (SCBCNT) (see #P1001)
+09B  RW  queue in FIFO register (QINFIFO)
	  write places the value into the FIFO, read removes
+09C  R-  queue in count register (QINCNT)
	  number of the SCBs in the queue in
+09D  -W  queue out FIFO register (QOUTFIFO)
	  read removes the value from the FIFO
+09E  R-  queue out count register (QOUTCNT)
	  number of the SCBs in the queue out
+0A0  RW  SCB array (32 bytes) (see #P1003)
Note:	AIC-7850 SCSI controllers sporatically get garbage in the MSBs of the
	  queue in/out count registers (QINCNT/QOUTCNT)

Bitfields for AIC-7870 board control register (BRDCTL):
Bit(s)	Description	(Table P1051)
 7	"BRDDAT7"
	(read) (ROM bank 0) internal 68-pin connector (INT68)
	=0 present
	=1 absent
	(read) (ROM bank 1) EPROM present (EPROMPS)
 6	"BRDDAT6"
	(read) (ROM bank 0) internal 50-pin connector (INT50)
	(read) (ROM bank 1) external 68-pin connector (EXT68)
	=0 present
	=1 absent
	(write) wide termination enable
 5	(write) "BRDDAT5"
	ROM bank setting
	=0 select bank 0
	=1 select bank 1
 4	strobe (BRDSTB)
 3	chip select (BRDCS)
 2	"BRDRW"
	=0 write
	=1 read
 1	"BRDCTL1"
 0	"BRDCTL0"
Notes:	accessing this register requires prior setting of bits 3 and 5 of the
	  serial EEPROM control register (SEECTL)
	bit 3 must be set to read/write bits 7-5, and reset afterwards
	bit 4 must be set along with bit 3 for writes, then value must be set
	  into the bits 7-5, and then bit 4 must be reset
	to read from bits 7-6 first perform a write operation of bit 5 in order
	  to select the ROM bank 0, then bit 2 must be set along with bit 3,
	  and then the data can be read
SeeAlso: #P1052

Bitfields for AIC-787x/788x serial EEPROM control register (SEECTL):
Bit(s)	Description	(Table P1052)
 7	"EXTARBACK"
 6	"EXTARBREQ"
 5	serial EEPROM memory port select? (SEEMS)
 4	serial EEPROM ready (SEERDY)
 3	serial EEPROM chip select (SEECS)
 2	serial EEPROM clock (SEECK)
 1	serial EEPROM data out (SEEDO)
 0	serial EEPROM data in  (SEEDI)
Notes:	AIC-7873/7883 use 93C56/93C66 serial EEPROM chips, others use 93C46;
	  93C46 serial EEPROM chips have 1024 bits organized into 64 16-bit
	  words and use 6 bits to address each word, while 93C56/93C66 chips
	  have 2048 bits organized into 128 16-bit words and use 8 bits to
	  address each word
	only the first 32 words of serial EEPROM are used by the Adaptec BIOS
	bits 3-0 are connected to the chip select, clock, data out, and data in
	  pins of the serial EEPROM respectively
	data in pin of the serial EEPROM can be read through the bit 0 of this
	  register after the clock pin goes from high to low
	bit 2 must be pulled high and then low for a minimum of 750 and 250 ns
	  to provide clocking for the EEPROM chip
	bit 2 going from low to high causes the EEPROM chip to sample the data
	  out pin and initiates the next bit to be sent through the data in pin
	bit 3 must be set for a minimum of 1 mcs with the bit 2 goig high and
	  then low for the EEPROM chip to be selected; then the instruction can
	  be sent to the EEPROM chip
	instruction can be terminated by taking the EEPROM chip select pin low,
	  with the bit 2 going high and low
	bit 5 requests access to the memory port; when access is granted, bit 4
	  will be set; during the EEPROM access bit 4 is cleared after writing
	  this register and goes high 800 ns later
SeeAlso: #P1007,#P1051,#P1055,#P1056

Bitfields for SCSI block control register (SBLKCTL):
Bit(s)	Description	(Table P1053)
 7	diagnostic LED enable (DIAGLEDEN)
 6	diagnostic LED on (DIAGLEDON)
 5	auto flush disable (AUTOFLUSHDIS)
 4	reserved
 3	select bus (SELBUS)
	=0 select bus A
	=1 select bus B (SELBUSB)
 2	reserved
 1	"SELWIDE"
 0	reserved
Note:	clearing bits 7-6 will take the card out of diagnostic mode and make
	  the host adapter LED follow bus activity
SeeAlso: #P0988

Bitfields for DSCommand register (DSCOMMAND):
Bit(s)	Description	(Table P1054)
 7	cache threshold enable (CACHETHEN)
 6	data   parity check enable (DPARCKEN)
 5	memory parity check enable (MPARCKEN)
 4	external request lock (EXTREQLCK)
 3-0	reserved

(Table P1055)
Values for the 93C56/93C66 serial EEPROM instructions:
Opcode	     Function  Parameter  Description
0000xxxxxxb  EWDS      -	  disable all programming instructions
0001xxxxxxb  WRAL      D15..D0	  write to all registers
0010xxxxxxb  ERAL      -	  erase all registers
0011xxxxxxb  EWEN      -	  write enable
				  must precede all programming modes
01AAAAAAAAb  WRITE     D15..D0	  write register with address A7..A0
10AAAAAAAAb  READ      -	  read registers starting with address A7..A0
11AAAAAAAAb  ERASE     -	  erase register with address A7..A0
SeeAlso: #P1007,#P1052

Format of the serial EEPROM:
Address	Size	Description	(Table P1056)
 00h  16 WORDs	SCSI ID configuration (see #P1009)
 10h	WORD	BIOS control (see #P1057)
 11h	WORD	host adapter control (see #P1058)
 12h	WORD	bus release time / host adapter ID (see #P1013)
 13h	WORD	maximum targets (see #P1014)
 14h  11 WORDs	reserved
 1Fh	WORD	checksum
SeeAlso: #P1052

Bitfields for the serial EEPROM BIOS control word:
Bit(s)	Description	(Table P1057)
 15-8	reserved
 7	extended translation enabled (CFEXTEND)
 6-5	reserved
 4	support more than 2 drives (CFSM2DRV)
 3	reserved
 2	BIOS enabled (CFBIOSEN)
 1	support removable drives for boot only (CFSUPREMB)
 0	support all removable drives (CFSUPREM)
SeeAlso: #P1056

Bitfields for the serial EEPROM host adapter control word:
Bit(s)	Description	(Table P1058)
 15-7	reserved
 6	reset SCSI bus at IC initialization (CFRESETB)
 5	reserved
 4	SCSI parity (CFSPARITY)
 3	SCSI high byte termination (CFWSTERM)
 2	SCSI low  byte termination (CFSTERM)
 1	(Ultra SCSI) Ultra SCSI speed enable (CFULTRAEN)
 0	reserved
SeeAlso: #P0600,#P0979,#P0980,#P0994,#P1056
--------p-Pxxxx------------------------------
PORT xxxx - AMD-645 - Power Management Registers
Range:	on any 256-byte boundary
SeeAlso: #01049

+000w RC  power management status (see #P1059)
+002w RW  power management enable (see #P1060)
+004w RW  power management control (see #P1061)
+006	  unused???
+008d RW  power management timer (24 or 32 bits)
+00C	  unused???
+010d RW  processor power management control (see #P1062)
+014  R-  "P_LVL2" processor level 2 -- reading switches to C2 power state
+015  R-  "P_LVL3" processor level 3 -- reading switches to C3 power state
+016	  unused???
+020w RC  general purpose status (see #P1063)
+022w RW  general purpose SCI enable (see #P1064)
+024w RW  general purpose SMI enable (see #P1065)
+026w RW  power supply control (see #P1066)
+028w RC  global power management status (see #P1067)
+02Aw RW  global power management enable (see #P1068)
+02Cw RW  global power management control (see #P1069)
+02E	  unused???
+02F  RW  SMI command
	writing this port sets the SW_SMI_STS bit (see #P1067,#P1068)
+030d RC  primary activity detection status (see #P1070)
+034d RW  primary activity detection enable (see #P1071)
+038d RW  general purpose timer reload enable (see #P1072)
+03C	  unused???
+040  RW  control of general-purpose I/O direction (see #P1073)
+041	  ???
+042  RW  output value for GPIO port (see #P1074)
+043  RW  ???
+044  RW  input value for GPIO port (see #P1075)
+045  RW  ???
+046w RW  output value for general-purpose output port
+048w RW  input value for general-purpose input port

Bitfields for AMD-645 Power Management Control Status:
Bit(s)	Description	(Table P1059)
 15	wakeup request -- system will transition from suspend to normal working
 14-12	reserved (0)
 11	power button override (set when PWRBTN# asserted for more than 4 sec)
	system will transition into "soft off" power state
 10	RTC alarm occurred
 9	reserved (0)
 8	"PB_STS" power button -- PWRBTN# asserted (but for less than 4 sec)
 7-6	reserved (0)
 5	"GBL_STS" Global Status
	set by hardware when "BIOS_RLS" set; "BIOS_RLS" cleared by hardware
	  when this bit cleared
 4	system bus requested by any bus master
 3-1	reserved (0)
 0	ACPI timer carried into highest bit
Note:	all bits are write-clear: write a 1 bit to acknowledge the
	  status and clear that bit
SeeAlso: #P1060,MEM xxxxh:xxx0h"ACPI"

Bitfields for AMD-645 Power Management Enable register:
Bit(s)	Description	(Table P1060)
 15-11	reserved (0)
 10	enable SCI/SMI on RTC alarm
 9	reserved (0)
 8	enable SCI/SMI when PB_STS set (see #P1059 bit 8)
 7-6	reserved
 5	enable SCI/SMI when GBL_STS set (see #P1059 bit 5)
 4-1	reserved
 0	enable SCI/SMI when ACPI timer carries
SeeAlso: #P1059,#P1061,MEM xxxxh:xxx0h"ACPI"

Bitfields for AMD-645 Power Management Control register:
Bit(s)	Description	(Table P1061)
 15-14	reserved (0)
 13	(write) force transition into sleep state (bits 12-10) when set
	(read) always 0
 12-10	sleep type
	000 "soft off" (suspend-to-disk)
	010 power-on suspend
	0x1 reserved
	1xx reserved
 9-3	reserved
 2	"GLB_RLS" release SCI/SMI lock
	when set, BIOS_STS bit set by hardware; when BIOS_STS cleared,
	  hardware clears this bit
 1	enable transition from suspend to normal working state on bus master
	  request
 0	power management event interrupt type
	0 generate SMI
	1 generate SCI
SeeAlso: #P1059,#P1060

Bitfields for AMD-645 Processor Power Management Control register:
Bit(s)	Description	(Table P1062)
 31-5	reserved (0)
 4	enable clock throttling
	0 = suspend processor on reading P_LVL2 port at offset 14h
	1 = throttle clock by modulating STPCLK# on reading P_LVL2
 3-1	throttling duty cycle (proportion of time STPCLK# is asserted)
	000 reserved
	001 0 - 1/8
	010 1/8 - 2/8
	...
	111 6/8 - 7/8
 0	reserved (0)
SeeAlso: #P1061,#P1062

Bitfields for AMD-645 General Purpose Status register:
Bit(s)	Description	(Table P1063)
 15-10	reserved (0)
 9	"USB_STS"	USB peripheral generated resume event
 8	"RI_STS"	ring detected (RI# asserted)
 7	"EXT7_STS"	EXTSMI7# pin toggled
 6-0	"EXT?_STS"	EXTSMI6# - EXTSMI0# pins toggled
SeeAlso: #P1061,#P1064

Bitfields for AMD-645 General Purpose SCI Enable register:
Bit(s)	Description	(Table P1064)
 15-10	reserved (0)
 9	enable SCI when USB_STS bit becomes set
 8	enable SCI when RI_STS bit becomes set
 7-0	enable SCI when EXT?_STS bit becomes set
SeeAlso: #P1063,#P1065

Bitfields for AMD-645 General Purpose SMI Enable register:
Bit(s)	Description	(Table P1065)
 15-10	reserved (0)
 9	enable SMI when USB_STS bit becomes set
 8	enable SMI when RI_STS bit becomes set
 7-0	enable SMI when EXT?_STS bit becomes set
SeeAlso: #P1063,#P1064,#P1066

Bitfields for AMD-645 Power Supply Control register:
Bit(s)	Description	(Table P1066)
 15-11	reserved (0)
 10	enable setting of RI_STS bit to turn on power
 9	set PB_STS bit to resume from suspend
 8	set RTC_STS bit to resume from suspend on RTC alarm
 7-1	reserved (0)
 0	enable setting of EXT0_STS bit to resume from suspend
SeeAlso: #P1063,#P1067,#P1068

Bitfields for AMD-645 PM Global Status register:
Bit(s)	Description	(Table P1067)
 15-7	reserved (0)
 6	"SW_SMI_STS" SMI_CMD port has been written
 5	"BIOS_STS" set whenever GLB_RLS bit is set; GLB_RLS is cleared when
	  this bit is cleared
 4	legacy USB event occurred
 3	GP1 timer timed out
 2	GP0 timer timed out
 1	secondary event timer timed out
 0	"PACT_STS" an enabled primary system activity has occurred (see #P1071)
Note:	this register is write-clear: writing a 1 to a bit clears that bit
SeeAlso: #P1066

Bitfields for AMD-645 PM Global Enable register:
Bit(s)	Description	(Table P1068)
 15-7	reserved (0)
 6	enable SMI when SMI_CMD port is written
 5	enable SMI when BIOS_STS bit set (see #P1067)
 4	enable SMI on legacy USB events
 3	enable SMI when GP1 timer times out
 2	enable SMI when GP0 timer times out
 1	enable SMI when secondary event timer times out
 0	enable SMI on occurrence of any primary activity
SeeAlso: #P1066,#P1067,#P1069

Bitfields for AMD-645 PM Global Control ("GLB_CTL") register:
Bit(s)	Description	(Table P1069)
 15-9	reserved
 8	SMI is active
 7-5	reserved
 4	SMI lock enabled (write-clear)
	(must be cleared before bit 8 can be cleared and the next SMI allowed)
 3	reserved
 2	type of power button triggering
	0 generate SCI/SMI on PWRBTN# asserted
	1 generate SCI/SMI when PWRBTN# becomes deasserted
	(must be clear to comply with ACPI v0.9, but setting it avoids the
	  situation where holding the power button for four seconds first wakes
	  the system and then puts it into the soft-off state)
 1	"BIOS_RLS" used by legacy software to release the SCI/SMI lock; when
	  set, the GBL_STS bit is set by hardware; when GBL_STS is cleared,
	  this bit is cleared by hardware
 0	enable SMI generation
SeeAlso: #P1066,#P1067,#P1068,MEM xxxxh:xxx0h"ACPI"

Bitfields for AMD-645 PM Primary Activity Detect Status register:
Bit(s)	Description	(Table P1070)
 31-8	reserved (0)
 7	keyboard controller accessed via PORT 0060h
 6	serial port accessed (via PORT 03F8h-03FFh, 02F8h-02FFh, 03E8h-03EFh,
	  or PORT 02E8h-02EFh)
 5	parallel port accessed (via PORT 0278h-027Fh or PORT 0378h-037Fh)
 4	video controller accessed
 3	IDE or Floppy controller accessed
 2	reserved (0)
 1	a primary interrupt occurred (see #01049 [offset 44h])
 0	ISA busmaster or DMA activity occurred
Note:	this register is write-clear: write a 1 to a bit to clear it
SeeAlso: #P1071,#P1069

Bitfields for AMD-645 PM Primary Activity Detect Enable register:
Bit(s)	Description	(Table P1071)
 31-8	reserved (0)
---set PACT_STS (see #P1067) whenever:
 7	keyboard controller is accessed via PORT 0060h
 6	serial port is accessed (via PORT 03F8h-03FFh, 02F8h-02FFh,
	  PORT 03E8h-03EFh, or PORT 02E8h-02EFh)
 5	parallel port is accessed (via PORT 0278h-027Fh or PORT 0378h-037Fh)
 4	video controller is accessed
 3	IDE or Floppy controller is accessed
 2	reserved (0)
 1	a primary interrupt occurrs (see #01049 [offset 44h])
 0	ISA busmaster or DMA activity occurrs
SeeAlso: #P1070,#P1069

Bitfields for AMD-645 GP Timer Reload Enable register:
Bit(s)	Description	(Table P1072)
 31-8	reserved (0)
 7	reload GP1 whenever keyboard controller is accessed
 6	reload GP1 whenever a serial port is accessed
 5	reserved (0)
 4	reload GP1 whenever video controller is accessed
 3	reload GP1 whenever IDE or floppy controller is accessed
 2-1	reserved (0)
 0	reload GP0 whenever a primary activity is detected
SeeAlso: #P1071,#P1070

Bitfields for AMD-645 GPIO Direction Control register:
Bit(s)	Description	(Table P1073)
 7-5	reserved (0)
 4	direction of GPIO4 (0 = input, 1 = output)
	this bit sets Pin136, which is always output if configured as GPO_WE#
 3	direction of GPIO3 (0 = input, 1 = output)
	this bit sets Pin92, which is always an output if configured as GPI_RE#
 2	direction of GPIO2/I2CD1 (0 = input, 1 = output)
 1	direction of GPIO1/I2CD2 (0 = input, 1 = output)
 0	direction of GPIO0 (0 = input, 1 = output)
SeeAlso: #P1071,#P1074

Bitfields for AMD-645 GPIO Port Output Value register:
Bit(s)	Description	(Table P1074)
 7-5	reserved
 4	value for GPIO4 pin (ignored if pin configured as GPO_WE#)
 3	value for GPIO3 pin (ignored if pin configured as GPI_RE#)
 2	value for GPIO2/I2CD1 pin
 1	value for GPIO1/I2CD2 pin
 0	value for GPIO0 pin
Note:	while these bits can be read back, they only indicate the values which
	  are driven onto the pins if configured for output; to read the actual
	  input values, use the "input value" register at offset 44h
	  (see #P1075)
SeeAlso: #P1075

Bitfields for GPIO Port Input Value (EXTSMI_VAL) register:
Bit(s)	Description	(Table P1075)
 7	(if GPIO3 set to input) current EXTSMI7# on XD7 (Pin122)
 6	(if GPIO3 set to input) current EXTSMI6# on XD6 (Pin121)
 5	(if GPIO3 set to input) current EXTSMI5# on XD5 (Pin119)
 4	(if GPIO4 set to input) current EXTSMI4# on XD4 (Pin118)
	(if GPIO4 set to output) current EXTSMI4# on GPIO4 (Pin136)
 3	(if GPIO3 set to input) current EXTSMI3# on XD3 (Pin117)
	(if GPIO3 set to output) current EXTSMI3# on GPIO3 (Pin92)
 2	GPIO2 input value
 1	GPIO1 input value
 0	GPIO0 input value
SeeAlso: #P1074
--------X-Pxxxx------------------------------
PORT xxxx - AMD-645 - USB
SeeAlso: #01046 at INT 1A/AX=B10Ah/SF=1106h
Note:	further details are supposedly in the UHCI v1.1 standard

+000w ?W  USB command
+002w R?  USB status
+004w ?W  USB interrupt enable
+006w ??  frame number
+008d ??  frame list base address
+00C  ??  Start of Frame Modify
+00D	unused???
+010w RW  Port 1 Status/Control
+012w RW  Port 2 Status/Control
----------Pxxxx------------------------------
PORT xxxx - Ensoniq AudioPCI ES1370 - CONTROL REGISTERS
Range:	anywhere on 64 byte boundary

+000d RW  interrupt/chip select control register (see #P1076)
+004d R-  interrupt/chip select status register (see #P1077)
+008  RW  UART data register (MIDI data)
+009  -W  UART control register (see #P1078)
+009  R-  UART status register (see #P1079)
+00A  RW  UART reserved register (see #P1080)
+00Cd RW  memory page register (see #P1081)
+010d -W  CODEC write register (see #P1082)
+020d RW  serial interface control register (see #P1083)
+024d RW  DAC1 channel sample count register (see #P1084)
+028d RW  DAC2 channel sample count register (see #P1084)
+02Cd RW  ADC channel sample count register (see #P1084)
+030d RW  internal memory 1 (see #P1085)
+034d RW  internal memory 2 (see #P1086)
+038d RW  internal memory 3 (see #P1087)
+03Cd RW  internal memory 4 (see #P1088)

Bitfields for Ensoniq ES1370/ES1371 interrupt/chip select control register:
Bit(s)	Description	(Table P1076)
---AudioPCI ES1370---
 31	record buffer transfer disable (ADC stop)
 30	(bit 0 = 0) general purpose output
	(bit 0 = 1) external IRQ output
 29	reserved
 28-16	programmable clock divide ratio (DAC2)
---AudioPCI-97 ES1371---
 31-26	reserved
 25-24	joystick base I/O address
	00 = 200h
	01 = 208h
	10 = 210h
	11 = 218h
 23-20	GPIO pin 3-0 (read-only)
 19-16	GPIO pin 3-0 output
------
 15	MPEG data format
	0 = Sony (lrclk high = left channel; data left justified)
	1 = I2S (lrclk low = left channel; data 1 bit clock delayed)
---AudioPCI ES1370---
 14	CODEC DAC (DAC2) source
	0 = programmable clock generator
	1 = MPEG clocks
 13-12	fixed frequency clock generator frequency (DAC1)
	00 = 5.512 KHz
	01 = 11.025 KHz
	10 = 22.05 KHz
	11 = 44.1 KHz
 11	CODEC DACs synchronous with fixed frequency clock generator
---AudioPCI-97 ES1371---
 14	AC97 warm reset
 13	CCB record transfer disable
 12	power management level change interrupt enable
 11	record channel source
	0 = CODEC ADC
	1 = I2S
------
 10	CCB voice interrupts enable
---AudioPCI ES1370---
 9	record channel source in serial module
	0 = CODEC ADC
	1 = MPEG
 8	general purpose output
---AudioPCI-97 ES1371---
 9-8	current power down level
	00-11 = D0-D3
------
 7	memory bus request enable (disables memory access) (test purposes only)
 6	DAC1 (CODEC FM DAC) playback channel enable
 5	DAC2 (CODEC DAC) playback channel enable
 4	CODEC ADC record channel enable
 3	UART enable
 2	joystick enable
---AudioPCI ES1370---
 1	CODEC interface enable
 0	PCI serr signal disable
---AudioPCI-97 ES1371---
 1	crystal clock input disable
 0	PCI clock input disable
------
Note:	this register is addressable as byte, word and dword

Bitfields for Ensoniq ES1370/ES1371 interrupt/chip select status register:
Bit(s)	Description	(Table P1077)
---AudioPCI ES1370---
 31	DAC1, DAC2, ADC, UART or CCB interrupt occurred
 30-11	reserved
 10	CODEC busy or register write in progress
 9	CODEC busy
 8	CODEC register write in progress
 7	reserved
 6-5	CCB voice code (if bit 4 = 1)
	00 = DAC1
	01 = DAC2
	10 = ADC
	11 = reserved
---AudioPCI-97 ES1371---
 31	DAC1, DAC2, ADC, UART, CCB or power management interrupt occurred
 30-9	reserved
 8	CODEC synchronization error
 7-6	CCB voice code (if bit 4 = 1)
	00 = DAC1
	01 = DAC2
	10 = ADC
	11 = reserved
 5	power level interrupt status
------
 4	CCB interrupt status
 3	UART interrupt status
 2	DAC1 playback channel interrupt status
 1	DAC2 playback channel interrupt status
 0	ADC record channel interrupt status

Bitfields for Ensoniq ES1370/ES1371 UART control register:
Bit(s)	Description	(Table P1078)
 7	UART receiver interrupt enable
 6-5	UART transmitter operation
	01 = Txrdy interrupts enabled
 4-2	reserved
 1-0	UART control
	11 = software reset

Bitfields for Ensoniq ES1370/ES1371 UART status register:
Bit(s)	Description	(Table P1079)
 7	UART receiver interrupt status
 6-3	reserved
 2	UART transmitter interrupt status
 1	UART transmitter ready
 0	UART receiver ready

Bitfields for Ensoniq ES1370/ES1371 UART reserved register:
Bit(s)	Description	(Table P1080)
 7-1	reserved
 0	UART test mode enable (UART clock switched to PCI bus clock)

Bitfields for Ensoniq ES1370/ES1371 memory page register:
Bit(s)	Description	(Table P1081)
 31-4	reserved
 3-0	memory page select (accessed in registers 30h-3Fh)
	0000 = DAC1 sample bytes 15-0 (lower half buffer)
	0001 = DAC1 sample bytes 31-16
	0010 = DAC1 sample bytes 47-32 (upper half buffer)
	0011 = DAC1 sample bytes 63-48
	0100 = DAC2 sample bytes 15-0 (lower half buffer)
	0101 = DAC2 sample bytes 31-16
	0110 = DAC2 sample bytes 47-32 (upper half buffer)
	0111 = DAC2 sample bytes 63-48
	1000 = ADC sample bytes 15-0 (lower half buffer)
	1001 = ADC sample bytes 31-16
	1010 = ADC sample bytes 47-32 (upper half buffer)
	1011 = ADC sample bytes 63-48
	1100 = DAC1/DAC2 frame information
	1101 = ADC frame information
	1110 = UART FIFO
	1111 = UART FIFO
Note:	this register is addressable as byte, word and dword

Bitfields for Ensoniq ES1370/ES1371 CODEC write register:
Bit(s)	Description	(Table P1082)
---AudioPCI ES1370---
 31-16	reserved
 15-8	CODEC register index
---AudioPCI-97 ES1371---
 31-24	reserved
 23	AC97 CODEC read/write
	0 = write
	1 = read
 22-16	AC97 CODEC register index
------
 7-0	CODEC register data
---index 16h---
 1	0 = CODEC power down
------
Note:	(AudioPCI ES1370) this register is addressable as word and dword

Bitfields for Ensoniq ES1370/ES1371 serial interface control register:
Bit(s)	Description	(Table P1083)
 31-22	reserved
 22	(ES1371) DAC test mode enable (selects I2S lrclk input as  source for
	  playback and record channels)
 21-19	sample address counter loop binary offset
 18-16	sample address counter channel start/restart binary offset
 15	ADC channel action when sample count reaches zero
	0 = loop (interrupt set, keep recording)
	1 = stop (inteerupt set, stop recording)
 14	DAC2 channel action when sample count reaches zero
	0 = loop (interrupt set, keep playing)
	1 = stop (inteerupt set, play last sample)
 13	DAC1 channel action when sample count reaches zero (same values as
	  bit 14)
 12	DAC2 channel playback pause
 11	DAC1 channel playback pause
 10	ADC interrupt enable
 9	DAC2 interrupt enable
 8	DAC1 interrupt enable
 7	DAC1 sample counter reload
 6	DAC2 sample counter reload
 5-4	ADC channel data format
	00 = 8-bit mono
	01 = 8-bit stereo
	10 = 16-bit mono
	11 = 16-bit stereo
 3-2	DAC2 channel data format (same values as bits 5-4)
 1-0	DAC1 channel data format (same values as bits 5-4)
Note:	this register is addressable as byte, word and dword

Bitfields for Ensoniq ES1370/ES1371 DAC1/2/ADC channel sample count register:
Bit(s)	Description	(Table P1084)
 31-16	sample counter current value (read-only)
 15-0	sample counter (samples - 1)
Note:	these registers are addressable as word and dword

Bitfields for Ensoniq ES1370/ES1371 internal memory 1:
Bit(s)	Description	(Table P1085)
---register +00Ch bits 3-0 = 0000---
 31-0	DAC1 sample bytes 3-0
---register +00Ch bits 3-0 = 0001---
 31-0	DAC1 sample bytes 19-16
---register +00Ch bits 3-0 = 0010---
 31-0	DAC1 sample bytes 35-32
---register +00Ch bits 3-0 = 0011---
 31-0	DAC1 sample bytes 51-48
---register +00Ch bits 3-0 = 0100---
 31-0	DAC2 sample bytes 3-0
---register +00Ch bits 3-0 = 0101---
 31-0	DAC2 sample bytes 19-16
---register +00Ch bits 3-0 = 0110---
 31-0	DAC2 sample bytes 35-32
---register +00Ch bits 3-0 = 0111---
 31-0	DAC2 sample bytes 51-48
---register +00Ch bits 3-0 = 1000---
 31-0	ADC sample bytes 3-0
---register +00Ch bits 3-0 = 1001---
 31-0	ADC sample bytes 19-16
---register +00Ch bits 3-0 = 1010---
 31-0	ADC sample bytes 35-32
---register +00Ch bits 3-0 = 1011---
 31-0	ADC sample bytes 51-48
---register +00Ch bits 3-0 = 1100---
 31-0	DAC1 sample buffer memory address
---register +00Ch bits 3-0 = 1101---
 31-0	ADC sample buffer memory address
---register +00Ch bits 3-0 = 1110---
 31-9	reserved
 8	UART data valid
 7-0	UART data received through MIDI interface
---register +00Ch bits 3-0 = 1111---
 31-9	reserved
 8	UART data valid
 7-0	UART data received through MIDI interface
------
SeeAlso: #P1086

Bitfields for Ensoniq ES1370/ES1371 internal memory 2:
Bit(s)	Description	(Table P1086)
---register +00Ch bits 3-0 = 0000---
 31-0	DAC1 sample bytes 7-4
---register +00Ch bits 3-0 = 0001---
 31-0	DAC1 sample bytes 23-20
---register +00Ch bits 3-0 = 0010---
 31-0	DAC1 sample bytes 39-36
---register +00Ch bits 3-0 = 0011---
 31-0	DAC1 sample bytes 55-52
---register +00Ch bits 3-0 = 0100---
 31-0	DAC2 sample bytes 7-4
---register +00Ch bits 3-0 = 0101---
 31-0	DAC2 sample bytes 23-20
---register +00Ch bits 3-0 = 0110---
 31-0	DAC2 sample bytes 39-36
---register +00Ch bits 3-0 = 0111---
 31-0	DAC2 sample bytes 55-52
---register +00Ch bits 3-0 = 1000---
 31-0	ADC sample bytes 7-4
---register +00Ch bits 3-0 = 1001---
 31-0	ADC sample bytes 23-20
---register +00Ch bits 3-0 = 1010---
 31-0	ADC sample bytes 39-36
---register +00Ch bits 3-0 = 1011---
 31-0	ADC sample bytes 55-52
---register +00Ch bits 3-0 = 1100---
 31-16	DAC1 dwords transferred
 15-0	DAC1 dwords in buffer - 1
---register +00Ch bits 3-0 = 1101---
 31-16	ADC dwords transferred
 15-0	ADC dwords in buffer - 1
---register +00Ch bits 3-0 = 1110---
 31-9	reserved
 8	UART data valid
 7-0	UART data received through MIDI interface
---register +00Ch bits 3-0 = 1111---
 31-9	reserved
 8	UART data valid
 7-0	UART data received through MIDI interface
------
SeeAlso: #P1085,#P1087

Bitfields for Ensoniq ES1370/ES1371 internal memory 3:
Bit(s)	Description	(Table P1087)
---register +00Ch bits 3-0 = 0000---
 31-0	DAC1 sample bytes 11-8
---register +00Ch bits 3-0 = 0001---
 31-0	DAC1 sample bytes 27-24
---register +00Ch bits 3-0 = 0010---
 31-0	DAC1 sample bytes 43-40
---register +00Ch bits 3-0 = 0011---
 31-0	DAC1 sample bytes 59-56
---register +00Ch bits 3-0 = 0100---
 31-0	DAC2 sample bytes 11-8
---register +00Ch bits 3-0 = 0101---
 31-0	DAC2 sample bytes 27-24
---register +00Ch bits 3-0 = 0110---
 31-0	DAC2 sample bytes 43-40
---register +00Ch bits 3-0 = 0111---
 31-0	DAC2 sample bytes 59-56
---register +00Ch bits 3-0 = 1000---
 31-0	ADC sample bytes 11-8
---register +00Ch bits 3-0 = 1001---
 31-0	ADC sample bytes 27-24
---register +00Ch bits 3-0 = 1010---
 31-0	ADC sample bytes 43-40
---register +00Ch bits 3-0 = 1011---
 31-0	ADC sample bytes 59-56
---register +00Ch bits 3-0 = 1100---
 31-0	DAC2 sample buffer memory address
---register +00Ch bits 3-0 = 1101---
 31-0	reserved
---register +00Ch bits 3-0 = 1110---
 31-9	reserved
 8	UART data valid
 7-0	UART data received through MIDI interface
---register +00Ch bits 3-0 = 1111---
 31-9	reserved
 8	UART data valid
 7-0	UART data received through MIDI interface
------
SeeAlso: #P1086,#P1088

Bitfields for Ensoniq ES1370/ES1371 internal memory 4:
Bit(s)	Description	(Table P1088)
---register +00Ch bits 3-0 = 0000---
 31-0	DAC1 sample bytes 15-12
---register +00Ch bits 3-0 = 0001---
 31-0	DAC1 sample bytes 31-28
---register +00Ch bits 3-0 = 0010---
 31-0	DAC1 sample bytes 47-44
---register +00Ch bits 3-0 = 0011---
 31-0	DAC1 sample bytes 63-60
---register +00Ch bits 3-0 = 0100---
 31-0	DAC2 sample bytes 15-12
---register +00Ch bits 3-0 = 0101---
 31-0	DAC2 sample bytes 31-28
---register +00Ch bits 3-0 = 0110---
 31-0	DAC2 sample bytes 47-44
---register +00Ch bits 3-0 = 0111---
 31-0	DAC2 sample bytes 63-60
---register +00Ch bits 3-0 = 1100---
 31-16	DAC2 dwords transferred
 15-0	DAC2 dwords in buffer - 1
---register +00Ch bits 3-0 = 1101---
 31-0	reserved
---register +00Ch bits 3-0 = 1110---
 31-9	reserved
 8	UART data valid
 7-0	UART data received through MIDI interface
---register +00Ch bits 3-0 = 1111---
 31-9	reserved
 8	UART data valid
 7-0	UART data received through MIDI interface
------
SeeAlso: #P1087
----------Pxxxx------------------------------
PORT xxxx - Ensoniq AudioPCI-97 ES1371 - CONTROL REGISTERS
Range:	anywhere on 64 byte boundary

+000d RW  interrupt/chip select control register (see #P1076)
+004d R-  interrupt/chip select status register (see #P1077)
+008  RW  UART data register (MIDI data)
+009  -W  UART control register (see #P1078)
+009  R-  UART status register (see #P1079)
+00A  RW  UART reserved register (see #P1080)
+00Cd RW  memory page register (see #P1081)
+010d RW  sample rate converter interface register (see #P1089)
+014d -W  CODEC write register (see #P1082)
+014d R-  CODEC read register (see #P1090)
+018d RW  legacy control/status register (see #P1091)
+020d RW  serial interface control register (see #P1083)
+024d RW  DAC1 channel sample count register (see #P1084)
+028d RW  DAC2 channel sample count register (see #P1084)
+02Cd RW  ADC channel sample count register (see #P1084)
+030d RW  internal memory 1 (see #P1085)
+034d RW  internal memory 2 (see #P1086)
+038d RW  internal memory 3 (see #P1087)
+03Cd RW  internal memory 4 (see #P1088)

Bitfields for Ensoniq AudioPCI-97 ES1371 sample rate converter interface:
Bit(s)	Description	(Table P1089)
 31-25	sample rate converter RAM address
 24	sample rate converter read/write control
 23	sample rate converter busy (read-only)
 22	sample rate converter disable
 21	playback channel 1 accumulator update disable
 20	playback channel 2 accumulator update disable
 19	record channel accumulator update disable
 18-16	reserved
 15-0	sample rate converter RAM data

Bitfields for Ensoniq AudioPCI-97 ES1371 CODEC read register:
Bit(s)	Description	(Table P1090)
 31	AC97 CODEC data ready
 30	AC97 CODEC register access in progress
 29-24	reserved
 23	AC97 CODEC read/write
	0 = write
	1 = read
 22-16	AC97 CODEC register index
 7-0	AC97 CODEC register data

Bitfields for Ensoniq AudioPCI-97 ES1371 legacy control/status register:
Bit(s)	Description	(Table P1091)
 31	joystick timing
	0 = ISA
	1 = fast
 30	host interrupt blocking enable ???
 29	Sound Blaster capture address range
	0 = 220h-22Fh
	1 = 240h-24Fh
 28-27	SoundScape base register capture address range
	00 = 320h-327h
	01 = 330h-337h
	10 = 340h-347h
	11 = 350h-357h
 26-25	CODEC capture address range
	00 = 530h-537h
	01 = reserved
	10 = E80h-E87h
	11 = F40h-F47h
 24	force interrupt
 23	slave DMA controller event capture enable (address range C0h-DFh)
 22	slave interrupt controller event capture enable (address range A0h-A1h)
 21	master DMA controller event capture enable (address range 0h-Fh)
 20	master interrupt controller event capture enable (address range
	  20h-21h)
 19	AdLib register event capture enable (address range 388h-38Bh)
 18	Sound Blaster register event capture enable (address range selected by
	  bit 29)
 17	CODEC event capture enable (address range selected by bits 26-25)
 16	SoundScape base address register event capture enable (address range
	  selected by bits 28-27)
 15-11	reserved
 10-8	captured event (read-only)
	000 = SoundScape base address
	001 = CODEC
	010 = Sound Blaster register
	011 = AdLib register
	100 = master interrupt controller
	101 = master DMA controller
	110 = slave interrupt controller
	111 = slave DMA controller
 7-3	captured event I/O address bits 4-0 (read-only)
 2	captured event read/write (read-only)
	0 = read
	1 = write
 1	reserved
 0	interrupt flag (write to reset)
	0 = interrupt occurred
	0 = interrupt not occurred
Note:	this register is addressable as byte, word and dword
--------d-Pxxxx------------------------------
PORT xxxx - Intel 82371, OPTi "Vendetta" (82C750) - Bus Master IDE Registers

+000  RW  command register, primary channel (see #P1092)
+002  Rw  status register, primary channel (see #P1093)
+004d RW  IDE descriptor table pointer, primary channel (see #P1094)
+008  RW  command register, secondary channel (see #P1092)
+00A  Rw  status register, secondary channel (see #P1093)
+00Cd RW  IDE descriptor table pointer, secondary channel (see #P1094)

Bitfields for Intel 82371 Bus Master IDE command register:
Bit(s)	Description	(Table P1092)
 7-4	reserved
 3	bus master read/write control
	=0 read
	=1 write
 2-1	reserved
 0	start/stop bus master
	=1 start
	=0 stop
SeeAlso: #P1093,#P1094

Bitfields for Bus Master IDE status register:
Bit(s)	Description	(Table P1093)
 7	(Intel) reserved (0)
	(OPTI "Vendetta") both channels operable at same time (read-only)
 6	drive 1 is DMA-capable
 5	drive 0 is DMA_capable
 4-3	reserved
 2	IDE interrupt pending
	write 1 to this bit to clear it
 1	IDE DMA error
	write 1 to this bit to clear it
 0	bus master IDE active (read-only)
SeeAlso: #P1092,#P1094

Bitfields for Bus Master IDE descriptor table pointer register:
Bit(s)	Description	(Table P1094)
 31-2	descriptor table base address bits 31-2
 1-0	reserved (0)
Notes:	(Intel 82371) the descriptor table must not cross a 4K boundary
	(OPTi "Vendetta") the descriptor table must not cross a 64K boundary
SeeAlso: #P1092,#P1093
----------Pxxxx------------------------------
PORT xxxx - Intel 82371SB - USB Host I/O Registers
InstallCheck: see #01215 at INT 1A/AX=B10Ah
SeeAlso: #01215

+000w RW  USB command register (see #P1095)
+002w Rw  USB status (see #P1096)
+004w RW  USB interrupt enable (see #P1097)
+006w RW  Frame Number (see #P1098)
+008d RW  Frame List Base Address
	   (bits 11-0 must be written as zeros)
+00C  RW  Start of Frame Modify (see #P1099)
+010w RW  port 1 status/control (see #P1100)
+012w RW  port 2 status/control (see #P1100)

Bitfields for Intel 82371SB USB command register:
Bit(s)	Description	(Table P1095)
 15-8	reserved
 7	maximum packet size (0=32 bytes, 1=64 bytes)
 6	Host Controller has been configured (set by software)
 5	software debug mode
 4	force global resume
 3	enter global suspend mode
 2	global reset
 1	host controller reset
 0	run/stop schedule (0=stop, 1=run)
SeeAlso: #P1096

Bitfields for Intel 82371SB USB status register:
Bit(s)	Description	(Table P1096)
 15-6	reserved
 5	host controller halted
 4	host controller process error
 3	PCI bus error
 2	resume received
 1	USB error interrupt
 0	USB interrupt
Note:	to clear a bit in this register, write a 1 to it
SeeAlso: #P1095

Bitfields for Intel 82371SB USB interrupt enable register:
Bit(s)	Description	(Table P1097)
 15-4	reserved
 3	enable short packet interrupts
 2	enable Interrupt On Complete
 1	enable Resume
 0	enable Timeout/CRC
SeeAlso: #P1096,#P1098

Bitfields for Intel 82371SB Frame Number register:
Bit(s)	Description	(Table P1098)
 15-11	reserved
 10-0	Frame List Current Index/Frame Number
	incremented at end of each time frame (~1ms)
Note:	only WORD writes are allowed to this register
SeeAlso: #P1095,#P1097

Bitfields for Intel 82371SB Start of Frame Modify register:
Bit(s)	Description	(Table P1099)
 7	reserved
 6-0	SOF timing value (default 64)
Note:	SOF cycle time equals 11936+timing value
SeeAlso: #P1095

Bitfields for Intel 82371SB Port 1/2 status/control register:
Bit(s)	Description	(Table P1100)
 15-13	reserved (0)
 12	suspend port
 11-10	reserved
 9	port in Reset State
 8	low-speed device is attached (read-only)
 7	reserved (1)
 6	resume detected (read-only)
 5-4	line status (read-only)
	bit 4: D+ signal line
	bit 5: D- signal line
 3	port enabled/disabled status has changed
	write 1 to this bit to clear it
 2	port is enabled
 1	connect status has changed
	write 1 to this bit to clear it
 0	current connect status (read-only)
Note:	only WORD writes are permitted to this register
SeeAlso: #P1095
--------!---CREDITS--------------------------
Wim Osterholt		<wim@djo.wtm.tudelft.nl>		Original File
Chuck Proctor		<71534.2302@CompuServe.COM>
Richard W. Watson	<73042.1420@CompuServe.COM>
Matthias Paul		<mpaul@ibh.rwth-aachen.de>
Serguei Shtyliov	<serge.fido@coudert.msk.ru>		Xirlink XL-22x
Serguei Shtyliov	<serge.fido@coudert.msk.ru>		TMC-16x0 SCSI
Serguei Shtyliov	<serge.fido@coudert.msk.ru>		AHA-154x SCSI
								MPU-401 MIDI

Some of the information in this list was extracted from Frank van Gilluwe's
_The_Undocumented_PC_, a must-have book for anyone programming down to the
"bare metal" of a PC.

Some of the information in this list from the shareware version of Dave
Williams' DOSREF, v3.0.

8514/A hardware ports found in FractInt v18.0 source file FR8514A.ASM

Compaq QVision info from the _COMPAQ_QVision_Graphics_System_Technical_
_Reference_Guide_, second edition (October 1993).  Compaq part number
073A/0693.  Much more to come!

AMI keyboard controller PORT 0064h commands from the American Megatrends, Inc.
_Version_KF_and_KH_Keyboard_Controller_BIOS_Reference_, available on the
AMI BBS and american.megatrends.com as KFKHMAN.ZIP.

Various chipset infos from "Het BIOS Boekje" 2nd edition, by Alle Metzlar,
ISBN 90-72260-59-7 (1995).

ATA-3 info from "AT Attachment-3 Interface (ATA-3) Revision 1", dated
April 21, 1995.

Some additional EISA info from _EISA_System_Architecture_ (second edition),
by MindShare, Inc. (Addison-Wesley 1995, ISBN 0-201-40995-X).

AMI BIOS diagnostics codes (port 0080h) from file CHECKPTS on AMI BBS.

Some S3 and additional ATI Mach8/Mach32 info from Richard F. Ferraro's
_Programmer's_Guide_to_the_EGA,_VGA,_and_Super_VGA_Cards_, third edition.

PCnet-ISA info from _Am79C960_PCnet-ISA(tm)_Technical_Manual_, May 1992,
available from www.amd.com as 16850B.PDF; additional details from file
16907B.PDF.

PCnet-SCSI info from _Am79C974 PCnet(tm)-SCSI_Combination_Ethernet_and_SCSI_
_Controller_for_PCI_Systems_, available from www.amd.com as 18681B.PDF.

PCnet-FAST info from _Am79C971 PCnet(tm)-FAST_Single-Chip_Full-Duplex_10/100_
_Mbps_Ethernet_Controller_for_PCI_Local_Bus_, available from www.amd.com as
20550B.PDF.

S.M.A.R.T. information from _Self-Monitoring,_Analysis,_and_Reporting_
_Technology_(S.M.A.R.T.)_(SFF-8035i)_, Revision 2.0, April 1, 1996.
Available as 8035r2_0.PDF from fission.dt.wdc.com/pub/standards/SFF/.

A variety of ports from Frank van Giluwe's _The_Undocumented_PC_, second
edition.

[many more sources listed in BIBLIO.LST]
--------!---Admin----------------------------
Highest Table Number = P1016
--------!---FILELIST-------------------------
Please redistribute all of the files comprising the interrupt list (listed at
the beginning of the list and in INTERRUP.1ST) unmodified as a group, in a
quartet of archives named INTER60A through INTER60D (preferably the original
authenticated PKZIP archives), and the utility and hypertext programs in a trio
of additional archives called INTER60E.ZIP to INTER60G.ZIP.

Copyright (c) 1989,1990,1991,1992,1993,1994,1995,1996,1997,1998,1999 Ralf Brown
--------!---CONTACT_INFO---------------------
Internet: ralf@pobox.com (currently forwards to ralf@telerama.lm.com)
FIDO: Ralf Brown 1:129/26.1